1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "llvm/ADT/SetVector.h"
10 #include "llvm/Analysis/AliasAnalysis.h"
11 #include "llvm/CodeGen/MachineFunctionPass.h"
12 #include "llvm/CodeGen/MachineInstr.h"
13 #include "llvm/CodeGen/MachineRegisterInfo.h"
14 #include "llvm/CodeGen/Passes.h"
15 #include "llvm/CodeGen/TargetInstrInfo.h"
16 #include "llvm/CodeGen/TargetSubtargetInfo.h"
17 #include "llvm/InitializePasses.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/raw_ostream.h"
23 #define DEBUG_TYPE "processimpdefs"
26 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
27 /// for each use. Add isUndef marker to implicit_def defs and their uses.
28 class ProcessImplicitDefs : public MachineFunctionPass {
29 const TargetInstrInfo *TII;
30 const TargetRegisterInfo *TRI;
31 MachineRegisterInfo *MRI;
33 SmallSetVector<MachineInstr*, 16> WorkList;
35 void processImplicitDef(MachineInstr *MI);
36 bool canTurnIntoImplicitDef(MachineInstr *MI);
41 ProcessImplicitDefs() : MachineFunctionPass(ID) {
42 initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
45 void getAnalysisUsage(AnalysisUsage &au) const override;
47 bool runOnMachineFunction(MachineFunction &MF) override;
49 } // end anonymous namespace
51 char ProcessImplicitDefs::ID = 0;
52 char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
54 INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
55 "Process Implicit Definitions", false, false)
57 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addPreserved<AAResultsWrapperPass>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
64 if (!MI->isCopyLike() &&
65 !MI->isInsertSubreg() &&
66 !MI->isRegSequence() &&
69 for (const MachineOperand &MO : MI->operands())
70 if (MO.isReg() && MO.isUse() && MO.readsReg())
75 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
76 LLVM_DEBUG(dbgs() << "Processing " << *MI);
77 Register Reg = MI->getOperand(0).getReg();
79 if (Register::isVirtualRegister(Reg)) {
80 // For virtual registers, mark all uses as <undef>, and convert users to
81 // implicit-def when possible.
82 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
84 MachineInstr *UserMI = MO.getParent();
85 if (!canTurnIntoImplicitDef(UserMI))
87 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
88 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
89 WorkList.insert(UserMI);
91 MI->eraseFromParent();
95 // This is a physreg implicit-def.
96 // Look for the first instruction to use or define an alias.
97 MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
98 MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
100 for (++UserMI; UserMI != UserE; ++UserMI) {
101 for (MachineOperand &MO : UserMI->operands()) {
104 Register UserReg = MO.getReg();
105 if (!Register::isPhysicalRegister(UserReg) ||
106 !TRI->regsOverlap(Reg, UserReg))
108 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
117 // If we found the using MI, we can erase the IMPLICIT_DEF.
119 LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
120 MI->eraseFromParent();
124 // Using instr wasn't found, it could be in another block.
125 // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
126 for (unsigned i = MI->getNumOperands() - 1; i; --i)
127 MI->RemoveOperand(i);
128 LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
131 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
132 /// <undef> operands.
133 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
135 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
136 << "********** Function: " << MF.getName() << '\n');
138 bool Changed = false;
140 TII = MF.getSubtarget().getInstrInfo();
141 TRI = MF.getSubtarget().getRegisterInfo();
142 MRI = &MF.getRegInfo();
143 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
144 assert(WorkList.empty() && "Inconsistent worklist state");
146 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
148 // Scan the basic block for implicit defs.
149 for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
150 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
151 if (MBBI->isImplicitDef())
152 WorkList.insert(&*MBBI);
154 if (WorkList.empty())
157 LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
158 << " implicit defs.\n");
161 // Drain the WorkList to recursively process any new implicit defs.
162 do processImplicitDef(WorkList.pop_back_val());
163 while (!WorkList.empty());