1 //===- RegisterScavenging.cpp - Machine register scavenging ---------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file implements the machine register scavenger. It can provide
11 /// information, such as unused registers, at any point in a machine basic
12 /// block. It also provides a mechanism to make registers available by evicting
13 /// them to spill slots.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/RegisterScavenging.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/LiveRegUnits.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/TargetFrameLowering.h"
31 #include "llvm/CodeGen/TargetInstrInfo.h"
32 #include "llvm/CodeGen/TargetRegisterInfo.h"
33 #include "llvm/CodeGen/TargetSubtargetInfo.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Pass.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
49 #define DEBUG_TYPE "reg-scavenging"
51 STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
53 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) {
54 LiveUnits.addRegMasked(Reg, LaneMask);
57 void RegScavenger::init(MachineBasicBlock &MBB) {
58 MachineFunction &MF = *MBB.getParent();
59 TII = MF.getSubtarget().getInstrInfo();
60 TRI = MF.getSubtarget().getRegisterInfo();
61 MRI = &MF.getRegInfo();
64 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
69 NumRegUnits = TRI->getNumRegUnits();
70 KillRegUnits.resize(NumRegUnits);
71 DefRegUnits.resize(NumRegUnits);
72 TmpRegUnits.resize(NumRegUnits);
76 for (ScavengedInfo &SI : Scavenged) {
84 void RegScavenger::enterBasicBlock(MachineBasicBlock &MBB) {
86 LiveUnits.addLiveIns(MBB);
89 void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
91 LiveUnits.addLiveOuts(MBB);
93 // Move internal iterator at the last instruction of the block.
94 if (MBB.begin() != MBB.end()) {
95 MBBI = std::prev(MBB.end());
100 void RegScavenger::addRegUnits(BitVector &BV, Register Reg) {
101 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
105 void RegScavenger::removeRegUnits(BitVector &BV, Register Reg) {
106 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
110 void RegScavenger::determineKillsAndDefs() {
111 assert(Tracking && "Must be tracking to determine kills and defs");
113 MachineInstr &MI = *MBBI;
114 assert(!MI.isDebugInstr() && "Debug values have no kills or defs");
116 // Find out which registers are early clobbered, killed, defined, and marked
117 // def-dead in this instruction.
118 KillRegUnits.reset();
120 for (const MachineOperand &MO : MI.operands()) {
121 if (MO.isRegMask()) {
123 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
124 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
125 if (MO.clobbersPhysReg(*RURI)) {
133 KillRegUnits |= TmpRegUnits;
137 Register Reg = MO.getReg();
138 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
142 // Ignore undef uses.
146 addRegUnits(KillRegUnits, Reg);
150 addRegUnits(KillRegUnits, Reg);
152 addRegUnits(DefRegUnits, Reg);
157 void RegScavenger::unprocess() {
158 assert(Tracking && "Cannot unprocess because we're not tracking");
160 MachineInstr &MI = *MBBI;
161 if (!MI.isDebugInstr()) {
162 determineKillsAndDefs();
164 // Commit the changes.
165 setUnused(DefRegUnits);
166 setUsed(KillRegUnits);
169 if (MBBI == MBB->begin()) {
170 MBBI = MachineBasicBlock::iterator(nullptr);
176 void RegScavenger::forward() {
182 assert(MBBI != MBB->end() && "Already past the end of the basic block!");
183 MBBI = std::next(MBBI);
185 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
187 MachineInstr &MI = *MBBI;
189 for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
190 IE = Scavenged.end(); I != IE; ++I) {
191 if (I->Restore != &MI)
195 I->Restore = nullptr;
198 if (MI.isDebugInstr())
201 determineKillsAndDefs();
203 // Verify uses and defs.
205 for (const MachineOperand &MO : MI.operands()) {
208 Register Reg = MO.getReg();
209 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
214 if (!isRegUsed(Reg)) {
215 // Check if it's partial live: e.g.
216 // D0 = insert_subreg undef D0, S0
218 // The problem is the insert_subreg could be eliminated. The use of
219 // D0 is using a partially undef value. This is not *incorrect* since
220 // S1 is can be freely clobbered.
221 // Ideally we would like a way to model this, but leaving the
222 // insert_subreg around causes both correctness and performance issues.
223 bool SubUsed = false;
224 for (const MCPhysReg &SubReg : TRI->subregs(Reg))
225 if (isRegUsed(SubReg)) {
229 bool SuperUsed = false;
230 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
231 if (isRegUsed(*SR)) {
236 if (!SubUsed && !SuperUsed) {
237 MBB->getParent()->verify(nullptr, "In Register Scavenger");
238 llvm_unreachable("Using an undefined register!");
246 // FIXME: Enable this once we've figured out how to correctly transfer
247 // implicit kills during codegen passes like the coalescer.
248 assert((KillRegs.test(Reg) || isUnused(Reg) ||
249 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
250 "Re-defining a live register!");
256 // Commit the changes.
257 setUnused(KillRegUnits);
258 setUsed(DefRegUnits);
261 void RegScavenger::backward() {
262 assert(Tracking && "Must be tracking to determine kills and defs");
264 const MachineInstr &MI = *MBBI;
265 LiveUnits.stepBackward(MI);
267 // Expire scavenge spill frameindex uses.
268 for (ScavengedInfo &I : Scavenged) {
269 if (I.Restore == &MI) {
275 if (MBBI == MBB->begin()) {
276 MBBI = MachineBasicBlock::iterator(nullptr);
282 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
284 return includeReserved;
285 return !LiveUnits.available(Reg);
288 Register RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
289 for (Register Reg : *RC) {
290 if (!isRegUsed(Reg)) {
291 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
299 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
300 BitVector Mask(TRI->getNumRegs());
301 for (Register Reg : *RC)
307 Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
308 BitVector &Candidates,
310 MachineBasicBlock::iterator &UseMI) {
311 int Survivor = Candidates.find_first();
312 assert(Survivor > 0 && "No candidates for scavenging");
314 MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
315 assert(StartMI != ME && "MI already at terminator");
316 MachineBasicBlock::iterator RestorePointMI = StartMI;
317 MachineBasicBlock::iterator MI = StartMI;
319 bool inVirtLiveRange = false;
320 for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
321 if (MI->isDebugInstr()) {
322 ++InstrLimit; // Don't count debug instructions
325 bool isVirtKillInsn = false;
326 bool isVirtDefInsn = false;
327 // Remove any candidates touched by instruction.
328 for (const MachineOperand &MO : MI->operands()) {
330 Candidates.clearBitsNotInMask(MO.getRegMask());
331 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
333 if (Register::isVirtualRegister(MO.getReg())) {
335 isVirtDefInsn = true;
336 else if (MO.isKill())
337 isVirtKillInsn = true;
340 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
341 Candidates.reset(*AI);
343 // If we're not in a virtual reg's live range, this is a valid
345 if (!inVirtLiveRange) RestorePointMI = MI;
347 // Update whether we're in the live range of a virtual register
348 if (isVirtKillInsn) inVirtLiveRange = false;
349 if (isVirtDefInsn) inVirtLiveRange = true;
351 // Was our survivor untouched by this instruction?
352 if (Candidates.test(Survivor))
355 // All candidates gone?
356 if (Candidates.none())
359 Survivor = Candidates.find_first();
361 // If we ran off the end, that's where we want to restore.
362 if (MI == ME) RestorePointMI = ME;
363 assert(RestorePointMI != StartMI &&
364 "No available scavenger restore location!");
366 // We ran out of candidates, so stop the search.
367 UseMI = RestorePointMI;
371 /// Given the bitvector \p Available of free register units at position
372 /// \p From. Search backwards to find a register that is part of \p
373 /// Candidates and not used/clobbered until the point \p To. If there is
374 /// multiple candidates continue searching and pick the one that is not used/
375 /// clobbered for the longest time.
376 /// Returns the register and the earliest position we know it to be free or
377 /// the position MBB.end() if no register is available.
378 static std::pair<MCPhysReg, MachineBasicBlock::iterator>
379 findSurvivorBackwards(const MachineRegisterInfo &MRI,
380 MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
381 const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder,
383 bool FoundTo = false;
384 MCPhysReg Survivor = 0;
385 MachineBasicBlock::iterator Pos;
386 MachineBasicBlock &MBB = *From->getParent();
387 unsigned InstrLimit = 25;
388 unsigned InstrCountDown = InstrLimit;
389 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
390 LiveRegUnits Used(TRI);
392 for (MachineBasicBlock::iterator I = From;; --I) {
393 const MachineInstr &MI = *I;
398 // See if one of the registers in RC wasn't used so far.
399 for (MCPhysReg Reg : AllocationOrder) {
400 if (!MRI.isReserved(Reg) && Used.available(Reg) &&
401 LiveOut.available(Reg))
402 return std::make_pair(Reg, MBB.end());
404 // Otherwise we will continue up to InstrLimit instructions to find
405 // the register which is not defined/used for the longest time.
408 // Note: It was fine so far to start our search at From, however now that
409 // we have to spill, and can only place the restore after From then
410 // add the regs used/defed by std::next(From) to the set.
412 Used.accumulate(*std::next(From));
415 if (Survivor == 0 || !Used.available(Survivor)) {
416 MCPhysReg AvilableReg = 0;
417 for (MCPhysReg Reg : AllocationOrder) {
418 if (!MRI.isReserved(Reg) && Used.available(Reg)) {
423 if (AvilableReg == 0)
425 Survivor = AvilableReg;
427 if (--InstrCountDown == 0)
430 // Keep searching when we find a vreg since the spilled register will
431 // be usefull for this other vreg as well later.
432 bool FoundVReg = false;
433 for (const MachineOperand &MO : MI.operands()) {
434 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
440 InstrCountDown = InstrLimit;
443 if (I == MBB.begin())
448 return std::make_pair(Survivor, Pos);
451 static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
453 while (!MI.getOperand(i).isFI()) {
455 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
460 RegScavenger::ScavengedInfo &
461 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
462 MachineBasicBlock::iterator Before,
463 MachineBasicBlock::iterator &UseMI) {
464 // Find an available scavenging slot with size and alignment matching
465 // the requirements of the class RC.
466 const MachineFunction &MF = *Before->getMF();
467 const MachineFrameInfo &MFI = MF.getFrameInfo();
468 unsigned NeedSize = TRI->getSpillSize(RC);
469 Align NeedAlign = TRI->getSpillAlign(RC);
471 unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();
472 int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
473 for (unsigned I = 0; I < Scavenged.size(); ++I) {
474 if (Scavenged[I].Reg != 0)
476 // Verify that this slot is valid for this register.
477 int FI = Scavenged[I].FrameIndex;
478 if (FI < FIB || FI >= FIE)
480 unsigned S = MFI.getObjectSize(FI);
481 Align A = MFI.getObjectAlign(FI);
482 if (NeedSize > S || NeedAlign > A)
484 // Avoid wasting slots with large size and/or large alignment. Pick one
485 // that is the best fit for this register class (in street metric).
486 // Picking a larger slot than necessary could happen if a slot for a
487 // larger register is reserved before a slot for a smaller one. When
488 // trying to spill a smaller register, the large slot would be found
489 // first, thus making it impossible to spill the larger register later.
490 unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value());
497 if (SI == Scavenged.size()) {
498 // We need to scavenge a register but have no spill slot, the target
499 // must know how to do it (if not, we'll assert below).
500 Scavenged.push_back(ScavengedInfo(FIE));
503 // Avoid infinite regress
504 Scavenged[SI].Reg = Reg;
506 // If the target knows how to save/restore the register, let it do so;
507 // otherwise, use the emergency stack spill slot.
508 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
509 // Spill the scavenged register before \p Before.
510 int FI = Scavenged[SI].FrameIndex;
511 if (FI < FIB || FI >= FIE) {
512 std::string Msg = std::string("Error while trying to spill ") +
513 TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +
514 ": Cannot scavenge register without an emergency spill slot!";
515 report_fatal_error(Msg.c_str());
517 TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,
519 MachineBasicBlock::iterator II = std::prev(Before);
521 unsigned FIOperandNum = getFrameIndexOperandNum(*II);
522 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
524 // Restore the scavenged register before its use (or first terminator).
525 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
527 II = std::prev(UseMI);
529 FIOperandNum = getFrameIndexOperandNum(*II);
530 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
532 return Scavenged[SI];
535 Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
536 MachineBasicBlock::iterator I,
537 int SPAdj, bool AllowSpill) {
538 MachineInstr &MI = *I;
539 const MachineFunction &MF = *MI.getMF();
540 // Consider all allocatable registers in the register class initially
541 BitVector Candidates = TRI->getAllocatableSet(MF, RC);
543 // Exclude all the registers being used by the instruction.
544 for (const MachineOperand &MO : MI.operands()) {
545 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
546 !Register::isVirtualRegister(MO.getReg()))
547 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
548 Candidates.reset(*AI);
551 // Try to find a register that's unused if there is one, as then we won't
553 BitVector Available = getRegsAvailable(RC);
554 Available &= Candidates;
556 Candidates = Available;
558 // Find the register whose use is furthest away.
559 MachineBasicBlock::iterator UseMI;
560 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
562 // If we found an unused register there is no reason to spill it.
563 if (!isRegUsed(SReg)) {
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
571 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
572 Scavenged.Restore = &*std::prev(UseMI);
574 LLVM_DEBUG(dbgs() << "Scavenged register (with spill): "
575 << printReg(SReg, TRI) << "\n");
580 Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
581 MachineBasicBlock::iterator To,
582 bool RestoreAfter, int SPAdj,
584 const MachineBasicBlock &MBB = *To->getParent();
585 const MachineFunction &MF = *MBB.getParent();
587 // Find the register whose use is furthest away.
588 MachineBasicBlock::iterator UseMI;
589 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF);
590 std::pair<MCPhysReg, MachineBasicBlock::iterator> P =
591 findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder,
593 MCPhysReg Reg = P.first;
594 MachineBasicBlock::iterator SpillBefore = P.second;
595 assert(Reg != 0 && "No register left to scavenge!");
596 // Found an available register?
597 if (SpillBefore == MBB.end()) {
598 LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
606 MachineBasicBlock::iterator ReloadAfter =
607 RestoreAfter ? std::next(MBBI) : MBBI;
608 MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
609 if (ReloadBefore != MBB.end())
610 LLVM_DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
611 ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
612 Scavenged.Restore = &*std::prev(SpillBefore);
613 LiveUnits.removeReg(Reg);
614 LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
615 << " until " << *SpillBefore);
619 /// Allocate a register for the virtual register \p VReg. The last use of
620 /// \p VReg is around the current position of the register scavenger \p RS.
621 /// \p ReserveAfter controls whether the scavenged register needs to be reserved
622 /// after the current instruction, otherwise it will only be reserved before the
623 /// current instruction.
624 static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
625 Register VReg, bool ReserveAfter) {
626 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
628 // Verify that all definitions and uses are in the same basic block.
629 const MachineBasicBlock *CommonMBB = nullptr;
630 // Real definition for the reg, re-definitions are not considered.
631 const MachineInstr *RealDef = nullptr;
632 for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {
633 MachineBasicBlock *MBB = MO.getParent()->getParent();
634 if (CommonMBB == nullptr)
636 assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");
638 const MachineInstr &MI = *MO.getParent();
639 if (!MI.readsRegister(VReg, &TRI)) {
640 assert((!RealDef || RealDef == &MI) &&
641 "Can have at most one definition which is not a redefinition");
646 assert(RealDef != nullptr && "Must have at least 1 Def");
649 // We should only have one definition of the register. However to accommodate
650 // the requirements of two address code we also allow definitions in
651 // subsequent instructions provided they also read the register. That way
652 // we get a single contiguous lifetime.
654 // Definitions in MRI.def_begin() are unordered, search for the first.
655 MachineRegisterInfo::def_iterator FirstDef =
656 std::find_if(MRI.def_begin(VReg), MRI.def_end(),
657 [VReg, &TRI](const MachineOperand &MO) {
658 return !MO.getParent()->readsRegister(VReg, &TRI);
660 assert(FirstDef != MRI.def_end() &&
661 "Must have one definition that does not redefine vreg");
662 MachineInstr &DefMI = *FirstDef->getParent();
664 // The register scavenger will report a free register inserting an emergency
665 // spill/reload if necessary.
667 const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
668 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
669 ReserveAfter, SPAdj);
670 MRI.replaceRegWith(VReg, SReg);
675 /// Allocate (scavenge) vregs inside a single basic block.
676 /// Returns true if the target spill callback created new vregs and a 2nd pass
678 static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,
680 MachineBasicBlock &MBB) {
681 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
682 RS.enterBasicBlockEnd(MBB);
684 unsigned InitialNumVirtRegs = MRI.getNumVirtRegs();
685 bool NextInstructionReadsVReg = false;
686 for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {
688 // Move RegScavenger to the position between *I and *std::next(I).
691 // Look for unassigned vregs in the uses of *std::next(I).
692 if (NextInstructionReadsVReg) {
693 MachineBasicBlock::iterator N = std::next(I);
694 const MachineInstr &NMI = *N;
695 for (const MachineOperand &MO : NMI.operands()) {
698 Register Reg = MO.getReg();
699 // We only care about virtual registers and ignore virtual registers
700 // created by the target callbacks in the process (those will be handled
701 // in a scavenging round).
702 if (!Register::isVirtualRegister(Reg) ||
703 Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
708 Register SReg = scavengeVReg(MRI, RS, Reg, true);
709 N->addRegisterKilled(SReg, &TRI, false);
714 // Look for unassigned vregs in the defs of *I.
715 NextInstructionReadsVReg = false;
716 const MachineInstr &MI = *I;
717 for (const MachineOperand &MO : MI.operands()) {
720 Register Reg = MO.getReg();
721 // Only vregs, no newly created vregs (see above).
722 if (!Register::isVirtualRegister(Reg) ||
723 Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
725 // We have to look at all operands anyway so we can precalculate here
726 // whether there is a reading operand. This allows use to skip the use
727 // step in the next iteration if there was none.
728 assert(!MO.isInternalRead() && "Cannot assign inside bundles");
729 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
731 NextInstructionReadsVReg = true;
734 Register SReg = scavengeVReg(MRI, RS, Reg, false);
735 I->addRegisterDead(SReg, &TRI, false);
740 for (const MachineOperand &MO : MBB.front().operands()) {
741 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
743 assert(!MO.isInternalRead() && "Cannot assign inside bundles");
744 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
745 assert(!MO.readsReg() && "Vreg use in first instruction not allowed");
749 return MRI.getNumVirtRegs() != InitialNumVirtRegs;
752 void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {
753 // FIXME: Iterating over the instruction stream is unnecessary. We can simply
754 // iterate over the vreg use list, which at this point only contains machine
755 // operands for which eliminateFrameIndex need a new scratch reg.
756 MachineRegisterInfo &MRI = MF.getRegInfo();
758 if (MRI.getNumVirtRegs() == 0) {
759 MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
763 // Run through the instructions and find any virtual registers.
764 for (MachineBasicBlock &MBB : MF) {
768 bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);
770 LLVM_DEBUG(dbgs() << "Warning: Required two scavenging passes for block "
771 << MBB.getName() << '\n');
772 Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);
773 // The target required a 2nd run (because it created new vregs while
774 // spilling). Refuse to do another pass to keep compiletime in check.
776 report_fatal_error("Incomplete scavenging after 2nd pass");
781 MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
786 /// This class runs register scavenging independ of the PrologEpilogInserter.
787 /// This is used in for testing.
788 class ScavengerTest : public MachineFunctionPass {
792 ScavengerTest() : MachineFunctionPass(ID) {}
794 bool runOnMachineFunction(MachineFunction &MF) override {
795 const TargetSubtargetInfo &STI = MF.getSubtarget();
796 const TargetFrameLowering &TFL = *STI.getFrameLowering();
799 // Let's hope that calling those outside of PrologEpilogueInserter works
800 // well enough to initialize the scavenger with some emergency spillslots
803 TFL.determineCalleeSaves(MF, SavedRegs, &RS);
804 TFL.processFunctionBeforeFrameFinalized(MF, &RS);
806 // Let's scavenge the current function
807 scavengeFrameVirtualRegs(MF, RS);
812 } // end anonymous namespace
814 char ScavengerTest::ID;
816 INITIALIZE_PASS(ScavengerTest, "scavenger-test",
817 "Scavenge virtual registers inside basic blocks", false, false)