1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
13 //===----------------------------------------------------------------------===//
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/StackMaps.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/CodeGen/TargetLowering.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 #define DEBUG_TYPE "instr-emitter"
35 /// MinRCSize - Smallest register class we allow when constraining virtual
36 /// registers. If satisfying all register class constraints would require
37 /// using a smaller register class, emit a COPY to a new virtual register
39 const unsigned MinRCSize = 4;
41 /// CountResults - The results of target nodes have register or immediate
42 /// operands first, then an optional chain, and optional glue operands (which do
43 /// not go into the resulting MachineInstr).
44 unsigned InstrEmitter::CountResults(SDNode *Node) {
45 unsigned N = Node->getNumValues();
46 while (N && Node->getValueType(N - 1) == MVT::Glue)
48 if (N && Node->getValueType(N - 1) == MVT::Other)
49 --N; // Skip over chain result.
53 /// countOperands - The inputs to target nodes have any actual inputs first,
54 /// followed by an optional chain operand, then an optional glue operand.
55 /// Compute the number of actual operands that will go into the resulting
58 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59 /// the chain and glue. These operands may be implicit on the machine instr.
60 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61 unsigned &NumImpUses) {
62 unsigned N = Node->getNumOperands();
63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66 --N; // Ignore chain if it exists.
68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69 NumImpUses = N - NumExpUses;
70 for (unsigned I = N; I > NumExpUses; --I) {
71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
83 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84 /// implicit physical register output.
86 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
90 // Just use the input register directly!
91 SDValue Op(Node, ResNo);
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95 (void)isNew; // Silence compiler warning.
96 assert(isNew && "Node emitted out of order - early");
100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
102 bool MatchReg = true;
103 const TargetRegisterClass *UseRC = nullptr;
104 MVT VT = Node->getSimpleValueType(ResNo);
106 // Stick to the preferred register classes for legal types.
107 if (TLI->isTypeLegal(VT))
108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
110 if (!IsClone && !IsCloned)
111 for (SDNode *User : Node->uses()) {
113 if (User->getOpcode() == ISD::CopyToReg &&
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
120 } else if (DestReg != SrcReg)
123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124 SDValue Op = User->getOperand(i);
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
131 if (User->isMachineOpcode()) {
132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133 const TargetRegisterClass *RC = nullptr;
134 if (i+II.getNumDefs() < II.getNumOperands()) {
135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
141 const TargetRegisterClass *ComRC =
142 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
143 // If multiple uses expect disjoint register classes, we emit
144 // copies in AddRegisterOperand.
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159 // Figure out the register class to create for the destreg.
161 DstRC = MRI->getRegClass(VRBase);
163 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
164 "Incompatible phys register def and uses!");
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
181 SDValue Op(Node, ResNo);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early");
189 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190 MachineInstrBuilder &MIB,
191 const MCInstrDesc &II,
192 bool IsClone, bool IsCloned,
193 DenseMap<SDValue, unsigned> &VRBaseMap) {
194 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
195 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
197 unsigned NumResults = CountResults(Node);
198 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
199 // If the specific node value is only used by a CopyToReg and the dest reg
200 // is a vreg in the same register class, use the CopyToReg'd destination
201 // register instead of creating a new vreg.
203 const TargetRegisterClass *RC =
204 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
205 // Always let the value type influence the used register class. The
206 // constraints on the instruction may be too lax to represent the value
207 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208 // the 32-bit float super-class (X86::FR32).
209 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211 Node->getSimpleValueType(i),
212 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
214 VTRC = TRI->getCommonSubClass(RC, VTRC);
219 if (II.OpInfo[i].isOptionalDef()) {
220 // Optional def must be a physical register.
221 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
222 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
223 MIB.addReg(VRBase, RegState::Define);
226 if (!VRBase && !IsClone && !IsCloned)
227 for (SDNode *User : Node->uses()) {
228 if (User->getOpcode() == ISD::CopyToReg &&
229 User->getOperand(2).getNode() == Node &&
230 User->getOperand(2).getResNo() == i) {
231 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
232 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
236 MIB.addReg(VRBase, RegState::Define);
243 // Create the result registers for this node and add the result regs to
244 // the machine instruction.
246 assert(RC && "Isn't a register operand!");
247 VRBase = MRI->createVirtualRegister(RC);
248 MIB.addReg(VRBase, RegState::Define);
251 // If this def corresponds to a result of the SDNode insert the VRBase into
253 if (i < NumResults) {
257 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
258 (void)isNew; // Silence compiler warning.
259 assert(isNew && "Node emitted out of order - early");
264 /// getVR - Return the virtual register corresponding to the specified result
265 /// of the specified node.
266 unsigned InstrEmitter::getVR(SDValue Op,
267 DenseMap<SDValue, unsigned> &VRBaseMap) {
268 if (Op.isMachineOpcode() &&
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270 // Add an IMPLICIT_DEF instruction before every use.
271 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272 // does not include operand register class info.
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
274 Op.getSimpleValueType(), Op.getNode()->isDivergent());
275 unsigned VReg = MRI->createVirtualRegister(RC);
276 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
281 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
282 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
287 /// AddRegisterOperand - Add the specified register as an operand to the
288 /// specified machine instr. Insert register copies if the register is
289 /// not in the required register class.
291 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
294 const MCInstrDesc *II,
295 DenseMap<SDValue, unsigned> &VRBaseMap,
296 bool IsDebug, bool IsClone, bool IsCloned) {
297 assert(Op.getValueType() != MVT::Other &&
298 Op.getValueType() != MVT::Glue &&
299 "Chain and glue operands should occur at end of operand list!");
300 // Get/emit the operand.
301 unsigned VReg = getVR(Op, VRBaseMap);
303 const MCInstrDesc &MCID = MIB->getDesc();
304 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305 MCID.OpInfo[IIOpNum].isOptionalDef();
307 // If the instruction requires a register in a different class, create
308 // a new virtual register and copy the value into it, but first attempt to
309 // shrink VReg's register class within reason. For example, if VReg == GR32
310 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
312 const TargetRegisterClass *OpRC = nullptr;
313 if (IIOpNum < II->getNumOperands())
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
317 const TargetRegisterClass *ConstrainedRC
318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
319 if (!ConstrainedRC) {
320 OpRC = TRI->getAllocatableClass(OpRC);
321 assert(OpRC && "Constraints cannot be fulfilled for allocation");
322 unsigned NewVReg = MRI->createVirtualRegister(OpRC);
323 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
327 assert(ConstrainedRC->isAllocatable() &&
328 "Constraining an allocatable VReg produced an unallocatable class?");
333 // If this value has only one use, that use is a kill. This is a
334 // conservative approximation. InstrEmitter does trivial coalescing
335 // with CopyFromReg nodes, so don't emit kill flags for them.
336 // Avoid kill flags on Schedule cloned nodes, since there will be
338 // Tied operands are never killed, so we need to check that. And that
339 // means we need to determine the index of the operand.
340 bool isKill = Op.hasOneUse() &&
341 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
343 !(IsClone || IsCloned);
345 unsigned Idx = MIB->getNumOperands();
347 MIB->getOperand(Idx-1).isReg() &&
348 MIB->getOperand(Idx-1).isImplicit())
350 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
356 getDebugRegState(IsDebug));
359 /// AddOperand - Add the specified operand to the specified machine instr. II
360 /// specifies the instruction information for the node, and IIOpNum is the
361 /// operand number (in the II) that we are adding.
362 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
365 const MCInstrDesc *II,
366 DenseMap<SDValue, unsigned> &VRBaseMap,
367 bool IsDebug, bool IsClone, bool IsCloned) {
368 if (Op.isMachineOpcode()) {
369 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
370 IsDebug, IsClone, IsCloned);
371 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
372 MIB.addImm(C->getSExtValue());
373 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
374 MIB.addFPImm(F->getConstantFPValue());
375 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
376 unsigned VReg = R->getReg();
377 MVT OpVT = Op.getSimpleValueType();
378 const TargetRegisterClass *IIRC =
379 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
381 const TargetRegisterClass *OpRC =
382 TLI->isTypeLegal(OpVT)
383 ? TLI->getRegClassFor(OpVT,
384 Op.getNode()->isDivergent() ||
385 (IIRC && TRI->isDivergentRegClass(IIRC)))
388 if (OpRC && IIRC && OpRC != IIRC &&
389 TargetRegisterInfo::isVirtualRegister(VReg)) {
390 unsigned NewVReg = MRI->createVirtualRegister(IIRC);
391 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
392 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
395 // Turn additional physreg operands into implicit uses on non-variadic
396 // instructions. This is used by call and return instructions passing
397 // arguments in registers.
398 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
399 MIB.addReg(VReg, getImplRegState(Imp));
400 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
401 MIB.addRegMask(RM->getRegMask());
402 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
403 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
404 TGA->getTargetFlags());
405 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
406 MIB.addMBB(BBNode->getBasicBlock());
407 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
408 MIB.addFrameIndex(FI->getIndex());
409 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
410 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
411 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
412 int Offset = CP->getOffset();
413 unsigned Align = CP->getAlignment();
414 Type *Type = CP->getType();
415 // MachineConstantPool wants an explicit alignment.
417 Align = MF->getDataLayout().getPrefTypeAlignment(Type);
419 // Alignment of vector types. FIXME!
420 Align = MF->getDataLayout().getTypeAllocSize(Type);
425 MachineConstantPool *MCP = MF->getConstantPool();
426 if (CP->isMachineConstantPoolEntry())
427 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
429 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
430 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
431 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
432 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
433 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
434 MIB.addSym(SymNode->getMCSymbol());
435 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
436 MIB.addBlockAddress(BA->getBlockAddress(),
438 BA->getTargetFlags());
439 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
440 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
442 assert(Op.getValueType() != MVT::Other &&
443 Op.getValueType() != MVT::Glue &&
444 "Chain and glue operands should occur at end of operand list!");
445 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
446 IsDebug, IsClone, IsCloned);
450 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
451 MVT VT, bool isDivergent, const DebugLoc &DL) {
452 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
453 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
455 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
458 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
460 // VReg has been adjusted. It can be used with SubIdx operands now.
464 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
466 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
467 assert(RC && "No legal register class for VT supports that SubIdx");
468 unsigned NewReg = MRI->createVirtualRegister(RC);
469 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
474 /// EmitSubregNode - Generate machine code for subreg nodes.
476 void InstrEmitter::EmitSubregNode(SDNode *Node,
477 DenseMap<SDValue, unsigned> &VRBaseMap,
478 bool IsClone, bool IsCloned) {
480 unsigned Opc = Node->getMachineOpcode();
482 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
483 // the CopyToReg'd destination register instead of creating a new vreg.
484 for (SDNode *User : Node->uses()) {
485 if (User->getOpcode() == ISD::CopyToReg &&
486 User->getOperand(2).getNode() == Node) {
487 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
488 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
495 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
496 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
497 // constraints on the %dst register, COPY can target all legal register
499 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
500 const TargetRegisterClass *TRC =
501 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
505 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
506 if (R && TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
510 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
511 DefMI = MRI->getVRegDef(Reg);
514 unsigned SrcReg, DstReg, DefSubIdx;
516 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
517 SubIdx == DefSubIdx &&
518 TRC == MRI->getRegClass(SrcReg)) {
520 // r1025 = s/zext r1024, 4
521 // r1026 = extract_subreg r1025, 4
523 // r1026 = copy r1024
524 VRBase = MRI->createVirtualRegister(TRC);
525 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
526 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
527 MRI->clearKillFlags(SrcReg);
529 // Reg may not support a SubIdx sub-register, and we may need to
530 // constrain its register class or issue a COPY to a compatible register
532 if (TargetRegisterInfo::isVirtualRegister(Reg))
533 Reg = ConstrainForSubReg(Reg, SubIdx,
534 Node->getOperand(0).getSimpleValueType(),
535 Node->isDivergent(), Node->getDebugLoc());
536 // Create the destreg if it is missing.
538 VRBase = MRI->createVirtualRegister(TRC);
540 // Create the extract_subreg machine instruction.
541 MachineInstrBuilder CopyMI =
542 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543 TII->get(TargetOpcode::COPY), VRBase);
544 if (TargetRegisterInfo::isVirtualRegister(Reg))
545 CopyMI.addReg(Reg, 0, SubIdx);
547 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
549 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
550 Opc == TargetOpcode::SUBREG_TO_REG) {
551 SDValue N0 = Node->getOperand(0);
552 SDValue N1 = Node->getOperand(1);
553 SDValue N2 = Node->getOperand(2);
554 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
556 // Figure out the register class to create for the destreg. It should be
557 // the largest legal register class supporting SubIdx sub-registers.
558 // RegisterCoalescer will constrain it further if it decides to eliminate
559 // the INSERT_SUBREG instruction.
561 // %dst = INSERT_SUBREG %src, %sub, SubIdx
563 // is lowered by TwoAddressInstructionPass to:
566 // %dst:SubIdx = COPY %sub
568 // There is no constraint on the %src register class.
570 const TargetRegisterClass *SRC =
571 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
572 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
573 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
575 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
576 VRBase = MRI->createVirtualRegister(SRC);
578 // Create the insert_subreg or subreg_to_reg machine instruction.
579 MachineInstrBuilder MIB =
580 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
582 // If creating a subreg_to_reg, then the first input operand
583 // is an implicit value immediate, otherwise it's a register
584 if (Opc == TargetOpcode::SUBREG_TO_REG) {
585 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
586 MIB.addImm(SD->getZExtValue());
588 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
590 // Add the subregister being inserted
591 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
594 MBB->insert(InsertPos, MIB);
596 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
599 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
600 (void)isNew; // Silence compiler warning.
601 assert(isNew && "Node emitted out of order - early");
604 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
605 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
606 /// register is constrained to be in a particular register class.
609 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
610 DenseMap<SDValue, unsigned> &VRBaseMap) {
611 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
613 // Create the new VReg in the destination class and emit a copy.
614 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
615 const TargetRegisterClass *DstRC =
616 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
617 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
618 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
619 NewVReg).addReg(VReg);
622 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
623 (void)isNew; // Silence compiler warning.
624 assert(isNew && "Node emitted out of order - early");
627 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
629 void InstrEmitter::EmitRegSequence(SDNode *Node,
630 DenseMap<SDValue, unsigned> &VRBaseMap,
631 bool IsClone, bool IsCloned) {
632 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
633 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
634 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
635 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
636 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
637 unsigned NumOps = Node->getNumOperands();
638 // If the input pattern has a chain, then the root of the corresponding
639 // output pattern will get a chain as well. This can happen to be a
640 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
641 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
642 --NumOps; // Ignore chain if it exists.
644 assert((NumOps & 1) == 1 &&
645 "REG_SEQUENCE must have an odd number of operands!");
646 for (unsigned i = 1; i != NumOps; ++i) {
647 SDValue Op = Node->getOperand(i);
649 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
650 // Skip physical registers as they don't have a vreg to get and we'll
651 // insert copies for them in TwoAddressInstructionPass anyway.
652 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
653 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
654 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
655 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
656 const TargetRegisterClass *SRC =
657 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
658 if (SRC && SRC != RC) {
659 MRI->setRegClass(NewVReg, SRC);
664 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
668 MBB->insert(InsertPos, MIB);
670 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
671 (void)isNew; // Silence compiler warning.
672 assert(isNew && "Node emitted out of order - early");
675 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
678 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
679 DenseMap<SDValue, unsigned> &VRBaseMap) {
680 MDNode *Var = SD->getVariable();
681 MDNode *Expr = SD->getExpression();
682 DebugLoc DL = SD->getDebugLoc();
683 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
684 "Expected inlined-at fields to agree");
688 if (SD->isInvalidated()) {
689 // An invalidated SDNode must generate an undef DBG_VALUE: although the
690 // original value is no longer computed, earlier DBG_VALUEs live ranges
691 // must not leak into later code.
692 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
694 MIB.addReg(0U, RegState::Debug);
695 MIB.addMetadata(Var);
696 MIB.addMetadata(Expr);
700 if (SD->getKind() == SDDbgValue::FRAMEIX) {
701 // Stack address; this needs to be lowered in target-dependent fashion.
702 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
703 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
704 .addFrameIndex(SD->getFrameIx());
705 if (SD->isIndirect())
706 // Push [fi + 0] onto the DIExpression stack.
709 // Push fi onto the DIExpression stack.
711 return FrameMI.addMetadata(Var).addMetadata(Expr);
713 // Otherwise, we're going to create an instruction here.
714 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
715 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
716 if (SD->getKind() == SDDbgValue::SDNODE) {
717 SDNode *Node = SD->getSDNode();
718 SDValue Op = SDValue(Node, SD->getResNo());
719 // It's possible we replaced this SDNode with other(s) and therefore
720 // didn't generate code for it. It's better to catch these cases where
721 // they happen and transfer the debug info, but trying to guarantee that
722 // in all cases would be very fragile; this is a safeguard for any
724 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
725 if (I==VRBaseMap.end())
726 MIB.addReg(0U); // undef
728 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
729 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
730 } else if (SD->getKind() == SDDbgValue::VREG) {
731 MIB.addReg(SD->getVReg(), RegState::Debug);
732 } else if (SD->getKind() == SDDbgValue::CONST) {
733 const Value *V = SD->getConst();
734 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
735 if (CI->getBitWidth() > 64)
738 MIB.addImm(CI->getSExtValue());
739 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
741 } else if (isa<ConstantPointerNull>(V)) {
742 // Note: This assumes that all nullptr constants are zero-valued.
745 // Could be an Undef. In any case insert an Undef so we can see what we
750 // Insert an Undef so we can see what we dropped.
754 // Indirect addressing is indicated by an Imm as the second parameter.
755 if (SD->isIndirect())
758 MIB.addReg(0U, RegState::Debug);
760 MIB.addMetadata(Var);
761 MIB.addMetadata(Expr);
767 InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
768 MDNode *Label = SD->getLabel();
769 DebugLoc DL = SD->getDebugLoc();
770 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
771 "Expected inlined-at fields to agree");
773 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
774 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
775 MIB.addMetadata(Label);
780 /// EmitMachineNode - Generate machine code for a target-specific node and
781 /// needed dependencies.
784 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
785 DenseMap<SDValue, unsigned> &VRBaseMap) {
786 unsigned Opc = Node->getMachineOpcode();
788 // Handle subreg insert/extract specially
789 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
790 Opc == TargetOpcode::INSERT_SUBREG ||
791 Opc == TargetOpcode::SUBREG_TO_REG) {
792 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
796 // Handle COPY_TO_REGCLASS specially.
797 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
798 EmitCopyToRegClassNode(Node, VRBaseMap);
802 // Handle REG_SEQUENCE specially.
803 if (Opc == TargetOpcode::REG_SEQUENCE) {
804 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
808 if (Opc == TargetOpcode::IMPLICIT_DEF)
809 // We want a unique VR for each IMPLICIT_DEF use.
812 const MCInstrDesc &II = TII->get(Opc);
813 unsigned NumResults = CountResults(Node);
814 unsigned NumDefs = II.getNumDefs();
815 const MCPhysReg *ScratchRegs = nullptr;
817 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
818 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
819 // Stackmaps do not have arguments and do not preserve their calling
820 // convention. However, to simplify runtime support, they clobber the same
821 // scratch registers as AnyRegCC.
822 unsigned CC = CallingConv::AnyReg;
823 if (Opc == TargetOpcode::PATCHPOINT) {
824 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
825 NumDefs = NumResults;
827 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
830 unsigned NumImpUses = 0;
831 unsigned NodeOperands =
832 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
833 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
835 unsigned NumMIOperands = NodeOperands + NumResults;
837 assert(NumMIOperands >= II.getNumOperands() &&
838 "Too few operands for a variadic node!");
840 assert(NumMIOperands >= II.getNumOperands() &&
841 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
843 "#operands for dag node doesn't match .td file!");
846 // Create the new machine instruction.
847 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
849 // Add result register values for things that are defined by this
852 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
854 // Transfer any IR flags from the SDNode to the MachineInstr
855 MachineInstr *MI = MIB.getInstr();
856 const SDNodeFlags Flags = Node->getFlags();
857 if (Flags.hasNoSignedZeros())
858 MI->setFlag(MachineInstr::MIFlag::FmNsz);
860 if (Flags.hasAllowReciprocal())
861 MI->setFlag(MachineInstr::MIFlag::FmArcp);
863 if (Flags.hasNoNaNs())
864 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
866 if (Flags.hasNoInfs())
867 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
869 if (Flags.hasAllowContract())
870 MI->setFlag(MachineInstr::MIFlag::FmContract);
872 if (Flags.hasApproximateFuncs())
873 MI->setFlag(MachineInstr::MIFlag::FmAfn);
875 if (Flags.hasAllowReassociation())
876 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
878 if (Flags.hasNoUnsignedWrap())
879 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
881 if (Flags.hasNoSignedWrap())
882 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
884 if (Flags.hasExact())
885 MI->setFlag(MachineInstr::MIFlag::IsExact);
887 if (Flags.hasFPExcept())
888 MI->setFlag(MachineInstr::MIFlag::FPExcept);
891 // Emit all of the actual operands of this instruction, adding them to the
892 // instruction as appropriate.
893 bool HasOptPRefs = NumDefs > NumResults;
894 assert((!HasOptPRefs || !HasPhysRegOuts) &&
895 "Unable to cope with optional defs and phys regs defs!");
896 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
897 for (unsigned i = NumSkip; i != NodeOperands; ++i)
898 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
899 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
901 // Add scratch registers as implicit def and early clobber
903 for (unsigned i = 0; ScratchRegs[i]; ++i)
904 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
905 RegState::EarlyClobber);
907 // Set the memory reference descriptions of this instruction now that it is
908 // part of the function.
909 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
911 // Insert the instruction into position in the block. This needs to
912 // happen before any custom inserter hook is called so that the
913 // hook knows where in the block to insert the replacement code.
914 MBB->insert(InsertPos, MIB);
916 // The MachineInstr may also define physregs instead of virtregs. These
917 // physreg values can reach other instructions in different ways:
919 // 1. When there is a use of a Node value beyond the explicitly defined
920 // virtual registers, we emit a CopyFromReg for one of the implicitly
921 // defined physregs. This only happens when HasPhysRegOuts is true.
923 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
925 // 3. A glued instruction may implicitly use a physreg.
927 // 4. A glued instruction may use a RegisterSDNode operand.
929 // Collect all the used physreg defs, and make sure that any unused physreg
930 // defs are marked as dead.
931 SmallVector<unsigned, 8> UsedRegs;
933 // Additional results must be physical register defs.
934 if (HasPhysRegOuts) {
935 for (unsigned i = NumDefs; i < NumResults; ++i) {
936 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
937 if (!Node->hasAnyUseOfValue(i))
939 // This implicitly defined physreg has a use.
940 UsedRegs.push_back(Reg);
941 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
945 // Scan the glue chain for any used physregs.
946 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
947 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
948 if (F->getOpcode() == ISD::CopyFromReg) {
949 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
951 } else if (F->getOpcode() == ISD::CopyToReg) {
952 // Skip CopyToReg nodes that are internal to the glue chain.
955 // Collect declared implicit uses.
956 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
957 UsedRegs.append(MCID.getImplicitUses(),
958 MCID.getImplicitUses() + MCID.getNumImplicitUses());
959 // In addition to declared implicit uses, we must also check for
960 // direct RegisterSDNode operands.
961 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
962 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
963 unsigned Reg = R->getReg();
964 if (TargetRegisterInfo::isPhysicalRegister(Reg))
965 UsedRegs.push_back(Reg);
970 // Finally mark unused registers as dead.
971 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
972 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
974 // Run post-isel target hook to adjust this instruction if needed.
975 if (II.hasPostISelHook())
976 TLI->AdjustInstrPostInstrSelection(*MIB, Node);
979 /// EmitSpecialNode - Generate machine code for a target-independent node and
980 /// needed dependencies.
982 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
983 DenseMap<SDValue, unsigned> &VRBaseMap) {
984 switch (Node->getOpcode()) {
989 llvm_unreachable("This target-independent node should have been selected!");
990 case ISD::EntryToken:
991 llvm_unreachable("EntryToken should have been excluded from the schedule!");
992 case ISD::MERGE_VALUES:
993 case ISD::TokenFactor: // fall thru
995 case ISD::CopyToReg: {
996 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
997 SDValue SrcVal = Node->getOperand(2);
998 if (TargetRegisterInfo::isVirtualRegister(DestReg) &&
999 SrcVal.isMachineOpcode() &&
1000 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1001 // Instead building a COPY to that vreg destination, build an
1002 // IMPLICIT_DEF instruction instead.
1003 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1004 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1008 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1009 SrcReg = R->getReg();
1011 SrcReg = getVR(SrcVal, VRBaseMap);
1013 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1016 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1017 DestReg).addReg(SrcReg);
1020 case ISD::CopyFromReg: {
1021 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1022 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1026 case ISD::ANNOTATION_LABEL: {
1027 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1028 ? TargetOpcode::EH_LABEL
1029 : TargetOpcode::ANNOTATION_LABEL;
1030 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1031 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1032 TII->get(Opc)).addSym(S);
1036 case ISD::LIFETIME_START:
1037 case ISD::LIFETIME_END: {
1038 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1039 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
1041 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1042 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1043 .addFrameIndex(FI->getIndex());
1047 case ISD::INLINEASM:
1048 case ISD::INLINEASM_BR: {
1049 unsigned NumOps = Node->getNumOperands();
1050 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1051 --NumOps; // Ignore the glue operand.
1053 // Create the inline asm machine instruction.
1054 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1055 ? TargetOpcode::INLINEASM_BR
1056 : TargetOpcode::INLINEASM;
1057 MachineInstrBuilder MIB =
1058 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1060 // Add the asm string as an external symbol operand.
1061 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1062 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1063 MIB.addExternalSymbol(AsmStr);
1065 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1068 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1070 MIB.addImm(ExtraInfo);
1072 // Remember to operand index of the group flags.
1073 SmallVector<unsigned, 8> GroupIdx;
1075 // Remember registers that are part of early-clobber defs.
1076 SmallVector<unsigned, 8> ECRegs;
1078 // Add all of the operand registers to the instruction.
1079 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1081 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1082 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1084 GroupIdx.push_back(MIB->getNumOperands());
1086 ++i; // Skip the ID value.
1088 switch (InlineAsm::getKind(Flags)) {
1089 default: llvm_unreachable("Bad flags!");
1090 case InlineAsm::Kind_RegDef:
1091 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1092 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1093 // FIXME: Add dead flags for physical and virtual registers defined.
1094 // For now, mark physical register defs as implicit to help fast
1095 // regalloc. This makes inline asm look a lot like calls.
1096 MIB.addReg(Reg, RegState::Define |
1097 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
1100 case InlineAsm::Kind_RegDefEarlyClobber:
1101 case InlineAsm::Kind_Clobber:
1102 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1103 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1104 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
1105 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
1106 ECRegs.push_back(Reg);
1109 case InlineAsm::Kind_RegUse: // Use of register.
1110 case InlineAsm::Kind_Imm: // Immediate.
1111 case InlineAsm::Kind_Mem: // Addressing mode.
1112 // The addressing mode has been selected, just add all of the
1113 // operands to the machine instruction.
1114 for (unsigned j = 0; j != NumVals; ++j, ++i)
1115 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1116 /*IsDebug=*/false, IsClone, IsCloned);
1118 // Manually set isTied bits.
1119 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1120 unsigned DefGroup = 0;
1121 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1122 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1123 unsigned UseIdx = GroupIdx.back() + 1;
1124 for (unsigned j = 0; j != NumVals; ++j)
1125 MIB->tieOperands(DefIdx + j, UseIdx + j);
1132 // GCC inline assembly allows input operands to also be early-clobber
1133 // output operands (so long as the operand is written only after it's
1134 // used), but this does not match the semantics of our early-clobber flag.
1135 // If an early-clobber operand register is also an input operand register,
1136 // then remove the early-clobber flag.
1137 for (unsigned Reg : ECRegs) {
1138 if (MIB->readsRegister(Reg, TRI)) {
1139 MachineOperand *MO =
1140 MIB->findRegisterDefOperand(Reg, false, false, TRI);
1141 assert(MO && "No def operand for clobbered register?");
1142 MO->setIsEarlyClobber(false);
1146 // Get the mdnode from the asm if it exists and add it to the instruction.
1147 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1148 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1150 MIB.addMetadata(MD);
1152 MBB->insert(InsertPos, MIB);
1158 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1159 /// at the given position in the given block.
1160 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1161 MachineBasicBlock::iterator insertpos)
1162 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1163 TII(MF->getSubtarget().getInstrInfo()),
1164 TRI(MF->getSubtarget().getRegisterInfo()),
1165 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1166 InsertPos(insertpos) {}