1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This implements the TargetLowering class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/TargetLowering.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/CodeGen/CallingConvLower.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetRegisterInfo.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/DerivedTypes.h"
25 #include "llvm/IR/GlobalVariable.h"
26 #include "llvm/IR/LLVMContext.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/KnownBits.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
33 #include "llvm/Target/TargetMachine.h"
37 /// NOTE: The TargetMachine owns TLOF.
38 TargetLowering::TargetLowering(const TargetMachine &tm)
39 : TargetLoweringBase(tm) {}
41 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
45 bool TargetLowering::isPositionIndependent() const {
46 return getTargetMachine().isPositionIndependent();
49 /// Check whether a given call node is in tail position within its function. If
50 /// so, it sets Chain to the input chain of the tail call.
51 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
52 SDValue &Chain) const {
53 const Function &F = DAG.getMachineFunction().getFunction();
55 // First, check if tail calls have been disabled in this function.
56 if (F.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
59 // Conservatively require the attributes of the call to match those of
60 // the return. Ignore NoAlias and NonNull because they don't affect the
62 AttributeList CallerAttrs = F.getAttributes();
63 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
64 .removeAttribute(Attribute::NoAlias)
65 .removeAttribute(Attribute::NonNull)
69 // It's not safe to eliminate the sign / zero extension of the return value.
70 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
71 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
74 // Check if the only use is a function return node.
75 return isUsedByReturnOnly(Node, Chain);
78 bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
79 const uint32_t *CallerPreservedMask,
80 const SmallVectorImpl<CCValAssign> &ArgLocs,
81 const SmallVectorImpl<SDValue> &OutVals) const {
82 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
83 const CCValAssign &ArgLoc = ArgLocs[I];
84 if (!ArgLoc.isRegLoc())
86 MCRegister Reg = ArgLoc.getLocReg();
87 // Only look at callee saved registers.
88 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
90 // Check that we pass the value used for the caller.
91 // (We look for a CopyFromReg reading a virtual register that is used
92 // for the function live-in value of register Reg)
93 SDValue Value = OutVals[I];
94 if (Value->getOpcode() != ISD::CopyFromReg)
96 MCRegister ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
97 if (MRI.getLiveInPhysReg(ArgReg) != Reg)
103 /// Set CallLoweringInfo attribute flags based on a call instruction
104 /// and called function attributes.
105 void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call,
107 IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt);
108 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt);
109 IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg);
110 IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet);
111 IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest);
112 IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal);
113 IsPreallocated = Call->paramHasAttr(ArgIdx, Attribute::Preallocated);
114 IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca);
115 IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned);
116 IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
117 IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError);
118 Alignment = Call->getParamAlign(ArgIdx);
121 ByValType = Call->getParamByValType(ArgIdx);
122 PreallocatedType = nullptr;
124 PreallocatedType = Call->getParamPreallocatedType(ArgIdx);
127 /// Generate a libcall taking the given operands as arguments and returning a
128 /// result of type RetVT.
129 std::pair<SDValue, SDValue>
130 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
131 ArrayRef<SDValue> Ops,
132 MakeLibCallOptions CallOptions,
134 SDValue InChain) const {
136 InChain = DAG.getEntryNode();
138 TargetLowering::ArgListTy Args;
139 Args.reserve(Ops.size());
141 TargetLowering::ArgListEntry Entry;
142 for (unsigned i = 0; i < Ops.size(); ++i) {
143 SDValue NewOp = Ops[i];
145 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
146 Entry.IsSExt = shouldSignExtendTypeInLibCall(NewOp.getValueType(),
148 Entry.IsZExt = !Entry.IsSExt;
150 if (CallOptions.IsSoften &&
151 !shouldExtendTypeInLibCall(CallOptions.OpsVTBeforeSoften[i])) {
152 Entry.IsSExt = Entry.IsZExt = false;
154 Args.push_back(Entry);
157 if (LC == RTLIB::UNKNOWN_LIBCALL)
158 report_fatal_error("Unsupported library call operation!");
159 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
160 getPointerTy(DAG.getDataLayout()));
162 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
163 TargetLowering::CallLoweringInfo CLI(DAG);
164 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt);
165 bool zeroExtend = !signExtend;
167 if (CallOptions.IsSoften &&
168 !shouldExtendTypeInLibCall(CallOptions.RetVTBeforeSoften)) {
169 signExtend = zeroExtend = false;
174 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
175 .setNoReturn(CallOptions.DoesNotReturn)
176 .setDiscardResult(!CallOptions.IsReturnValueUsed)
177 .setIsPostTypeLegalization(CallOptions.IsPostTypeLegalization)
178 .setSExtResult(signExtend)
179 .setZExtResult(zeroExtend);
180 return LowerCallTo(CLI);
183 bool TargetLowering::findOptimalMemOpLowering(
184 std::vector<EVT> &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS,
185 unsigned SrcAS, const AttributeList &FuncAttributes) const {
186 if (Op.isMemcpyWithFixedDstAlign() && Op.getSrcAlign() < Op.getDstAlign())
189 EVT VT = getOptimalMemOpType(Op, FuncAttributes);
191 if (VT == MVT::Other) {
192 // Use the largest integer type whose alignment constraints are satisfied.
193 // We only need to check DstAlign here as SrcAlign is always greater or
194 // equal to DstAlign (or zero).
196 if (Op.isFixedDstAlign())
198 Op.getDstAlign() < (VT.getSizeInBits() / 8) &&
199 !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign().value()))
200 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
201 assert(VT.isInteger());
203 // Find the largest legal integer type.
205 while (!isTypeLegal(LVT))
206 LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1);
207 assert(LVT.isInteger());
209 // If the type we've chosen is larger than the largest legal integer type
210 // then use that instead.
215 unsigned NumMemOps = 0;
216 uint64_t Size = Op.size();
218 unsigned VTSize = VT.getSizeInBits() / 8;
219 while (VTSize > Size) {
220 // For now, only use non-vector load / store's for the left-over pieces.
225 if (VT.isVector() || VT.isFloatingPoint()) {
226 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32;
227 if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&
228 isSafeMemOpType(NewVT.getSimpleVT()))
230 else if (NewVT == MVT::i64 &&
231 isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
232 isSafeMemOpType(MVT::f64)) {
233 // i64 is usually not legal on 32-bit targets, but f64 may be.
241 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1);
242 if (NewVT == MVT::i8)
244 } while (!isSafeMemOpType(NewVT.getSimpleVT()));
246 NewVTSize = NewVT.getSizeInBits() / 8;
248 // If the new VT cannot cover all of the remaining bits, then consider
249 // issuing a (or a pair of) unaligned and overlapping load / store.
251 if (NumMemOps && Op.allowOverlap() && NewVTSize < Size &&
252 allowsMisalignedMemoryAccesses(
253 VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign().value() : 0,
254 MachineMemOperand::MONone, &Fast) &&
263 if (++NumMemOps > Limit)
266 MemOps.push_back(VT);
273 /// Soften the operands of a comparison. This code is shared among BR_CC,
274 /// SELECT_CC, and SETCC handlers.
275 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
276 SDValue &NewLHS, SDValue &NewRHS,
277 ISD::CondCode &CCCode,
278 const SDLoc &dl, const SDValue OldLHS,
279 const SDValue OldRHS) const {
281 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS,
285 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
286 SDValue &NewLHS, SDValue &NewRHS,
287 ISD::CondCode &CCCode,
288 const SDLoc &dl, const SDValue OldLHS,
289 const SDValue OldRHS,
291 bool IsSignaling) const {
292 // FIXME: Currently we cannot really respect all IEEE predicates due to libgcc
293 // not supporting it. We can update this code when libgcc provides such
296 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
297 && "Unsupported setcc type!");
299 // Expand into one or more soft-fp libcall(s).
300 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
301 bool ShouldInvertCC = false;
305 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
306 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
307 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
311 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
312 (VT == MVT::f64) ? RTLIB::UNE_F64 :
313 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
317 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
318 (VT == MVT::f64) ? RTLIB::OGE_F64 :
319 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
323 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
324 (VT == MVT::f64) ? RTLIB::OLT_F64 :
325 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
329 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
330 (VT == MVT::f64) ? RTLIB::OLE_F64 :
331 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
335 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
336 (VT == MVT::f64) ? RTLIB::OGT_F64 :
337 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
340 ShouldInvertCC = true;
343 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
344 (VT == MVT::f64) ? RTLIB::UO_F64 :
345 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
349 ShouldInvertCC = true;
352 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
353 (VT == MVT::f64) ? RTLIB::UO_F64 :
354 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
355 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
356 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
357 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
360 // Invert CC for unordered comparisons
361 ShouldInvertCC = true;
364 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
365 (VT == MVT::f64) ? RTLIB::OGE_F64 :
366 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
369 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
370 (VT == MVT::f64) ? RTLIB::OGT_F64 :
371 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
374 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
375 (VT == MVT::f64) ? RTLIB::OLE_F64 :
376 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
379 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
380 (VT == MVT::f64) ? RTLIB::OLT_F64 :
381 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
383 default: llvm_unreachable("Do not know how to soften this setcc!");
387 // Use the target specific return value for comparions lib calls.
388 EVT RetVT = getCmpLibcallReturnType();
389 SDValue Ops[2] = {NewLHS, NewRHS};
390 TargetLowering::MakeLibCallOptions CallOptions;
391 EVT OpsVT[2] = { OldLHS.getValueType(),
392 OldRHS.getValueType() };
393 CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true);
394 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain);
396 NewRHS = DAG.getConstant(0, dl, RetVT);
398 CCCode = getCmpLibcallCC(LC1);
399 if (ShouldInvertCC) {
400 assert(RetVT.isInteger());
401 CCCode = getSetCCInverse(CCCode, RetVT);
404 if (LC2 == RTLIB::UNKNOWN_LIBCALL) {
409 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT);
410 SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode);
411 auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain);
412 CCCode = getCmpLibcallCC(LC2);
414 CCCode = getSetCCInverse(CCCode, RetVT);
415 NewLHS = DAG.getSetCC(dl, SetCCVT, Call2.first, NewRHS, CCCode);
417 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Call.second,
419 NewLHS = DAG.getNode(ShouldInvertCC ? ISD::AND : ISD::OR, dl,
420 Tmp.getValueType(), Tmp, NewLHS);
425 /// Return the entry encoding for a jump table in the current function. The
426 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
427 unsigned TargetLowering::getJumpTableEncoding() const {
428 // In non-pic modes, just use the address of a block.
429 if (!isPositionIndependent())
430 return MachineJumpTableInfo::EK_BlockAddress;
432 // In PIC mode, if the target supports a GPRel32 directive, use it.
433 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
434 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
436 // Otherwise, use a label difference.
437 return MachineJumpTableInfo::EK_LabelDifference32;
440 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
441 SelectionDAG &DAG) const {
442 // If our PIC model is GP relative, use the global offset table as the base.
443 unsigned JTEncoding = getJumpTableEncoding();
445 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
446 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
447 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
452 /// This returns the relocation base for the given PIC jumptable, the same as
453 /// getPICJumpTableRelocBase, but as an MCExpr.
455 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
456 unsigned JTI,MCContext &Ctx) const{
457 // The normal PIC reloc base is the label at the start of the jump table.
458 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
462 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
463 const TargetMachine &TM = getTargetMachine();
464 const GlobalValue *GV = GA->getGlobal();
466 // If the address is not even local to this DSO we will have to load it from
467 // a got and then add the offset.
468 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
471 // If the code is position independent we will have to add a base register.
472 if (isPositionIndependent())
475 // Otherwise we can do it.
479 //===----------------------------------------------------------------------===//
480 // Optimization Methods
481 //===----------------------------------------------------------------------===//
483 /// If the specified instruction has a constant integer operand and there are
484 /// bits set in that constant that are not demanded, then clear those bits and
486 bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
487 const APInt &DemandedBits,
488 const APInt &DemandedElts,
489 TargetLoweringOpt &TLO) const {
491 unsigned Opcode = Op.getOpcode();
493 // Do target-specific constant optimization.
494 if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
495 return TLO.New.getNode();
497 // FIXME: ISD::SELECT, ISD::SELECT_CC
504 auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
508 // If this is a 'not' op, don't touch it because that's a canonical form.
509 const APInt &C = Op1C->getAPIntValue();
510 if (Opcode == ISD::XOR && DemandedBits.isSubsetOf(C))
513 if (!C.isSubsetOf(DemandedBits)) {
514 EVT VT = Op.getValueType();
515 SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT);
516 SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
517 return TLO.CombineTo(Op, NewOp);
527 bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
528 const APInt &DemandedBits,
529 TargetLoweringOpt &TLO) const {
530 EVT VT = Op.getValueType();
531 APInt DemandedElts = VT.isVector()
532 ? APInt::getAllOnesValue(VT.getVectorNumElements())
534 return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO);
537 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
538 /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
539 /// generalized for targets with other types of implicit widening casts.
540 bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
541 const APInt &Demanded,
542 TargetLoweringOpt &TLO) const {
543 assert(Op.getNumOperands() == 2 &&
544 "ShrinkDemandedOp only supports binary operators!");
545 assert(Op.getNode()->getNumValues() == 1 &&
546 "ShrinkDemandedOp only supports nodes with one result!");
548 SelectionDAG &DAG = TLO.DAG;
551 // Early return, as this function cannot handle vector types.
552 if (Op.getValueType().isVector())
555 // Don't do this if the node has another user, which may require the
557 if (!Op.getNode()->hasOneUse())
560 // Search for the smallest integer type with free casts to and from
561 // Op's type. For expedience, just check power-of-2 integer types.
562 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
563 unsigned DemandedSize = Demanded.getActiveBits();
564 unsigned SmallVTBits = DemandedSize;
565 if (!isPowerOf2_32(SmallVTBits))
566 SmallVTBits = NextPowerOf2(SmallVTBits);
567 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
568 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
569 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
570 TLI.isZExtFree(SmallVT, Op.getValueType())) {
571 // We found a type with free casts.
572 SDValue X = DAG.getNode(
573 Op.getOpcode(), dl, SmallVT,
574 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
575 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
576 assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
577 SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
578 return TLO.CombineTo(Op, Z);
584 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
585 DAGCombinerInfo &DCI) const {
586 SelectionDAG &DAG = DCI.DAG;
587 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
588 !DCI.isBeforeLegalizeOps());
591 bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO);
593 DCI.AddToWorklist(Op.getNode());
594 DCI.CommitTargetLoweringOpt(TLO);
599 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
601 TargetLoweringOpt &TLO,
603 bool AssumeSingleUse) const {
604 EVT VT = Op.getValueType();
606 // TODO: We can probably do more work on calculating the known bits and
607 // simplifying the operations for scalable vectors, but for now we just
609 if (VT.isScalableVector()) {
610 // Pretend we don't know anything for now.
611 Known = KnownBits(DemandedBits.getBitWidth());
615 APInt DemandedElts = VT.isVector()
616 ? APInt::getAllOnesValue(VT.getVectorNumElements())
618 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth,
622 // TODO: Can we merge SelectionDAG::GetDemandedBits into this?
623 // TODO: Under what circumstances can we create nodes? Constant folding?
624 SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
625 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
626 SelectionDAG &DAG, unsigned Depth) const {
627 // Limit search depth.
628 if (Depth >= SelectionDAG::MaxRecursionDepth)
635 // Not demanding any bits/elts from Op.
636 if (DemandedBits == 0 || DemandedElts == 0)
637 return DAG.getUNDEF(Op.getValueType());
639 unsigned NumElts = DemandedElts.getBitWidth();
640 unsigned BitWidth = DemandedBits.getBitWidth();
641 KnownBits LHSKnown, RHSKnown;
642 switch (Op.getOpcode()) {
644 SDValue Src = peekThroughBitcasts(Op.getOperand(0));
645 EVT SrcVT = Src.getValueType();
646 EVT DstVT = Op.getValueType();
650 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
651 unsigned NumDstEltBits = DstVT.getScalarSizeInBits();
652 if (NumSrcEltBits == NumDstEltBits)
653 if (SDValue V = SimplifyMultipleUseDemandedBits(
654 Src, DemandedBits, DemandedElts, DAG, Depth + 1))
655 return DAG.getBitcast(DstVT, V);
657 // TODO - bigendian once we have test coverage.
658 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 &&
659 DAG.getDataLayout().isLittleEndian()) {
660 unsigned Scale = NumDstEltBits / NumSrcEltBits;
661 unsigned NumSrcElts = SrcVT.getVectorNumElements();
662 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
663 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
664 for (unsigned i = 0; i != Scale; ++i) {
665 unsigned Offset = i * NumSrcEltBits;
666 APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset);
667 if (!Sub.isNullValue()) {
668 DemandedSrcBits |= Sub;
669 for (unsigned j = 0; j != NumElts; ++j)
671 DemandedSrcElts.setBit((j * Scale) + i);
675 if (SDValue V = SimplifyMultipleUseDemandedBits(
676 Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1))
677 return DAG.getBitcast(DstVT, V);
680 // TODO - bigendian once we have test coverage.
681 if ((NumSrcEltBits % NumDstEltBits) == 0 &&
682 DAG.getDataLayout().isLittleEndian()) {
683 unsigned Scale = NumSrcEltBits / NumDstEltBits;
684 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
685 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
686 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
687 for (unsigned i = 0; i != NumElts; ++i)
688 if (DemandedElts[i]) {
689 unsigned Offset = (i % Scale) * NumDstEltBits;
690 DemandedSrcBits.insertBits(DemandedBits, Offset);
691 DemandedSrcElts.setBit(i / Scale);
694 if (SDValue V = SimplifyMultipleUseDemandedBits(
695 Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1))
696 return DAG.getBitcast(DstVT, V);
702 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
703 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
705 // If all of the demanded bits are known 1 on one side, return the other.
706 // These bits cannot contribute to the result of the 'and' in this
708 if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
709 return Op.getOperand(0);
710 if (DemandedBits.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
711 return Op.getOperand(1);
715 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
716 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
718 // If all of the demanded bits are known zero on one side, return the
719 // other. These bits cannot contribute to the result of the 'or' in this
721 if (DemandedBits.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
722 return Op.getOperand(0);
723 if (DemandedBits.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
724 return Op.getOperand(1);
728 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
729 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
731 // If all of the demanded bits are known zero on one side, return the
733 if (DemandedBits.isSubsetOf(RHSKnown.Zero))
734 return Op.getOperand(0);
735 if (DemandedBits.isSubsetOf(LHSKnown.Zero))
736 return Op.getOperand(1);
740 // If we are only demanding sign bits then we can use the shift source
742 if (const APInt *MaxSA =
743 DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) {
744 SDValue Op0 = Op.getOperand(0);
745 unsigned ShAmt = MaxSA->getZExtValue();
746 unsigned NumSignBits =
747 DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
748 unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
749 if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
755 SDValue Op0 = Op.getOperand(0);
756 SDValue Op1 = Op.getOperand(1);
757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
758 // If (1) we only need the sign-bit, (2) the setcc operands are the same
759 // width as the setcc result, and (3) the result of a setcc conforms to 0 or
760 // -1, we may be able to bypass the setcc.
761 if (DemandedBits.isSignMask() &&
762 Op0.getScalarValueSizeInBits() == BitWidth &&
763 getBooleanContents(Op0.getValueType()) ==
764 BooleanContent::ZeroOrNegativeOneBooleanContent) {
765 // If we're testing X < 0, then this compare isn't needed - just use X!
766 // FIXME: We're limiting to integer types here, but this should also work
767 // if we don't care about FP signed-zero. The use of SETLT with FP means
768 // that we don't care about NaNs.
769 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
770 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
775 case ISD::SIGN_EXTEND_INREG: {
776 // If none of the extended bits are demanded, eliminate the sextinreg.
777 SDValue Op0 = Op.getOperand(0);
778 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
779 unsigned ExBits = ExVT.getScalarSizeInBits();
780 if (DemandedBits.getActiveBits() <= ExBits)
782 // If the input is already sign extended, just drop the extension.
783 unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
784 if (NumSignBits >= (BitWidth - ExBits + 1))
788 case ISD::ANY_EXTEND_VECTOR_INREG:
789 case ISD::SIGN_EXTEND_VECTOR_INREG:
790 case ISD::ZERO_EXTEND_VECTOR_INREG: {
791 // If we only want the lowest element and none of extended bits, then we can
792 // return the bitcasted source vector.
793 SDValue Src = Op.getOperand(0);
794 EVT SrcVT = Src.getValueType();
795 EVT DstVT = Op.getValueType();
796 if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() &&
797 DAG.getDataLayout().isLittleEndian() &&
798 DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) {
799 return DAG.getBitcast(DstVT, Src);
803 case ISD::INSERT_VECTOR_ELT: {
804 // If we don't demand the inserted element, return the base vector.
805 SDValue Vec = Op.getOperand(0);
806 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
807 EVT VecVT = Vec.getValueType();
808 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) &&
809 !DemandedElts[CIdx->getZExtValue()])
813 case ISD::INSERT_SUBVECTOR: {
814 // If we don't demand the inserted subvector, return the base vector.
815 SDValue Vec = Op.getOperand(0);
816 SDValue Sub = Op.getOperand(1);
817 uint64_t Idx = Op.getConstantOperandVal(2);
818 unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
819 if (DemandedElts.extractBits(NumSubElts, Idx) == 0)
823 case ISD::VECTOR_SHUFFLE: {
824 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
826 // If all the demanded elts are from one operand and are inline,
827 // then we can use the operand directly.
828 bool AllUndef = true, IdentityLHS = true, IdentityRHS = true;
829 for (unsigned i = 0; i != NumElts; ++i) {
830 int M = ShuffleMask[i];
831 if (M < 0 || !DemandedElts[i])
834 IdentityLHS &= (M == (int)i);
835 IdentityRHS &= ((M - NumElts) == i);
839 return DAG.getUNDEF(Op.getValueType());
841 return Op.getOperand(0);
843 return Op.getOperand(1);
847 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
848 if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode(
849 Op, DemandedBits, DemandedElts, DAG, Depth))
856 SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
857 SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG,
858 unsigned Depth) const {
859 EVT VT = Op.getValueType();
860 APInt DemandedElts = VT.isVector()
861 ? APInt::getAllOnesValue(VT.getVectorNumElements())
863 return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG,
867 SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts(
868 SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG,
869 unsigned Depth) const {
870 APInt DemandedBits = APInt::getAllOnesValue(Op.getScalarValueSizeInBits());
871 return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG,
875 /// Look at Op. At this point, we know that only the OriginalDemandedBits of the
876 /// result of Op are ever used downstream. If we can use this information to
877 /// simplify Op, create a new simplified DAG node and return true, returning the
878 /// original and new nodes in Old and New. Otherwise, analyze the expression and
879 /// return a mask of Known bits for the expression (used to simplify the
880 /// caller). The Known bits may only be accurate for those bits in the
881 /// OriginalDemandedBits and OriginalDemandedElts.
882 bool TargetLowering::SimplifyDemandedBits(
883 SDValue Op, const APInt &OriginalDemandedBits,
884 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
885 unsigned Depth, bool AssumeSingleUse) const {
886 unsigned BitWidth = OriginalDemandedBits.getBitWidth();
887 assert(Op.getScalarValueSizeInBits() == BitWidth &&
888 "Mask size mismatches value type size!");
890 // Don't know anything.
891 Known = KnownBits(BitWidth);
893 // TODO: We can probably do more work on calculating the known bits and
894 // simplifying the operations for scalable vectors, but for now we just
896 if (Op.getValueType().isScalableVector())
899 unsigned NumElts = OriginalDemandedElts.getBitWidth();
900 assert((!Op.getValueType().isVector() ||
901 NumElts == Op.getValueType().getVectorNumElements()) &&
902 "Unexpected vector size");
904 APInt DemandedBits = OriginalDemandedBits;
905 APInt DemandedElts = OriginalDemandedElts;
907 auto &DL = TLO.DAG.getDataLayout();
913 if (Op.getOpcode() == ISD::Constant) {
914 // We know all of the bits for a constant!
915 Known.One = cast<ConstantSDNode>(Op)->getAPIntValue();
916 Known.Zero = ~Known.One;
920 // Other users may use these bits.
921 EVT VT = Op.getValueType();
922 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
924 // If not at the root, Just compute the Known bits to
925 // simplify things downstream.
926 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
929 // If this is the root being simplified, allow it to have multiple uses,
930 // just set the DemandedBits/Elts to all bits.
931 DemandedBits = APInt::getAllOnesValue(BitWidth);
932 DemandedElts = APInt::getAllOnesValue(NumElts);
933 } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) {
934 // Not demanding any bits/elts from Op.
935 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
936 } else if (Depth >= SelectionDAG::MaxRecursionDepth) {
937 // Limit search depth.
942 switch (Op.getOpcode()) {
943 case ISD::TargetConstant:
944 llvm_unreachable("Can't simplify this node");
945 case ISD::SCALAR_TO_VECTOR: {
946 if (!DemandedElts[0])
947 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
950 SDValue Src = Op.getOperand(0);
951 unsigned SrcBitWidth = Src.getScalarValueSizeInBits();
952 APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth);
953 if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1))
956 // Upper elements are undef, so only get the knownbits if we just demand
957 // the bottom element.
958 if (DemandedElts == 1)
959 Known = SrcKnown.anyextOrTrunc(BitWidth);
962 case ISD::BUILD_VECTOR:
963 // Collect the known bits that are shared by every demanded element.
964 // TODO: Call SimplifyDemandedBits for non-constant demanded elements.
965 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
966 return false; // Don't fall through, will infinitely loop.
968 LoadSDNode *LD = cast<LoadSDNode>(Op);
969 if (getTargetConstantFromLoad(LD)) {
970 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
971 return false; // Don't fall through, will infinitely loop.
972 } else if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) {
973 // If this is a ZEXTLoad and we are looking at the loaded value.
974 EVT MemVT = LD->getMemoryVT();
975 unsigned MemBits = MemVT.getScalarSizeInBits();
976 Known.Zero.setBitsFrom(MemBits);
977 return false; // Don't fall through, will infinitely loop.
981 case ISD::INSERT_VECTOR_ELT: {
982 SDValue Vec = Op.getOperand(0);
983 SDValue Scl = Op.getOperand(1);
984 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
985 EVT VecVT = Vec.getValueType();
987 // If index isn't constant, assume we need all vector elements AND the
989 APInt DemandedVecElts(DemandedElts);
990 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) {
991 unsigned Idx = CIdx->getZExtValue();
992 DemandedVecElts.clearBit(Idx);
994 // Inserted element is not required.
995 if (!DemandedElts[Idx])
996 return TLO.CombineTo(Op, Vec);
1000 unsigned NumSclBits = Scl.getScalarValueSizeInBits();
1001 APInt DemandedSclBits = DemandedBits.zextOrTrunc(NumSclBits);
1002 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1))
1005 Known = KnownScl.anyextOrTrunc(BitWidth);
1008 if (SimplifyDemandedBits(Vec, DemandedBits, DemandedVecElts, KnownVec, TLO,
1012 if (!!DemandedVecElts) {
1013 Known.One &= KnownVec.One;
1014 Known.Zero &= KnownVec.Zero;
1019 case ISD::INSERT_SUBVECTOR: {
1020 // Demand any elements from the subvector and the remainder from the src its
1022 SDValue Src = Op.getOperand(0);
1023 SDValue Sub = Op.getOperand(1);
1024 uint64_t Idx = Op.getConstantOperandVal(2);
1025 unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
1026 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
1027 APInt DemandedSrcElts = DemandedElts;
1028 DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx);
1030 KnownBits KnownSub, KnownSrc;
1031 if (SimplifyDemandedBits(Sub, DemandedBits, DemandedSubElts, KnownSub, TLO,
1034 if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, KnownSrc, TLO,
1038 Known.Zero.setAllBits();
1039 Known.One.setAllBits();
1040 if (!!DemandedSubElts) {
1041 Known.One &= KnownSub.One;
1042 Known.Zero &= KnownSub.Zero;
1044 if (!!DemandedSrcElts) {
1045 Known.One &= KnownSrc.One;
1046 Known.Zero &= KnownSrc.Zero;
1049 // Attempt to avoid multi-use src if we don't need anything from it.
1050 if (!DemandedBits.isAllOnesValue() || !DemandedSubElts.isAllOnesValue() ||
1051 !DemandedSrcElts.isAllOnesValue()) {
1052 SDValue NewSub = SimplifyMultipleUseDemandedBits(
1053 Sub, DemandedBits, DemandedSubElts, TLO.DAG, Depth + 1);
1054 SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1055 Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1);
1056 if (NewSub || NewSrc) {
1057 NewSub = NewSub ? NewSub : Sub;
1058 NewSrc = NewSrc ? NewSrc : Src;
1059 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc, NewSub,
1061 return TLO.CombineTo(Op, NewOp);
1066 case ISD::EXTRACT_SUBVECTOR: {
1067 // Offset the demanded elts by the subvector index.
1068 SDValue Src = Op.getOperand(0);
1069 if (Src.getValueType().isScalableVector())
1071 uint64_t Idx = Op.getConstantOperandVal(1);
1072 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1073 APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
1075 if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, Known, TLO,
1079 // Attempt to avoid multi-use src if we don't need anything from it.
1080 if (!DemandedBits.isAllOnesValue() || !DemandedSrcElts.isAllOnesValue()) {
1081 SDValue DemandedSrc = SimplifyMultipleUseDemandedBits(
1082 Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1);
1084 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc,
1086 return TLO.CombineTo(Op, NewOp);
1091 case ISD::CONCAT_VECTORS: {
1092 Known.Zero.setAllBits();
1093 Known.One.setAllBits();
1094 EVT SubVT = Op.getOperand(0).getValueType();
1095 unsigned NumSubVecs = Op.getNumOperands();
1096 unsigned NumSubElts = SubVT.getVectorNumElements();
1097 for (unsigned i = 0; i != NumSubVecs; ++i) {
1098 APInt DemandedSubElts =
1099 DemandedElts.extractBits(NumSubElts, i * NumSubElts);
1100 if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts,
1101 Known2, TLO, Depth + 1))
1103 // Known bits are shared by every demanded subvector element.
1104 if (!!DemandedSubElts) {
1105 Known.One &= Known2.One;
1106 Known.Zero &= Known2.Zero;
1111 case ISD::VECTOR_SHUFFLE: {
1112 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
1114 // Collect demanded elements from shuffle operands..
1115 APInt DemandedLHS(NumElts, 0);
1116 APInt DemandedRHS(NumElts, 0);
1117 for (unsigned i = 0; i != NumElts; ++i) {
1118 if (!DemandedElts[i])
1120 int M = ShuffleMask[i];
1122 // For UNDEF elements, we don't know anything about the common state of
1123 // the shuffle result.
1124 DemandedLHS.clearAllBits();
1125 DemandedRHS.clearAllBits();
1128 assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
1129 if (M < (int)NumElts)
1130 DemandedLHS.setBit(M);
1132 DemandedRHS.setBit(M - NumElts);
1135 if (!!DemandedLHS || !!DemandedRHS) {
1136 SDValue Op0 = Op.getOperand(0);
1137 SDValue Op1 = Op.getOperand(1);
1139 Known.Zero.setAllBits();
1140 Known.One.setAllBits();
1141 if (!!DemandedLHS) {
1142 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO,
1145 Known.One &= Known2.One;
1146 Known.Zero &= Known2.Zero;
1148 if (!!DemandedRHS) {
1149 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO,
1152 Known.One &= Known2.One;
1153 Known.Zero &= Known2.Zero;
1156 // Attempt to avoid multi-use ops if we don't need anything from them.
1157 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1158 Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1);
1159 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1160 Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1);
1161 if (DemandedOp0 || DemandedOp1) {
1162 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1163 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1164 SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask);
1165 return TLO.CombineTo(Op, NewOp);
1171 SDValue Op0 = Op.getOperand(0);
1172 SDValue Op1 = Op.getOperand(1);
1174 // If the RHS is a constant, check to see if the LHS would be zero without
1175 // using the bits from the RHS. Below, we use knowledge about the RHS to
1176 // simplify the LHS, here we're using information from the LHS to simplify
1178 if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) {
1179 // Do not increment Depth here; that can cause an infinite loop.
1180 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
1181 // If the LHS already has zeros where RHSC does, this 'and' is dead.
1182 if ((LHSKnown.Zero & DemandedBits) ==
1183 (~RHSC->getAPIntValue() & DemandedBits))
1184 return TLO.CombineTo(Op, Op0);
1186 // If any of the set bits in the RHS are known zero on the LHS, shrink
1188 if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits,
1192 // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
1193 // constant, but if this 'and' is only clearing bits that were just set by
1194 // the xor, then this 'and' can be eliminated by shrinking the mask of
1195 // the xor. For example, for a 32-bit X:
1196 // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
1197 if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
1198 LHSKnown.One == ~RHSC->getAPIntValue()) {
1199 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1);
1200 return TLO.CombineTo(Op, Xor);
1204 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1207 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1208 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
1209 Known2, TLO, Depth + 1))
1211 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
1213 // Attempt to avoid multi-use ops if we don't need anything from them.
1214 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1215 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1216 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1217 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1218 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1219 if (DemandedOp0 || DemandedOp1) {
1220 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1221 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1222 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1223 return TLO.CombineTo(Op, NewOp);
1227 // If all of the demanded bits are known one on one side, return the other.
1228 // These bits cannot contribute to the result of the 'and'.
1229 if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
1230 return TLO.CombineTo(Op, Op0);
1231 if (DemandedBits.isSubsetOf(Known.Zero | Known2.One))
1232 return TLO.CombineTo(Op, Op1);
1233 // If all of the demanded bits in the inputs are known zeros, return zero.
1234 if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
1235 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT));
1236 // If the RHS is a constant, see if we can simplify it.
1237 if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, DemandedElts,
1240 // If the operation can be done in a smaller type, do so.
1241 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1248 SDValue Op0 = Op.getOperand(0);
1249 SDValue Op1 = Op.getOperand(1);
1251 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1254 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1255 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
1256 Known2, TLO, Depth + 1))
1258 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
1260 // Attempt to avoid multi-use ops if we don't need anything from them.
1261 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1262 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1263 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1264 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1265 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1266 if (DemandedOp0 || DemandedOp1) {
1267 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1268 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1269 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1270 return TLO.CombineTo(Op, NewOp);
1274 // If all of the demanded bits are known zero on one side, return the other.
1275 // These bits cannot contribute to the result of the 'or'.
1276 if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
1277 return TLO.CombineTo(Op, Op0);
1278 if (DemandedBits.isSubsetOf(Known.One | Known2.Zero))
1279 return TLO.CombineTo(Op, Op1);
1280 // If the RHS is a constant, see if we can simplify it.
1281 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1283 // If the operation can be done in a smaller type, do so.
1284 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1291 SDValue Op0 = Op.getOperand(0);
1292 SDValue Op1 = Op.getOperand(1);
1294 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1297 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1298 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO,
1301 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
1303 // Attempt to avoid multi-use ops if we don't need anything from them.
1304 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1305 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1306 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1307 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1308 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1309 if (DemandedOp0 || DemandedOp1) {
1310 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1311 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1312 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1313 return TLO.CombineTo(Op, NewOp);
1317 // If all of the demanded bits are known zero on one side, return the other.
1318 // These bits cannot contribute to the result of the 'xor'.
1319 if (DemandedBits.isSubsetOf(Known.Zero))
1320 return TLO.CombineTo(Op, Op0);
1321 if (DemandedBits.isSubsetOf(Known2.Zero))
1322 return TLO.CombineTo(Op, Op1);
1323 // If the operation can be done in a smaller type, do so.
1324 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1327 // If all of the unknown bits are known to be zero on one side or the other
1328 // (but not both) turn this into an *inclusive* or.
1329 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1330 if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
1331 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
1333 ConstantSDNode* C = isConstOrConstSplat(Op1, DemandedElts);
1335 // If one side is a constant, and all of the known set bits on the other
1336 // side are also set in the constant, turn this into an AND, as we know
1337 // the bits will be cleared.
1338 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1339 // NB: it is okay if more bits are known than are requested
1340 if (C->getAPIntValue() == Known2.One) {
1342 TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT);
1343 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC));
1346 // If the RHS is a constant, see if we can change it. Don't alter a -1
1347 // constant because that's a 'not' op, and that is better for combining
1349 if (!C->isAllOnesValue() &&
1350 DemandedBits.isSubsetOf(C->getAPIntValue())) {
1351 // We're flipping all demanded bits. Flip the undemanded bits too.
1352 SDValue New = TLO.DAG.getNOT(dl, Op0, VT);
1353 return TLO.CombineTo(Op, New);
1357 // If we can't turn this into a 'not', try to shrink the constant.
1358 if (!C || !C->isAllOnesValue())
1359 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1366 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO,
1369 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO,
1372 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1373 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
1375 // If the operands are constants, see if we can simplify them.
1376 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1379 // Only known if known in both the LHS and RHS.
1380 Known.One &= Known2.One;
1381 Known.Zero &= Known2.Zero;
1383 case ISD::SELECT_CC:
1384 if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO,
1387 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO,
1390 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1391 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
1393 // If the operands are constants, see if we can simplify them.
1394 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1397 // Only known if known in both the LHS and RHS.
1398 Known.One &= Known2.One;
1399 Known.Zero &= Known2.Zero;
1402 SDValue Op0 = Op.getOperand(0);
1403 SDValue Op1 = Op.getOperand(1);
1404 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1405 // If (1) we only need the sign-bit, (2) the setcc operands are the same
1406 // width as the setcc result, and (3) the result of a setcc conforms to 0 or
1407 // -1, we may be able to bypass the setcc.
1408 if (DemandedBits.isSignMask() &&
1409 Op0.getScalarValueSizeInBits() == BitWidth &&
1410 getBooleanContents(Op0.getValueType()) ==
1411 BooleanContent::ZeroOrNegativeOneBooleanContent) {
1412 // If we're testing X < 0, then this compare isn't needed - just use X!
1413 // FIXME: We're limiting to integer types here, but this should also work
1414 // if we don't care about FP signed-zero. The use of SETLT with FP means
1415 // that we don't care about NaNs.
1416 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
1417 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
1418 return TLO.CombineTo(Op, Op0);
1420 // TODO: Should we check for other forms of sign-bit comparisons?
1421 // Examples: X <= -1, X >= 0
1423 if (getBooleanContents(Op0.getValueType()) ==
1424 TargetLowering::ZeroOrOneBooleanContent &&
1426 Known.Zero.setBitsFrom(1);
1430 SDValue Op0 = Op.getOperand(0);
1431 SDValue Op1 = Op.getOperand(1);
1432 EVT ShiftVT = Op1.getValueType();
1434 if (const APInt *SA =
1435 TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) {
1436 unsigned ShAmt = SA->getZExtValue();
1438 return TLO.CombineTo(Op, Op0);
1440 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1441 // single shift. We can do this if the bottom bits (which are shifted
1442 // out) are never demanded.
1443 // TODO - support non-uniform vector amounts.
1444 if (Op0.getOpcode() == ISD::SRL) {
1445 if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) {
1446 if (const APInt *SA2 =
1447 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) {
1448 unsigned C1 = SA2->getZExtValue();
1449 unsigned Opc = ISD::SHL;
1450 int Diff = ShAmt - C1;
1455 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT);
1456 return TLO.CombineTo(
1457 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1462 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1463 // are not demanded. This will likely allow the anyext to be folded away.
1464 // TODO - support non-uniform vector amounts.
1465 if (Op0.getOpcode() == ISD::ANY_EXTEND) {
1466 SDValue InnerOp = Op0.getOperand(0);
1467 EVT InnerVT = InnerOp.getValueType();
1468 unsigned InnerBits = InnerVT.getScalarSizeInBits();
1469 if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
1470 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1471 EVT ShTy = getShiftAmountTy(InnerVT, DL);
1472 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1475 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1476 TLO.DAG.getConstant(ShAmt, dl, ShTy));
1477 return TLO.CombineTo(
1478 Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
1481 // Repeat the SHL optimization above in cases where an extension
1482 // intervenes: (shl (anyext (shr x, c1)), c2) to
1483 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
1484 // aren't demanded (as above) and that the shifted upper c1 bits of
1485 // x aren't demanded.
1486 // TODO - support non-uniform vector amounts.
1487 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
1488 InnerOp.hasOneUse()) {
1489 if (const APInt *SA2 =
1490 TLO.DAG.getValidShiftAmountConstant(InnerOp, DemandedElts)) {
1491 unsigned InnerShAmt = SA2->getZExtValue();
1492 if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
1493 DemandedBits.getActiveBits() <=
1494 (InnerBits - InnerShAmt + ShAmt) &&
1495 DemandedBits.countTrailingZeros() >= ShAmt) {
1497 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, ShiftVT);
1498 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
1499 InnerOp.getOperand(0));
1500 return TLO.CombineTo(
1501 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA));
1507 APInt InDemandedMask = DemandedBits.lshr(ShAmt);
1508 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1511 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1512 Known.Zero <<= ShAmt;
1513 Known.One <<= ShAmt;
1514 // low bits known zero.
1515 Known.Zero.setLowBits(ShAmt);
1517 // Try shrinking the operation as long as the shift amount will still be
1519 if ((ShAmt < DemandedBits.getActiveBits()) &&
1520 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1524 // If we are only demanding sign bits then we can use the shift source
1526 if (const APInt *MaxSA =
1527 TLO.DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) {
1528 unsigned ShAmt = MaxSA->getZExtValue();
1529 unsigned NumSignBits =
1530 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
1531 unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
1532 if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
1533 return TLO.CombineTo(Op, Op0);
1538 SDValue Op0 = Op.getOperand(0);
1539 SDValue Op1 = Op.getOperand(1);
1540 EVT ShiftVT = Op1.getValueType();
1542 if (const APInt *SA =
1543 TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) {
1544 unsigned ShAmt = SA->getZExtValue();
1546 return TLO.CombineTo(Op, Op0);
1548 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1549 // single shift. We can do this if the top bits (which are shifted out)
1550 // are never demanded.
1551 // TODO - support non-uniform vector amounts.
1552 if (Op0.getOpcode() == ISD::SHL) {
1553 if (!DemandedBits.intersects(APInt::getHighBitsSet(BitWidth, ShAmt))) {
1554 if (const APInt *SA2 =
1555 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) {
1556 unsigned C1 = SA2->getZExtValue();
1557 unsigned Opc = ISD::SRL;
1558 int Diff = ShAmt - C1;
1563 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT);
1564 return TLO.CombineTo(
1565 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1570 APInt InDemandedMask = (DemandedBits << ShAmt);
1572 // If the shift is exact, then it does demand the low bits (and knows that
1574 if (Op->getFlags().hasExact())
1575 InDemandedMask.setLowBits(ShAmt);
1577 // Compute the new bits that are at the top now.
1578 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1581 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1582 Known.Zero.lshrInPlace(ShAmt);
1583 Known.One.lshrInPlace(ShAmt);
1584 // High bits known zero.
1585 Known.Zero.setHighBits(ShAmt);
1590 SDValue Op0 = Op.getOperand(0);
1591 SDValue Op1 = Op.getOperand(1);
1592 EVT ShiftVT = Op1.getValueType();
1594 // If we only want bits that already match the signbit then we don't need
1596 unsigned NumHiDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
1597 if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >=
1599 return TLO.CombineTo(Op, Op0);
1601 // If this is an arithmetic shift right and only the low-bit is set, we can
1602 // always convert this into a logical shr, even if the shift amount is
1603 // variable. The low bit of the shift cannot be an input sign bit unless
1604 // the shift amount is >= the size of the datatype, which is undefined.
1605 if (DemandedBits.isOneValue())
1606 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
1608 if (const APInt *SA =
1609 TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) {
1610 unsigned ShAmt = SA->getZExtValue();
1612 return TLO.CombineTo(Op, Op0);
1614 APInt InDemandedMask = (DemandedBits << ShAmt);
1616 // If the shift is exact, then it does demand the low bits (and knows that
1618 if (Op->getFlags().hasExact())
1619 InDemandedMask.setLowBits(ShAmt);
1621 // If any of the demanded bits are produced by the sign extension, we also
1622 // demand the input sign bit.
1623 if (DemandedBits.countLeadingZeros() < ShAmt)
1624 InDemandedMask.setSignBit();
1626 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1629 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1630 Known.Zero.lshrInPlace(ShAmt);
1631 Known.One.lshrInPlace(ShAmt);
1633 // If the input sign bit is known to be zero, or if none of the top bits
1634 // are demanded, turn this into an unsigned shift right.
1635 if (Known.Zero[BitWidth - ShAmt - 1] ||
1636 DemandedBits.countLeadingZeros() >= ShAmt) {
1638 Flags.setExact(Op->getFlags().hasExact());
1639 return TLO.CombineTo(
1640 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags));
1643 int Log2 = DemandedBits.exactLogBase2();
1645 // The bit must come from the sign.
1646 SDValue NewSA = TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, ShiftVT);
1647 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA));
1650 if (Known.One[BitWidth - ShAmt - 1])
1651 // New bits are known one.
1652 Known.One.setHighBits(ShAmt);
1654 // Attempt to avoid multi-use ops if we don't need anything from them.
1655 if (!InDemandedMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1656 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1657 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
1659 SDValue NewOp = TLO.DAG.getNode(ISD::SRA, dl, VT, DemandedOp0, Op1);
1660 return TLO.CombineTo(Op, NewOp);
1668 SDValue Op0 = Op.getOperand(0);
1669 SDValue Op1 = Op.getOperand(1);
1670 SDValue Op2 = Op.getOperand(2);
1671 bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
1673 if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) {
1674 unsigned Amt = SA->getAPIntValue().urem(BitWidth);
1676 // For fshl, 0-shift returns the 1st arg.
1677 // For fshr, 0-shift returns the 2nd arg.
1679 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1680 Known, TLO, Depth + 1))
1685 // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt))
1686 // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt)
1687 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
1688 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
1689 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
1692 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO,
1696 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
1697 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
1698 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1699 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1700 Known.One |= Known2.One;
1701 Known.Zero |= Known2.Zero;
1704 // For pow-2 bitwidths we only demand the bottom modulo amt bits.
1705 if (isPowerOf2_32(BitWidth)) {
1706 APInt DemandedAmtBits(Op2.getScalarValueSizeInBits(), BitWidth - 1);
1707 if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts,
1708 Known2, TLO, Depth + 1))
1715 SDValue Op0 = Op.getOperand(0);
1716 SDValue Op1 = Op.getOperand(1);
1718 // If we're rotating an 0/-1 value, then it stays an 0/-1 value.
1719 if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1))
1720 return TLO.CombineTo(Op, Op0);
1722 // For pow-2 bitwidths we only demand the bottom modulo amt bits.
1723 if (isPowerOf2_32(BitWidth)) {
1724 APInt DemandedAmtBits(Op1.getScalarValueSizeInBits(), BitWidth - 1);
1725 if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO,
1731 case ISD::BITREVERSE: {
1732 SDValue Src = Op.getOperand(0);
1733 APInt DemandedSrcBits = DemandedBits.reverseBits();
1734 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
1737 Known.One = Known2.One.reverseBits();
1738 Known.Zero = Known2.Zero.reverseBits();
1742 SDValue Src = Op.getOperand(0);
1743 APInt DemandedSrcBits = DemandedBits.byteSwap();
1744 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
1747 Known.One = Known2.One.byteSwap();
1748 Known.Zero = Known2.Zero.byteSwap();
1751 case ISD::SIGN_EXTEND_INREG: {
1752 SDValue Op0 = Op.getOperand(0);
1753 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1754 unsigned ExVTBits = ExVT.getScalarSizeInBits();
1756 // If we only care about the highest bit, don't bother shifting right.
1757 if (DemandedBits.isSignMask()) {
1758 unsigned NumSignBits =
1759 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
1760 bool AlreadySignExtended = NumSignBits >= BitWidth - ExVTBits + 1;
1761 // However if the input is already sign extended we expect the sign
1762 // extension to be dropped altogether later and do not simplify.
1763 if (!AlreadySignExtended) {
1764 // Compute the correct shift amount type, which must be getShiftAmountTy
1765 // for scalar types after legalization.
1766 EVT ShiftAmtTy = VT;
1767 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1768 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
1771 TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy);
1772 return TLO.CombineTo(Op,
1773 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1777 // If none of the extended bits are demanded, eliminate the sextinreg.
1778 if (DemandedBits.getActiveBits() <= ExVTBits)
1779 return TLO.CombineTo(Op, Op0);
1781 APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits);
1783 // Since the sign extended bits are demanded, we know that the sign
1785 InputDemandedBits.setBit(ExVTBits - 1);
1787 if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1))
1789 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1791 // If the sign bit of the input is known set or clear, then we know the
1792 // top bits of the result.
1794 // If the input sign bit is known zero, convert this into a zero extension.
1795 if (Known.Zero[ExVTBits - 1])
1796 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT));
1798 APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits);
1799 if (Known.One[ExVTBits - 1]) { // Input sign bit known set
1800 Known.One.setBitsFrom(ExVTBits);
1802 } else { // Input sign bit unknown
1808 case ISD::BUILD_PAIR: {
1809 EVT HalfVT = Op.getOperand(0).getValueType();
1810 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
1812 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
1813 APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
1815 KnownBits KnownLo, KnownHi;
1817 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
1820 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1))
1823 Known.Zero = KnownLo.Zero.zext(BitWidth) |
1824 KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth);
1826 Known.One = KnownLo.One.zext(BitWidth) |
1827 KnownHi.One.zext(BitWidth).shl(HalfBitWidth);
1830 case ISD::ZERO_EXTEND:
1831 case ISD::ZERO_EXTEND_VECTOR_INREG: {
1832 SDValue Src = Op.getOperand(0);
1833 EVT SrcVT = Src.getValueType();
1834 unsigned InBits = SrcVT.getScalarSizeInBits();
1835 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1836 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
1838 // If none of the top bits are demanded, convert this into an any_extend.
1839 if (DemandedBits.getActiveBits() <= InBits) {
1840 // If we only need the non-extended bits of the bottom element
1841 // then we can just bitcast to the result.
1842 if (IsVecInReg && DemandedElts == 1 &&
1843 VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1844 TLO.DAG.getDataLayout().isLittleEndian())
1845 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1848 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1849 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1850 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1853 APInt InDemandedBits = DemandedBits.trunc(InBits);
1854 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1855 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1858 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1859 assert(Known.getBitWidth() == InBits && "Src width has changed?");
1860 Known = Known.zext(BitWidth);
1863 case ISD::SIGN_EXTEND:
1864 case ISD::SIGN_EXTEND_VECTOR_INREG: {
1865 SDValue Src = Op.getOperand(0);
1866 EVT SrcVT = Src.getValueType();
1867 unsigned InBits = SrcVT.getScalarSizeInBits();
1868 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1869 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
1871 // If none of the top bits are demanded, convert this into an any_extend.
1872 if (DemandedBits.getActiveBits() <= InBits) {
1873 // If we only need the non-extended bits of the bottom element
1874 // then we can just bitcast to the result.
1875 if (IsVecInReg && DemandedElts == 1 &&
1876 VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1877 TLO.DAG.getDataLayout().isLittleEndian())
1878 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1881 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1882 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1883 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1886 APInt InDemandedBits = DemandedBits.trunc(InBits);
1887 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1889 // Since some of the sign extended bits are demanded, we know that the sign
1891 InDemandedBits.setBit(InBits - 1);
1893 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1896 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1897 assert(Known.getBitWidth() == InBits && "Src width has changed?");
1899 // If the sign bit is known one, the top bits match.
1900 Known = Known.sext(BitWidth);
1902 // If the sign bit is known zero, convert this to a zero extend.
1903 if (Known.isNonNegative()) {
1905 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
1906 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1907 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1911 case ISD::ANY_EXTEND:
1912 case ISD::ANY_EXTEND_VECTOR_INREG: {
1913 SDValue Src = Op.getOperand(0);
1914 EVT SrcVT = Src.getValueType();
1915 unsigned InBits = SrcVT.getScalarSizeInBits();
1916 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1917 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
1919 // If we only need the bottom element then we can just bitcast.
1920 // TODO: Handle ANY_EXTEND?
1921 if (IsVecInReg && DemandedElts == 1 &&
1922 VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1923 TLO.DAG.getDataLayout().isLittleEndian())
1924 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1926 APInt InDemandedBits = DemandedBits.trunc(InBits);
1927 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1928 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1931 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1932 assert(Known.getBitWidth() == InBits && "Src width has changed?");
1933 Known = Known.anyext(BitWidth);
1935 // Attempt to avoid multi-use ops if we don't need anything from them.
1936 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1937 Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1))
1938 return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc));
1941 case ISD::TRUNCATE: {
1942 SDValue Src = Op.getOperand(0);
1944 // Simplify the input, using demanded bit information, and compute the known
1945 // zero/one bits live out.
1946 unsigned OperandBitWidth = Src.getScalarValueSizeInBits();
1947 APInt TruncMask = DemandedBits.zext(OperandBitWidth);
1948 if (SimplifyDemandedBits(Src, TruncMask, Known, TLO, Depth + 1))
1950 Known = Known.trunc(BitWidth);
1952 // Attempt to avoid multi-use ops if we don't need anything from them.
1953 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1954 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1))
1955 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc));
1957 // If the input is only used by this truncate, see if we can shrink it based
1958 // on the known demanded bits.
1959 if (Src.getNode()->hasOneUse()) {
1960 switch (Src.getOpcode()) {
1964 // Shrink SRL by a constant if none of the high bits shifted in are
1966 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT))
1967 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1971 SDValue ShAmt = Src.getOperand(1);
1972 auto *ShAmtC = dyn_cast<ConstantSDNode>(ShAmt);
1973 if (!ShAmtC || ShAmtC->getAPIntValue().uge(BitWidth))
1975 uint64_t ShVal = ShAmtC->getZExtValue();
1978 APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth);
1979 HighBits.lshrInPlace(ShVal);
1980 HighBits = HighBits.trunc(BitWidth);
1982 if (!(HighBits & DemandedBits)) {
1983 // None of the shifted in bits are needed. Add a truncate of the
1984 // shift input, then shift it.
1985 if (TLO.LegalTypes())
1986 ShAmt = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL));
1988 TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
1989 return TLO.CombineTo(
1990 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, ShAmt));
1996 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1999 case ISD::AssertZext: {
2000 // AssertZext demands all of the high bits, plus any of the low bits
2001 // demanded by its users.
2002 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2003 APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits());
2004 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known,
2007 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
2009 Known.Zero |= ~InMask;
2012 case ISD::EXTRACT_VECTOR_ELT: {
2013 SDValue Src = Op.getOperand(0);
2014 SDValue Idx = Op.getOperand(1);
2015 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2016 unsigned EltBitWidth = Src.getScalarValueSizeInBits();
2018 // Demand the bits from every vector element without a constant index.
2019 APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts);
2020 if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx))
2021 if (CIdx->getAPIntValue().ult(NumSrcElts))
2022 DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue());
2024 // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
2025 // anything about the extended bits.
2026 APInt DemandedSrcBits = DemandedBits;
2027 if (BitWidth > EltBitWidth)
2028 DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth);
2030 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO,
2034 // Attempt to avoid multi-use ops if we don't need anything from them.
2035 if (!DemandedSrcBits.isAllOnesValue() ||
2036 !DemandedSrcElts.isAllOnesValue()) {
2037 if (SDValue DemandedSrc = SimplifyMultipleUseDemandedBits(
2038 Src, DemandedSrcBits, DemandedSrcElts, TLO.DAG, Depth + 1)) {
2040 TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, Idx);
2041 return TLO.CombineTo(Op, NewOp);
2046 if (BitWidth > EltBitWidth)
2047 Known = Known.anyext(BitWidth);
2050 case ISD::BITCAST: {
2051 SDValue Src = Op.getOperand(0);
2052 EVT SrcVT = Src.getValueType();
2053 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
2055 // If this is an FP->Int bitcast and if the sign bit is the only
2056 // thing demanded, turn this into a FGETSIGN.
2057 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() &&
2058 DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) &&
2059 SrcVT.isFloatingPoint()) {
2060 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
2061 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
2062 if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 &&
2063 SrcVT != MVT::f128) {
2064 // Cannot eliminate/lower SHL for f128 yet.
2065 EVT Ty = OpVTLegal ? VT : MVT::i32;
2066 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
2067 // place. We expect the SHL to be eliminated by other optimizations.
2068 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src);
2069 unsigned OpVTSizeInBits = Op.getValueSizeInBits();
2070 if (!OpVTLegal && OpVTSizeInBits > 32)
2071 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign);
2072 unsigned ShVal = Op.getValueSizeInBits() - 1;
2073 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT);
2074 return TLO.CombineTo(Op,
2075 TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt));
2079 // Bitcast from a vector using SimplifyDemanded Bits/VectorElts.
2080 // Demand the elt/bit if any of the original elts/bits are demanded.
2081 // TODO - bigendian once we have test coverage.
2082 if (SrcVT.isVector() && (BitWidth % NumSrcEltBits) == 0 &&
2083 TLO.DAG.getDataLayout().isLittleEndian()) {
2084 unsigned Scale = BitWidth / NumSrcEltBits;
2085 unsigned NumSrcElts = SrcVT.getVectorNumElements();
2086 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
2087 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
2088 for (unsigned i = 0; i != Scale; ++i) {
2089 unsigned Offset = i * NumSrcEltBits;
2090 APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset);
2091 if (!Sub.isNullValue()) {
2092 DemandedSrcBits |= Sub;
2093 for (unsigned j = 0; j != NumElts; ++j)
2094 if (DemandedElts[j])
2095 DemandedSrcElts.setBit((j * Scale) + i);
2099 APInt KnownSrcUndef, KnownSrcZero;
2100 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
2101 KnownSrcZero, TLO, Depth + 1))
2104 KnownBits KnownSrcBits;
2105 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
2106 KnownSrcBits, TLO, Depth + 1))
2108 } else if ((NumSrcEltBits % BitWidth) == 0 &&
2109 TLO.DAG.getDataLayout().isLittleEndian()) {
2110 unsigned Scale = NumSrcEltBits / BitWidth;
2111 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
2112 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
2113 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
2114 for (unsigned i = 0; i != NumElts; ++i)
2115 if (DemandedElts[i]) {
2116 unsigned Offset = (i % Scale) * BitWidth;
2117 DemandedSrcBits.insertBits(DemandedBits, Offset);
2118 DemandedSrcElts.setBit(i / Scale);
2121 if (SrcVT.isVector()) {
2122 APInt KnownSrcUndef, KnownSrcZero;
2123 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
2124 KnownSrcZero, TLO, Depth + 1))
2128 KnownBits KnownSrcBits;
2129 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
2130 KnownSrcBits, TLO, Depth + 1))
2134 // If this is a bitcast, let computeKnownBits handle it. Only do this on a
2135 // recursive call where Known may be useful to the caller.
2137 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
2145 // Add, Sub, and Mul don't demand any bits in positions beyond that
2146 // of the highest bit demanded of them.
2147 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
2148 SDNodeFlags Flags = Op.getNode()->getFlags();
2149 unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros();
2150 APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ);
2151 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO,
2153 SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO,
2155 // See if the operation should be performed at a smaller bit width.
2156 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) {
2157 if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
2158 // Disable the nsw and nuw flags. We can no longer guarantee that we
2159 // won't wrap after simplification.
2160 Flags.setNoSignedWrap(false);
2161 Flags.setNoUnsignedWrap(false);
2163 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
2164 return TLO.CombineTo(Op, NewOp);
2169 // Attempt to avoid multi-use ops if we don't need anything from them.
2170 if (!LoMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
2171 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
2172 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2173 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
2174 Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2175 if (DemandedOp0 || DemandedOp1) {
2176 Flags.setNoSignedWrap(false);
2177 Flags.setNoUnsignedWrap(false);
2178 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
2179 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
2181 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
2182 return TLO.CombineTo(Op, NewOp);
2186 // If we have a constant operand, we may be able to turn it into -1 if we
2187 // do not demand the high bits. This can make the constant smaller to
2188 // encode, allow more general folding, or match specialized instruction
2189 // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that
2190 // is probably not useful (and could be detrimental).
2191 ConstantSDNode *C = isConstOrConstSplat(Op1);
2192 APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ);
2193 if (C && !C->isAllOnesValue() && !C->isOne() &&
2194 (C->getAPIntValue() | HighMask).isAllOnesValue()) {
2195 SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT);
2196 // Disable the nsw and nuw flags. We can no longer guarantee that we
2197 // won't wrap after simplification.
2198 Flags.setNoSignedWrap(false);
2199 Flags.setNoUnsignedWrap(false);
2200 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
2201 return TLO.CombineTo(Op, NewOp);
2207 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
2208 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts,
2214 // Just use computeKnownBits to compute output bits.
2215 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
2219 // If we know the value of all of the demanded bits, return this as a
2221 if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) {
2222 // Avoid folding to a constant if any OpaqueConstant is involved.
2223 const SDNode *N = Op.getNode();
2224 for (SDNodeIterator I = SDNodeIterator::begin(N),
2225 E = SDNodeIterator::end(N);
2228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
2232 // TODO: Handle float bits as well.
2234 return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
2240 bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
2241 const APInt &DemandedElts,
2244 DAGCombinerInfo &DCI) const {
2245 SelectionDAG &DAG = DCI.DAG;
2246 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2247 !DCI.isBeforeLegalizeOps());
2250 SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
2252 DCI.AddToWorklist(Op.getNode());
2253 DCI.CommitTargetLoweringOpt(TLO);
2259 /// Given a vector binary operation and known undefined elements for each input
2260 /// operand, compute whether each element of the output is undefined.
2261 static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG,
2262 const APInt &UndefOp0,
2263 const APInt &UndefOp1) {
2264 EVT VT = BO.getValueType();
2265 assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&
2266 "Vector binop only");
2268 EVT EltVT = VT.getVectorElementType();
2269 unsigned NumElts = VT.getVectorNumElements();
2270 assert(UndefOp0.getBitWidth() == NumElts &&
2271 UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis");
2273 auto getUndefOrConstantElt = [&](SDValue V, unsigned Index,
2274 const APInt &UndefVals) {
2275 if (UndefVals[Index])
2276 return DAG.getUNDEF(EltVT);
2278 if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2279 // Try hard to make sure that the getNode() call is not creating temporary
2280 // nodes. Ignore opaque integers because they do not constant fold.
2281 SDValue Elt = BV->getOperand(Index);
2282 auto *C = dyn_cast<ConstantSDNode>(Elt);
2283 if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque()))
2290 APInt KnownUndef = APInt::getNullValue(NumElts);
2291 for (unsigned i = 0; i != NumElts; ++i) {
2292 // If both inputs for this element are either constant or undef and match
2293 // the element type, compute the constant/undef result for this element of
2295 // TODO: Ideally we would use FoldConstantArithmetic() here, but that does
2296 // not handle FP constants. The code within getNode() should be refactored
2297 // to avoid the danger of creating a bogus temporary node here.
2298 SDValue C0 = getUndefOrConstantElt(BO.getOperand(0), i, UndefOp0);
2299 SDValue C1 = getUndefOrConstantElt(BO.getOperand(1), i, UndefOp1);
2300 if (C0 && C1 && C0.getValueType() == EltVT && C1.getValueType() == EltVT)
2301 if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef())
2302 KnownUndef.setBit(i);
2307 bool TargetLowering::SimplifyDemandedVectorElts(
2308 SDValue Op, const APInt &OriginalDemandedElts, APInt &KnownUndef,
2309 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth,
2310 bool AssumeSingleUse) const {
2311 EVT VT = Op.getValueType();
2312 unsigned Opcode = Op.getOpcode();
2313 APInt DemandedElts = OriginalDemandedElts;
2314 unsigned NumElts = DemandedElts.getBitWidth();
2315 assert(VT.isVector() && "Expected vector op");
2317 KnownUndef = KnownZero = APInt::getNullValue(NumElts);
2319 // TODO: For now we assume we know nothing about scalable vectors.
2320 if (VT.isScalableVector())
2323 assert(VT.getVectorNumElements() == NumElts &&
2324 "Mask size mismatches value type element count!");
2328 KnownUndef.setAllBits();
2332 // If Op has other users, assume that all elements are needed.
2333 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse)
2334 DemandedElts.setAllBits();
2336 // Not demanding any elements from Op.
2337 if (DemandedElts == 0) {
2338 KnownUndef.setAllBits();
2339 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2342 // Limit search depth.
2343 if (Depth >= SelectionDAG::MaxRecursionDepth)
2347 unsigned EltSizeInBits = VT.getScalarSizeInBits();
2349 // Helper for demanding the specified elements and all the bits of both binary
2351 auto SimplifyDemandedVectorEltsBinOp = [&](SDValue Op0, SDValue Op1) {
2352 SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts,
2353 TLO.DAG, Depth + 1);
2354 SDValue NewOp1 = SimplifyMultipleUseDemandedVectorElts(Op1, DemandedElts,
2355 TLO.DAG, Depth + 1);
2356 if (NewOp0 || NewOp1) {
2357 SDValue NewOp = TLO.DAG.getNode(
2358 Opcode, SDLoc(Op), VT, NewOp0 ? NewOp0 : Op0, NewOp1 ? NewOp1 : Op1);
2359 return TLO.CombineTo(Op, NewOp);
2365 case ISD::SCALAR_TO_VECTOR: {
2366 if (!DemandedElts[0]) {
2367 KnownUndef.setAllBits();
2368 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2370 KnownUndef.setHighBits(NumElts - 1);
2373 case ISD::BITCAST: {
2374 SDValue Src = Op.getOperand(0);
2375 EVT SrcVT = Src.getValueType();
2377 // We only handle vectors here.
2378 // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits?
2379 if (!SrcVT.isVector())
2382 // Fast handling of 'identity' bitcasts.
2383 unsigned NumSrcElts = SrcVT.getVectorNumElements();
2384 if (NumSrcElts == NumElts)
2385 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
2386 KnownZero, TLO, Depth + 1);
2388 APInt SrcZero, SrcUndef;
2389 APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts);
2391 // Bitcast from 'large element' src vector to 'small element' vector, we
2392 // must demand a source element if any DemandedElt maps to it.
2393 if ((NumElts % NumSrcElts) == 0) {
2394 unsigned Scale = NumElts / NumSrcElts;
2395 for (unsigned i = 0; i != NumElts; ++i)
2396 if (DemandedElts[i])
2397 SrcDemandedElts.setBit(i / Scale);
2399 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
2403 // Try calling SimplifyDemandedBits, converting demanded elts to the bits
2404 // of the large element.
2405 // TODO - bigendian once we have test coverage.
2406 if (TLO.DAG.getDataLayout().isLittleEndian()) {
2407 unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits();
2408 APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits);
2409 for (unsigned i = 0; i != NumElts; ++i)
2410 if (DemandedElts[i]) {
2411 unsigned Ofs = (i % Scale) * EltSizeInBits;
2412 SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits);
2416 if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcDemandedElts, Known,
2421 // If the src element is zero/undef then all the output elements will be -
2422 // only demanded elements are guaranteed to be correct.
2423 for (unsigned i = 0; i != NumSrcElts; ++i) {
2424 if (SrcDemandedElts[i]) {
2426 KnownZero.setBits(i * Scale, (i + 1) * Scale);
2428 KnownUndef.setBits(i * Scale, (i + 1) * Scale);
2433 // Bitcast from 'small element' src vector to 'large element' vector, we
2434 // demand all smaller source elements covered by the larger demanded element
2436 if ((NumSrcElts % NumElts) == 0) {
2437 unsigned Scale = NumSrcElts / NumElts;
2438 for (unsigned i = 0; i != NumElts; ++i)
2439 if (DemandedElts[i])
2440 SrcDemandedElts.setBits(i * Scale, (i + 1) * Scale);
2442 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
2446 // If all the src elements covering an output element are zero/undef, then
2447 // the output element will be as well, assuming it was demanded.
2448 for (unsigned i = 0; i != NumElts; ++i) {
2449 if (DemandedElts[i]) {
2450 if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue())
2451 KnownZero.setBit(i);
2452 if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue())
2453 KnownUndef.setBit(i);
2459 case ISD::BUILD_VECTOR: {
2460 // Check all elements and simplify any unused elements with UNDEF.
2461 if (!DemandedElts.isAllOnesValue()) {
2462 // Don't simplify BROADCASTS.
2463 if (llvm::any_of(Op->op_values(),
2464 [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
2465 SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
2466 bool Updated = false;
2467 for (unsigned i = 0; i != NumElts; ++i) {
2468 if (!DemandedElts[i] && !Ops[i].isUndef()) {
2469 Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType());
2470 KnownUndef.setBit(i);
2475 return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops));
2478 for (unsigned i = 0; i != NumElts; ++i) {
2479 SDValue SrcOp = Op.getOperand(i);
2480 if (SrcOp.isUndef()) {
2481 KnownUndef.setBit(i);
2482 } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() &&
2483 (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) {
2484 KnownZero.setBit(i);
2489 case ISD::CONCAT_VECTORS: {
2490 EVT SubVT = Op.getOperand(0).getValueType();
2491 unsigned NumSubVecs = Op.getNumOperands();
2492 unsigned NumSubElts = SubVT.getVectorNumElements();
2493 for (unsigned i = 0; i != NumSubVecs; ++i) {
2494 SDValue SubOp = Op.getOperand(i);
2495 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
2496 APInt SubUndef, SubZero;
2497 if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
2500 KnownUndef.insertBits(SubUndef, i * NumSubElts);
2501 KnownZero.insertBits(SubZero, i * NumSubElts);
2505 case ISD::INSERT_SUBVECTOR: {
2506 // Demand any elements from the subvector and the remainder from the src its
2508 SDValue Src = Op.getOperand(0);
2509 SDValue Sub = Op.getOperand(1);
2510 uint64_t Idx = Op.getConstantOperandVal(2);
2511 unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
2512 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
2513 APInt DemandedSrcElts = DemandedElts;
2514 DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx);
2516 APInt SubUndef, SubZero;
2517 if (SimplifyDemandedVectorElts(Sub, DemandedSubElts, SubUndef, SubZero, TLO,
2521 // If none of the src operand elements are demanded, replace it with undef.
2522 if (!DemandedSrcElts && !Src.isUndef())
2523 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
2524 TLO.DAG.getUNDEF(VT), Sub,
2527 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownUndef, KnownZero,
2530 KnownUndef.insertBits(SubUndef, Idx);
2531 KnownZero.insertBits(SubZero, Idx);
2533 // Attempt to avoid multi-use ops if we don't need anything from them.
2534 if (!DemandedSrcElts.isAllOnesValue() ||
2535 !DemandedSubElts.isAllOnesValue()) {
2536 SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts(
2537 Src, DemandedSrcElts, TLO.DAG, Depth + 1);
2538 SDValue NewSub = SimplifyMultipleUseDemandedVectorElts(
2539 Sub, DemandedSubElts, TLO.DAG, Depth + 1);
2540 if (NewSrc || NewSub) {
2541 NewSrc = NewSrc ? NewSrc : Src;
2542 NewSub = NewSub ? NewSub : Sub;
2543 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, NewSrc,
2544 NewSub, Op.getOperand(2));
2545 return TLO.CombineTo(Op, NewOp);
2550 case ISD::EXTRACT_SUBVECTOR: {
2551 // Offset the demanded elts by the subvector index.
2552 SDValue Src = Op.getOperand(0);
2553 if (Src.getValueType().isScalableVector())
2555 uint64_t Idx = Op.getConstantOperandVal(1);
2556 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2557 APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
2559 APInt SrcUndef, SrcZero;
2560 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
2563 KnownUndef = SrcUndef.extractBits(NumElts, Idx);
2564 KnownZero = SrcZero.extractBits(NumElts, Idx);
2566 // Attempt to avoid multi-use ops if we don't need anything from them.
2567 if (!DemandedElts.isAllOnesValue()) {
2568 SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts(
2569 Src, DemandedSrcElts, TLO.DAG, Depth + 1);
2571 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, NewSrc,
2573 return TLO.CombineTo(Op, NewOp);
2578 case ISD::INSERT_VECTOR_ELT: {
2579 SDValue Vec = Op.getOperand(0);
2580 SDValue Scl = Op.getOperand(1);
2581 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2583 // For a legal, constant insertion index, if we don't need this insertion
2584 // then strip it, else remove it from the demanded elts.
2585 if (CIdx && CIdx->getAPIntValue().ult(NumElts)) {
2586 unsigned Idx = CIdx->getZExtValue();
2587 if (!DemandedElts[Idx])
2588 return TLO.CombineTo(Op, Vec);
2590 APInt DemandedVecElts(DemandedElts);
2591 DemandedVecElts.clearBit(Idx);
2592 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
2593 KnownZero, TLO, Depth + 1))
2596 KnownUndef.clearBit(Idx);
2598 KnownUndef.setBit(Idx);
2600 KnownZero.clearBit(Idx);
2601 if (isNullConstant(Scl) || isNullFPConstant(Scl))
2602 KnownZero.setBit(Idx);
2606 APInt VecUndef, VecZero;
2607 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
2610 // Without knowing the insertion index we can't set KnownUndef/KnownZero.
2613 case ISD::VSELECT: {
2614 // Try to transform the select condition based on the current demanded
2616 // TODO: If a condition element is undef, we can choose from one arm of the
2617 // select (and if one arm is undef, then we can propagate that to the
2619 // TODO - add support for constant vselect masks (see IR version of this).
2620 APInt UnusedUndef, UnusedZero;
2621 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
2622 UnusedZero, TLO, Depth + 1))
2625 // See if we can simplify either vselect operand.
2626 APInt DemandedLHS(DemandedElts);
2627 APInt DemandedRHS(DemandedElts);
2628 APInt UndefLHS, ZeroLHS;
2629 APInt UndefRHS, ZeroRHS;
2630 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS,
2631 ZeroLHS, TLO, Depth + 1))
2633 if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS,
2634 ZeroRHS, TLO, Depth + 1))
2637 KnownUndef = UndefLHS & UndefRHS;
2638 KnownZero = ZeroLHS & ZeroRHS;
2641 case ISD::VECTOR_SHUFFLE: {
2642 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
2644 // Collect demanded elements from shuffle operands..
2645 APInt DemandedLHS(NumElts, 0);
2646 APInt DemandedRHS(NumElts, 0);
2647 for (unsigned i = 0; i != NumElts; ++i) {
2648 int M = ShuffleMask[i];
2649 if (M < 0 || !DemandedElts[i])
2651 assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
2652 if (M < (int)NumElts)
2653 DemandedLHS.setBit(M);
2655 DemandedRHS.setBit(M - NumElts);
2658 // See if we can simplify either shuffle operand.
2659 APInt UndefLHS, ZeroLHS;
2660 APInt UndefRHS, ZeroRHS;
2661 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS,
2662 ZeroLHS, TLO, Depth + 1))
2664 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS,
2665 ZeroRHS, TLO, Depth + 1))
2668 // Simplify mask using undef elements from LHS/RHS.
2669 bool Updated = false;
2670 bool IdentityLHS = true, IdentityRHS = true;
2671 SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end());
2672 for (unsigned i = 0; i != NumElts; ++i) {
2673 int &M = NewMask[i];
2676 if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
2677 (M >= (int)NumElts && UndefRHS[M - NumElts])) {
2681 IdentityLHS &= (M < 0) || (M == (int)i);
2682 IdentityRHS &= (M < 0) || ((M - NumElts) == i);
2685 // Update legal shuffle masks based on demanded elements if it won't reduce
2686 // to Identity which can cause premature removal of the shuffle mask.
2687 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) {
2688 SDValue LegalShuffle =
2689 buildLegalVectorShuffle(VT, DL, Op.getOperand(0), Op.getOperand(1),
2692 return TLO.CombineTo(Op, LegalShuffle);
2695 // Propagate undef/zero elements from LHS/RHS.
2696 for (unsigned i = 0; i != NumElts; ++i) {
2697 int M = ShuffleMask[i];
2699 KnownUndef.setBit(i);
2700 } else if (M < (int)NumElts) {
2702 KnownUndef.setBit(i);
2704 KnownZero.setBit(i);
2706 if (UndefRHS[M - NumElts])
2707 KnownUndef.setBit(i);
2708 if (ZeroRHS[M - NumElts])
2709 KnownZero.setBit(i);
2714 case ISD::ANY_EXTEND_VECTOR_INREG:
2715 case ISD::SIGN_EXTEND_VECTOR_INREG:
2716 case ISD::ZERO_EXTEND_VECTOR_INREG: {
2717 APInt SrcUndef, SrcZero;
2718 SDValue Src = Op.getOperand(0);
2719 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2720 APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts);
2721 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
2724 KnownZero = SrcZero.zextOrTrunc(NumElts);
2725 KnownUndef = SrcUndef.zextOrTrunc(NumElts);
2727 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
2728 Op.getValueSizeInBits() == Src.getValueSizeInBits() &&
2729 DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) {
2730 // aext - if we just need the bottom element then we can bitcast.
2731 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
2734 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
2735 // zext(undef) upper bits are guaranteed to be zero.
2736 if (DemandedElts.isSubsetOf(KnownUndef))
2737 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
2738 KnownUndef.clearAllBits();
2743 // TODO: There are more binop opcodes that could be handled here - MIN,
2744 // MAX, saturated math, etc.
2754 SDValue Op0 = Op.getOperand(0);
2755 SDValue Op1 = Op.getOperand(1);
2757 APInt UndefRHS, ZeroRHS;
2758 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO,
2761 APInt UndefLHS, ZeroLHS;
2762 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
2766 KnownZero = ZeroLHS & ZeroRHS;
2767 KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS);
2769 // Attempt to avoid multi-use ops if we don't need anything from them.
2770 // TODO - use KnownUndef to relax the demandedelts?
2771 if (!DemandedElts.isAllOnesValue())
2772 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
2781 SDValue Op0 = Op.getOperand(0);
2782 SDValue Op1 = Op.getOperand(1);
2784 APInt UndefRHS, ZeroRHS;
2785 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO,
2788 APInt UndefLHS, ZeroLHS;
2789 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
2793 KnownZero = ZeroLHS;
2794 KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop?
2796 // Attempt to avoid multi-use ops if we don't need anything from them.
2797 // TODO - use KnownUndef to relax the demandedelts?
2798 if (!DemandedElts.isAllOnesValue())
2799 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
2805 SDValue Op0 = Op.getOperand(0);
2806 SDValue Op1 = Op.getOperand(1);
2808 APInt SrcUndef, SrcZero;
2809 if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO,
2812 if (SimplifyDemandedVectorElts(Op0, DemandedElts, KnownUndef, KnownZero,
2816 // If either side has a zero element, then the result element is zero, even
2817 // if the other is an UNDEF.
2818 // TODO: Extend getKnownUndefForVectorBinop to also deal with known zeros
2819 // and then handle 'and' nodes with the rest of the binop opcodes.
2820 KnownZero |= SrcZero;
2821 KnownUndef &= SrcUndef;
2822 KnownUndef &= ~KnownZero;
2824 // Attempt to avoid multi-use ops if we don't need anything from them.
2825 // TODO - use KnownUndef to relax the demandedelts?
2826 if (!DemandedElts.isAllOnesValue())
2827 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
2832 case ISD::SIGN_EXTEND:
2833 case ISD::ZERO_EXTEND:
2834 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2835 KnownZero, TLO, Depth + 1))
2838 if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2839 // zext(undef) upper bits are guaranteed to be zero.
2840 if (DemandedElts.isSubsetOf(KnownUndef))
2841 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
2842 KnownUndef.clearAllBits();
2846 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
2847 if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
2848 KnownZero, TLO, Depth))
2852 APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits);
2853 if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known,
2854 TLO, Depth, AssumeSingleUse))
2860 assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero");
2862 // Constant fold all undef cases.
2863 // TODO: Handle zero cases as well.
2864 if (DemandedElts.isSubsetOf(KnownUndef))
2865 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2870 /// Determine which of the bits specified in Mask are known to be either zero or
2871 /// one and return them in the Known.
2872 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
2874 const APInt &DemandedElts,
2875 const SelectionDAG &DAG,
2876 unsigned Depth) const {
2877 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2878 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2879 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2880 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2881 "Should use MaskedValueIsZero if you don't know whether Op"
2882 " is a target node!");
2886 void TargetLowering::computeKnownBitsForTargetInstr(
2887 GISelKnownBits &Analysis, Register R, KnownBits &Known,
2888 const APInt &DemandedElts, const MachineRegisterInfo &MRI,
2889 unsigned Depth) const {
2893 void TargetLowering::computeKnownBitsForFrameIndex(
2894 const int FrameIdx, KnownBits &Known, const MachineFunction &MF) const {
2895 // The low bits are known zero if the pointer is aligned.
2896 Known.Zero.setLowBits(Log2(MF.getFrameInfo().getObjectAlign(FrameIdx)));
2899 Align TargetLowering::computeKnownAlignForTargetInstr(
2900 GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI,
2901 unsigned Depth) const {
2905 /// This method can be implemented by targets that want to expose additional
2906 /// information about sign bits to the DAG Combiner.
2907 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
2909 const SelectionDAG &,
2910 unsigned Depth) const {
2911 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2912 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2913 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2914 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2915 "Should use ComputeNumSignBits if you don't know whether Op"
2916 " is a target node!");
2920 unsigned TargetLowering::computeNumSignBitsForTargetInstr(
2921 GISelKnownBits &Analysis, Register R, const APInt &DemandedElts,
2922 const MachineRegisterInfo &MRI, unsigned Depth) const {
2926 bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
2927 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
2928 TargetLoweringOpt &TLO, unsigned Depth) const {
2929 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2930 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2931 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2932 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2933 "Should use SimplifyDemandedVectorElts if you don't know whether Op"
2934 " is a target node!");
2938 bool TargetLowering::SimplifyDemandedBitsForTargetNode(
2939 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
2940 KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const {
2941 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2942 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2943 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2944 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2945 "Should use SimplifyDemandedBits if you don't know whether Op"
2946 " is a target node!");
2947 computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
2951 SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
2952 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
2953 SelectionDAG &DAG, unsigned Depth) const {
2955 (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2956 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2957 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2958 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2959 "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
2960 " is a target node!");
2965 TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
2966 SDValue N1, MutableArrayRef<int> Mask,
2967 SelectionDAG &DAG) const {
2968 bool LegalMask = isShuffleMaskLegal(Mask, VT);
2971 ShuffleVectorSDNode::commuteMask(Mask);
2972 LegalMask = isShuffleMaskLegal(Mask, VT);
2978 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask);
2981 const Constant *TargetLowering::getTargetConstantFromLoad(LoadSDNode*) const {
2985 bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
2986 const SelectionDAG &DAG,
2988 unsigned Depth) const {
2989 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2990 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2991 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2992 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2993 "Should use isKnownNeverNaN if you don't know whether Op"
2994 " is a target node!");
2998 // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
2999 // work with truncating build vectors and vectors with elements of less than
3001 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
3006 if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
3007 CVal = CN->getAPIntValue();
3008 } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) {
3009 auto *CN = BV->getConstantSplatNode();
3013 // If this is a truncating build vector, truncate the splat value.
3014 // Otherwise, we may fail to match the expected values below.
3015 unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits();
3016 CVal = CN->getAPIntValue();
3017 if (BVEltWidth < CVal.getBitWidth())
3018 CVal = CVal.trunc(BVEltWidth);
3023 switch (getBooleanContents(N->getValueType(0))) {
3024 case UndefinedBooleanContent:
3026 case ZeroOrOneBooleanContent:
3027 return CVal.isOneValue();
3028 case ZeroOrNegativeOneBooleanContent:
3029 return CVal.isAllOnesValue();
3032 llvm_unreachable("Invalid boolean contents");
3035 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
3039 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
3041 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
3045 // Only interested in constant splats, we don't care about undef
3046 // elements in identifying boolean constants and getConstantSplatNode
3047 // returns NULL if all ops are undef;
3048 CN = BV->getConstantSplatNode();
3053 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
3054 return !CN->getAPIntValue()[0];
3056 return CN->isNullValue();
3059 bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT,
3064 TargetLowering::BooleanContent Cnt = getBooleanContents(VT);
3066 case TargetLowering::ZeroOrOneBooleanContent:
3067 // An extended value of 1 is always true, unless its original type is i1,
3068 // in which case it will be sign extended to -1.
3069 return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1));
3070 case TargetLowering::UndefinedBooleanContent:
3071 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3072 return N->isAllOnesValue() && SExt;
3074 llvm_unreachable("Unexpected enumeration.");
3077 /// This helper function of SimplifySetCC tries to optimize the comparison when
3078 /// either operand of the SetCC node is a bitwise-and instruction.
3079 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3080 ISD::CondCode Cond, const SDLoc &DL,
3081 DAGCombinerInfo &DCI) const {
3082 // Match these patterns in any of their permutations:
3085 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
3088 EVT OpVT = N0.getValueType();
3089 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
3090 (Cond != ISD::SETEQ && Cond != ISD::SETNE))
3094 if (N0.getOperand(0) == N1) {
3095 X = N0.getOperand(1);
3096 Y = N0.getOperand(0);
3097 } else if (N0.getOperand(1) == N1) {
3098 X = N0.getOperand(0);
3099 Y = N0.getOperand(1);
3104 SelectionDAG &DAG = DCI.DAG;
3105 SDValue Zero = DAG.getConstant(0, DL, OpVT);
3106 if (DAG.isKnownToBeAPowerOfTwo(Y)) {
3107 // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set.
3108 // Note that where Y is variable and is known to have at most one bit set
3109 // (for example, if it is Z & 1) we cannot do this; the expressions are not
3110 // equivalent when Y == 0.
3111 assert(OpVT.isInteger());
3112 Cond = ISD::getSetCCInverse(Cond, OpVT);
3113 if (DCI.isBeforeLegalizeOps() ||
3114 isCondCodeLegal(Cond, N0.getSimpleValueType()))
3115 return DAG.getSetCC(DL, VT, N0, Zero, Cond);
3116 } else if (N0.hasOneUse() && hasAndNotCompare(Y)) {
3117 // If the target supports an 'and-not' or 'and-complement' logic operation,
3118 // try to use that to make a comparison operation more efficient.
3119 // But don't do this transform if the mask is a single bit because there are
3120 // more efficient ways to deal with that case (for example, 'bt' on x86 or
3121 // 'rlwinm' on PPC).
3123 // Bail out if the compare operand that we want to turn into a zero is
3124 // already a zero (otherwise, infinite loop).
3125 auto *YConst = dyn_cast<ConstantSDNode>(Y);
3126 if (YConst && YConst->isNullValue())
3129 // Transform this into: ~X & Y == 0.
3130 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT);
3131 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
3132 return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond);
3138 /// There are multiple IR patterns that could be checking whether certain
3139 /// truncation of a signed number would be lossy or not. The pattern which is
3140 /// best at IR level, may not lower optimally. Thus, we want to unfold it.
3141 /// We are looking for the following pattern: (KeptBits is a constant)
3142 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
3143 /// KeptBits won't be bitwidth(x), that will be constant-folded to true/false.
3144 /// KeptBits also can't be 1, that would have been folded to %x dstcond 0
3145 /// We will unfold it into the natural trunc+sext pattern:
3146 /// ((%x << C) a>> C) dstcond %x
3147 /// Where C = bitwidth(x) - KeptBits and C u< bitwidth(x)
3148 SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
3149 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI,
3150 const SDLoc &DL) const {
3151 // We must be comparing with a constant.
3153 if (!(C1 = dyn_cast<ConstantSDNode>(N1)))
3156 // N0 should be: add %x, (1 << (KeptBits-1))
3157 if (N0->getOpcode() != ISD::ADD)
3160 // And we must be 'add'ing a constant.
3161 ConstantSDNode *C01;
3162 if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1))))
3165 SDValue X = N0->getOperand(0);
3166 EVT XVT = X.getValueType();
3168 // Validate constants ...
3170 APInt I1 = C1->getAPIntValue();
3172 ISD::CondCode NewCond;
3173 if (Cond == ISD::CondCode::SETULT) {
3174 NewCond = ISD::CondCode::SETEQ;
3175 } else if (Cond == ISD::CondCode::SETULE) {
3176 NewCond = ISD::CondCode::SETEQ;
3177 // But need to 'canonicalize' the constant.
3179 } else if (Cond == ISD::CondCode::SETUGT) {
3180 NewCond = ISD::CondCode::SETNE;
3181 // But need to 'canonicalize' the constant.
3183 } else if (Cond == ISD::CondCode::SETUGE) {
3184 NewCond = ISD::CondCode::SETNE;
3188 APInt I01 = C01->getAPIntValue();
3190 auto checkConstants = [&I1, &I01]() -> bool {
3191 // Both of them must be power-of-two, and the constant from setcc is bigger.
3192 return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2();
3195 if (checkConstants()) {
3196 // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256
3198 // What if we invert constants? (and the target predicate)
3201 assert(XVT.isInteger());
3202 NewCond = getSetCCInverse(NewCond, XVT);
3203 if (!checkConstants())
3205 // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256
3208 // They are power-of-two, so which bit is set?
3209 const unsigned KeptBits = I1.logBase2();
3210 const unsigned KeptBitsMinusOne = I01.logBase2();
3213 if (KeptBits != (KeptBitsMinusOne + 1))
3215 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable");
3217 // We don't want to do this in every single case.
3218 SelectionDAG &DAG = DCI.DAG;
3219 if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck(
3223 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits;
3224 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable");
3226 // Unfold into: ((%x << C) a>> C) cond %x
3227 // Where 'cond' will be either 'eq' or 'ne'.
3228 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT);
3229 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
3230 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
3231 SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond);
3236 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
3237 SDValue TargetLowering::optimizeSetCCByHoistingAndByConstFromLogicalShift(
3238 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
3239 DAGCombinerInfo &DCI, const SDLoc &DL) const {
3240 assert(isConstOrConstSplat(N1C) &&
3241 isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() &&
3242 "Should be a comparison with 0.");
3243 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3244 "Valid only for [in]equality comparisons.");
3246 unsigned NewShiftOpcode;
3249 SelectionDAG &DAG = DCI.DAG;
3250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3252 // Look for '(C l>>/<< Y)'.
3253 auto Match = [&NewShiftOpcode, &X, &C, &Y, &TLI, &DAG](SDValue V) {
3254 // The shift should be one-use.
3257 unsigned OldShiftOpcode = V.getOpcode();
3258 switch (OldShiftOpcode) {
3260 NewShiftOpcode = ISD::SRL;
3263 NewShiftOpcode = ISD::SHL;
3266 return false; // must be a logical shift.
3268 // We should be shifting a constant.
3269 // FIXME: best to use isConstantOrConstantVector().
3270 C = V.getOperand(0);
3271 ConstantSDNode *CC =
3272 isConstOrConstSplat(C, /*AllowUndefs=*/true, /*AllowTruncation=*/true);
3275 Y = V.getOperand(1);
3277 ConstantSDNode *XC =
3278 isConstOrConstSplat(X, /*AllowUndefs=*/true, /*AllowTruncation=*/true);
3279 return TLI.shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
3280 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG);
3283 // LHS of comparison should be an one-use 'and'.
3284 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
3287 X = N0.getOperand(0);
3288 SDValue Mask = N0.getOperand(1);
3290 // 'and' is commutative!
3297 EVT VT = X.getValueType();
3300 // ((X 'OppositeShiftOpcode' Y) & C) Cond 0
3301 SDValue T0 = DAG.getNode(NewShiftOpcode, DL, VT, X, Y);
3302 SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C);
3303 SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, N1C, Cond);
3307 /// Try to fold an equality comparison with a {add/sub/xor} binary operation as
3308 /// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to
3309 /// handle the commuted versions of these patterns.
3310 SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
3311 ISD::CondCode Cond, const SDLoc &DL,
3312 DAGCombinerInfo &DCI) const {
3313 unsigned BOpcode = N0.getOpcode();
3314 assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&
3315 "Unexpected binop");
3316 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode");
3318 // (X + Y) == X --> Y == 0
3319 // (X - Y) == X --> Y == 0
3320 // (X ^ Y) == X --> Y == 0
3321 SelectionDAG &DAG = DCI.DAG;
3322 EVT OpVT = N0.getValueType();
3323 SDValue X = N0.getOperand(0);
3324 SDValue Y = N0.getOperand(1);
3326 return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond);
3331 // (X + Y) == Y --> X == 0
3332 // (X ^ Y) == Y --> X == 0
3333 if (BOpcode == ISD::ADD || BOpcode == ISD::XOR)
3334 return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond);
3336 // The shift would not be valid if the operands are boolean (i1).
3337 if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1)
3340 // (X - Y) == Y --> X == Y << 1
3341 EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
3342 !DCI.isBeforeLegalize());
3343 SDValue One = DAG.getConstant(1, DL, ShiftVT);
3344 SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
3345 if (!DCI.isCalledByLegalizer())
3346 DCI.AddToWorklist(YShl1.getNode());
3347 return DAG.getSetCC(DL, VT, X, YShl1, Cond);
3350 /// Try to simplify a setcc built with the specified operands and cc. If it is
3351 /// unable to simplify it, return a null SDValue.
3352 SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
3353 ISD::CondCode Cond, bool foldBooleans,
3354 DAGCombinerInfo &DCI,
3355 const SDLoc &dl) const {
3356 SelectionDAG &DAG = DCI.DAG;
3357 const DataLayout &Layout = DAG.getDataLayout();
3358 EVT OpVT = N0.getValueType();
3360 // Constant fold or commute setcc.
3361 if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
3364 // Ensure that the constant occurs on the RHS and fold constant comparisons.
3365 // TODO: Handle non-splat vector constants. All undef causes trouble.
3366 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
3367 if (isConstOrConstSplat(N0) &&
3368 (DCI.isBeforeLegalizeOps() ||
3369 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
3370 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
3372 // If we have a subtract with the same 2 non-constant operands as this setcc
3373 // -- but in reverse order -- then try to commute the operands of this setcc
3374 // to match. A matching pair of setcc (cmp) and sub may be combined into 1
3375 // instruction on some targets.
3376 if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
3377 (DCI.isBeforeLegalizeOps() ||
3378 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
3379 DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
3380 !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } ))
3381 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
3383 if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
3384 const APInt &C1 = N1C->getAPIntValue();
3386 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3387 // equality comparison, then we're just comparing whether X itself is
3389 if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
3390 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3391 N0.getOperand(1).getOpcode() == ISD::Constant) {
3392 const APInt &ShAmt = N0.getConstantOperandAPInt(1);
3393 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3394 ShAmt == Log2_32(N0.getValueSizeInBits())) {
3395 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3396 // (srl (ctlz x), 5) == 0 -> X != 0
3397 // (srl (ctlz x), 5) != 1 -> X != 0
3400 // (srl (ctlz x), 5) != 0 -> X == 0
3401 // (srl (ctlz x), 5) == 1 -> X == 0
3404 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
3405 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
3411 // Look through truncs that don't change the value of a ctpop.
3412 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
3413 CTPOP = N0.getOperand(0);
3415 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
3417 N0.getValueSizeInBits() > Log2_32_Ceil(CTPOP.getValueSizeInBits()))) {
3418 EVT CTVT = CTPOP.getValueType();
3419 SDValue CTOp = CTPOP.getOperand(0);
3421 // (ctpop x) u< 2 -> (x & x-1) == 0
3422 // (ctpop x) u> 1 -> (x & x-1) != 0
3423 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
3424 SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
3425 SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
3426 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
3427 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
3428 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
3431 // If ctpop is not supported, expand a power-of-2 comparison based on it.
3432 if (C1 == 1 && !isOperationLegalOrCustom(ISD::CTPOP, CTVT) &&
3433 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3434 // (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0)
3435 // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
3436 SDValue Zero = DAG.getConstant(0, dl, CTVT);
3437 SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
3438 assert(CTVT.isInteger());
3439 ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT);
3440 SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
3441 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
3442 SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond);
3443 SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond);
3444 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
3445 return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS);
3449 // (zext x) == C --> x == (trunc C)
3450 // (sext x) == C --> x == (trunc C)
3451 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3452 DCI.isBeforeLegalize() && N0->hasOneUse()) {
3453 unsigned MinBits = N0.getValueSizeInBits();
3455 bool Signed = false;
3456 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
3458 MinBits = N0->getOperand(0).getValueSizeInBits();
3459 PreExt = N0->getOperand(0);
3460 } else if (N0->getOpcode() == ISD::AND) {
3461 // DAGCombine turns costly ZExts into ANDs
3462 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
3463 if ((C->getAPIntValue()+1).isPowerOf2()) {
3464 MinBits = C->getAPIntValue().countTrailingOnes();
3465 PreExt = N0->getOperand(0);
3467 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
3469 MinBits = N0->getOperand(0).getValueSizeInBits();
3470 PreExt = N0->getOperand(0);
3472 } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
3473 // ZEXTLOAD / SEXTLOAD
3474 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
3475 MinBits = LN0->getMemoryVT().getSizeInBits();
3477 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
3479 MinBits = LN0->getMemoryVT().getSizeInBits();
3484 // Figure out how many bits we need to preserve this constant.
3485 unsigned ReqdBits = Signed ?
3486 C1.getBitWidth() - C1.getNumSignBits() + 1 :
3489 // Make sure we're not losing bits from the constant.
3491 MinBits < C1.getBitWidth() &&
3492 MinBits >= ReqdBits) {
3493 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
3494 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
3495 // Will get folded away.
3496 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
3497 if (MinBits == 1 && C1 == 1)
3498 // Invert the condition.
3499 return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
3500 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3501 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
3502 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
3505 // If truncating the setcc operands is not desirable, we can still
3506 // simplify the expression in some cases:
3507 // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc)
3508 // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc))
3509 // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc))
3510 // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc)
3511 // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc))
3512 // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc)
3513 SDValue TopSetCC = N0->getOperand(0);
3514 unsigned N0Opc = N0->getOpcode();
3515 bool SExt = (N0Opc == ISD::SIGN_EXTEND);
3516 if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 &&
3517 TopSetCC.getOpcode() == ISD::SETCC &&
3518 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
3519 (isConstFalseVal(N1C) ||
3520 isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
3522 bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) ||
3523 (!N1C->isNullValue() && Cond == ISD::SETNE);
3528 ISD::CondCode InvCond = ISD::getSetCCInverse(
3529 cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(),
3530 TopSetCC.getOperand(0).getValueType());
3531 return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0),
3532 TopSetCC.getOperand(1),
3538 // If the LHS is '(and load, const)', the RHS is 0, the test is for
3539 // equality or unsigned, and all 1 bits of the const are in the same
3540 // partial word, see if we can shorten the load.
3541 if (DCI.isBeforeLegalize() &&
3542 !ISD::isSignedIntSetCC(Cond) &&
3543 N0.getOpcode() == ISD::AND && C1 == 0 &&
3544 N0.getNode()->hasOneUse() &&
3545 isa<LoadSDNode>(N0.getOperand(0)) &&
3546 N0.getOperand(0).getNode()->hasOneUse() &&
3547 isa<ConstantSDNode>(N0.getOperand(1))) {
3548 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
3550 unsigned bestWidth = 0, bestOffset = 0;
3551 if (Lod->isSimple() && Lod->isUnindexed()) {
3552 unsigned origWidth = N0.getValueSizeInBits();
3553 unsigned maskWidth = origWidth;
3554 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
3555 // 8 bits, but have to be careful...
3556 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
3557 origWidth = Lod->getMemoryVT().getSizeInBits();
3558 const APInt &Mask = N0.getConstantOperandAPInt(1);
3559 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
3560 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
3561 for (unsigned offset=0; offset<origWidth/width; offset++) {
3562 if (Mask.isSubsetOf(newMask)) {
3563 if (Layout.isLittleEndian())
3564 bestOffset = (uint64_t)offset * (width/8);
3566 bestOffset = (origWidth/width - offset - 1) * (width/8);
3567 bestMask = Mask.lshr(offset * (width/8) * 8);
3576 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
3577 if (newVT.isRound() &&
3578 shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
3579 SDValue Ptr = Lod->getBasePtr();
3580 if (bestOffset != 0)
3581 Ptr = DAG.getMemBasePlusOffset(Ptr, bestOffset, dl);
3582 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
3583 SDValue NewLoad = DAG.getLoad(
3584 newVT, dl, Lod->getChain(), Ptr,
3585 Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign);
3586 return DAG.getSetCC(dl, VT,
3587 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
3588 DAG.getConstant(bestMask.trunc(bestWidth),
3590 DAG.getConstant(0LL, dl, newVT), Cond);
3595 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3596 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3597 unsigned InSize = N0.getOperand(0).getValueSizeInBits();
3599 // If the comparison constant has bits in the upper part, the
3600 // zero-extended value could never match.
3601 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
3602 C1.getBitWidth() - InSize))) {
3607 return DAG.getConstant(0, dl, VT);
3611 return DAG.getConstant(1, dl, VT);
3614 // True if the sign bit of C1 is set.
3615 return DAG.getConstant(C1.isNegative(), dl, VT);
3618 // True if the sign bit of C1 isn't set.
3619 return DAG.getConstant(C1.isNonNegative(), dl, VT);
3625 // Otherwise, we can perform the comparison with the low bits.
3633 EVT newVT = N0.getOperand(0).getValueType();
3634 if (DCI.isBeforeLegalizeOps() ||
3635 (isOperationLegal(ISD::SETCC, newVT) &&
3636 isCondCodeLegal(Cond, newVT.getSimpleVT()))) {
3637 EVT NewSetCCVT = getSetCCResultType(Layout, *DAG.getContext(), newVT);
3638 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
3640 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
3642 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
3647 break; // todo, be more careful with signed comparisons
3649 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3650 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3651 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3652 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
3653 EVT ExtDstTy = N0.getValueType();
3654 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
3656 // If the constant doesn't fit into the number of bits for the source of
3657 // the sign extension, it is impossible for both sides to be equal.
3658 if (C1.getMinSignedBits() > ExtSrcTyBits)
3659 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
3662 EVT Op0Ty = N0.getOperand(0).getValueType();
3663 if (Op0Ty == ExtSrcTy) {
3664 ZextOp = N0.getOperand(0);
3666 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
3667 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
3668 DAG.getConstant(Imm, dl, Op0Ty));
3670 if (!DCI.isCalledByLegalizer())
3671 DCI.AddToWorklist(ZextOp.getNode());
3672 // Otherwise, make this a use of a zext.
3673 return DAG.getSetCC(dl, VT, ZextOp,
3674 DAG.getConstant(C1 & APInt::getLowBitsSet(
3679 } else if ((N1C->isNullValue() || N1C->isOne()) &&
3680 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3681 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3682 if (N0.getOpcode() == ISD::SETCC &&
3683 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) &&
3684 (N0.getValueType() == MVT::i1 ||
3685 getBooleanContents(N0.getOperand(0).getValueType()) ==
3686 ZeroOrOneBooleanContent)) {
3687 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne());
3689 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
3690 // Invert the condition.
3691 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3692 CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType());
3693 if (DCI.isBeforeLegalizeOps() ||
3694 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
3695 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
3698 if ((N0.getOpcode() == ISD::XOR ||
3699 (N0.getOpcode() == ISD::AND &&
3700 N0.getOperand(0).getOpcode() == ISD::XOR &&
3701 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3702 isa<ConstantSDNode>(N0.getOperand(1)) &&
3703 cast<ConstantSDNode>(N0.getOperand(1))->isOne()) {
3704 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
3705 // can only do this if the top bits are known zero.
3706 unsigned BitWidth = N0.getValueSizeInBits();
3707 if (DAG.MaskedValueIsZero(N0,
3708 APInt::getHighBitsSet(BitWidth,
3710 // Okay, get the un-inverted input value.
3712 if (N0.getOpcode() == ISD::XOR) {
3713 Val = N0.getOperand(0);
3715 assert(N0.getOpcode() == ISD::AND &&
3716 N0.getOperand(0).getOpcode() == ISD::XOR);
3717 // ((X^1)&1)^1 -> X & 1
3718 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
3719 N0.getOperand(0).getOperand(0),
3723 return DAG.getSetCC(dl, VT, Val, N1,
3724 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3726 } else if (N1C->isOne()) {
3728 if (Op0.getOpcode() == ISD::TRUNCATE)
3729 Op0 = Op0.getOperand(0);
3731 if ((Op0.getOpcode() == ISD::XOR) &&
3732 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
3733 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
3734 SDValue XorLHS = Op0.getOperand(0);
3735 SDValue XorRHS = Op0.getOperand(1);
3736 // Ensure that the input setccs return an i1 type or 0/1 value.
3737 if (Op0.getValueType() == MVT::i1 ||
3738 (getBooleanContents(XorLHS.getOperand(0).getValueType()) ==
3739 ZeroOrOneBooleanContent &&
3740 getBooleanContents(XorRHS.getOperand(0).getValueType()) ==
3741 ZeroOrOneBooleanContent)) {
3742 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
3743 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
3744 return DAG.getSetCC(dl, VT, XorLHS, XorRHS, Cond);
3747 if (Op0.getOpcode() == ISD::AND &&
3748 isa<ConstantSDNode>(Op0.getOperand(1)) &&
3749 cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) {
3750 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
3751 if (Op0.getValueType().bitsGT(VT))
3752 Op0 = DAG.getNode(ISD::AND, dl, VT,
3753 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
3754 DAG.getConstant(1, dl, VT));
3755 else if (Op0.getValueType().bitsLT(VT))
3756 Op0 = DAG.getNode(ISD::AND, dl, VT,
3757 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
3758 DAG.getConstant(1, dl, VT));
3760 return DAG.getSetCC(dl, VT, Op0,
3761 DAG.getConstant(0, dl, Op0.getValueType()),
3762 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3764 if (Op0.getOpcode() == ISD::AssertZext &&
3765 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
3766 return DAG.getSetCC(dl, VT, Op0,
3767 DAG.getConstant(0, dl, Op0.getValueType()),
3768 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3773 // icmp eq/ne (urem %x, %y), 0
3774 // Iff %x has 0 or 1 bits set, and %y has at least 2 bits set, omit 'urem':
3776 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
3777 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3778 KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0));
3779 KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1));
3780 if (XKnown.countMaxPopulation() == 1 && YKnown.countMinPopulation() >= 2)
3781 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
3785 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
3789 // These simplifications apply to splat vectors as well.
3790 // TODO: Handle more splat vector cases.
3791 if (auto *N1C = isConstOrConstSplat(N1)) {
3792 const APInt &C1 = N1C->getAPIntValue();
3794 APInt MinVal, MaxVal;
3795 unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits();
3796 if (ISD::isSignedIntSetCC(Cond)) {
3797 MinVal = APInt::getSignedMinValue(OperandBitSize);
3798 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
3800 MinVal = APInt::getMinValue(OperandBitSize);
3801 MaxVal = APInt::getMaxValue(OperandBitSize);
3804 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3805 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3806 // X >= MIN --> true
3808 return DAG.getBoolConstant(true, dl, VT, OpVT);
3810 if (!VT.isVector()) { // TODO: Support this for vectors.
3811 // X >= C0 --> X > (C0 - 1)
3813 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
3814 if ((DCI.isBeforeLegalizeOps() ||
3815 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3816 (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
3817 isLegalICmpImmediate(C.getSExtValue())))) {
3818 return DAG.getSetCC(dl, VT, N0,
3819 DAG.getConstant(C, dl, N1.getValueType()),
3825 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3826 // X <= MAX --> true
3828 return DAG.getBoolConstant(true, dl, VT, OpVT);
3830 // X <= C0 --> X < (C0 + 1)
3831 if (!VT.isVector()) { // TODO: Support this for vectors.
3833 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
3834 if ((DCI.isBeforeLegalizeOps() ||
3835 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3836 (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
3837 isLegalICmpImmediate(C.getSExtValue())))) {
3838 return DAG.getSetCC(dl, VT, N0,
3839 DAG.getConstant(C, dl, N1.getValueType()),
3845 if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
3847 return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false
3849 // TODO: Support this for vectors after legalize ops.
3850 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3851 // Canonicalize setlt X, Max --> setne X, Max
3853 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3855 // If we have setult X, 1, turn it into seteq X, 0
3857 return DAG.getSetCC(dl, VT, N0,
3858 DAG.getConstant(MinVal, dl, N0.getValueType()),
3863 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) {
3865 return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false
3867 // TODO: Support this for vectors after legalize ops.
3868 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3869 // Canonicalize setgt X, Min --> setne X, Min
3871 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3873 // If we have setugt X, Max-1, turn it into seteq X, Max
3875 return DAG.getSetCC(dl, VT, N0,
3876 DAG.getConstant(MaxVal, dl, N0.getValueType()),
3881 if (Cond == ISD::SETEQ || Cond == ISD::SETNE) {
3882 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
3883 if (C1.isNullValue())
3884 if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift(
3885 VT, N0, N1, Cond, DCI, dl))
3889 // If we have "setcc X, C0", check to see if we can shrink the immediate
3891 // TODO: Support this for vectors after legalize ops.
3892 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3893 // SETUGT X, SINTMAX -> SETLT X, 0
3894 if (Cond == ISD::SETUGT &&
3895 C1 == APInt::getSignedMaxValue(OperandBitSize))
3896 return DAG.getSetCC(dl, VT, N0,
3897 DAG.getConstant(0, dl, N1.getValueType()),
3900 // SETULT X, SINTMIN -> SETGT X, -1
3901 if (Cond == ISD::SETULT &&
3902 C1 == APInt::getSignedMinValue(OperandBitSize)) {
3903 SDValue ConstMinusOne =
3904 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
3906 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
3911 // Back to non-vector simplifications.
3912 // TODO: Can we do these for vector splats?
3913 if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
3914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3915 const APInt &C1 = N1C->getAPIntValue();
3916 EVT ShValTy = N0.getValueType();
3918 // Fold bit comparisons when we can.
3919 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3920 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) &&
3921 N0.getOpcode() == ISD::AND) {
3922 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3924 getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
3925 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3926 // Perform the xform if the AND RHS is a single bit.
3927 unsigned ShCt = AndRHS->getAPIntValue().logBase2();
3928 if (AndRHS->getAPIntValue().isPowerOf2() &&
3929 !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
3930 return DAG.getNode(ISD::TRUNCATE, dl, VT,
3931 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
3932 DAG.getConstant(ShCt, dl, ShiftTy)));
3934 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
3935 // (X & 8) == 8 --> (X & 8) >> 3
3936 // Perform the xform if C1 is a single bit.
3937 unsigned ShCt = C1.logBase2();
3938 if (C1.isPowerOf2() &&
3939 !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
3940 return DAG.getNode(ISD::TRUNCATE, dl, VT,
3941 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
3942 DAG.getConstant(ShCt, dl, ShiftTy)));
3948 if (C1.getMinSignedBits() <= 64 &&
3949 !isLegalICmpImmediate(C1.getSExtValue())) {
3950 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
3951 // (X & -256) == 256 -> (X >> 8) == 1
3952 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3953 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3954 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3955 const APInt &AndRHSC = AndRHS->getAPIntValue();
3956 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
3957 unsigned ShiftBits = AndRHSC.countTrailingZeros();
3958 if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
3960 DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
3961 DAG.getConstant(ShiftBits, dl, ShiftTy));
3962 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
3963 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
3967 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
3968 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
3969 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
3970 // X < 0x100000000 -> (X >> 32) < 1
3971 // X >= 0x100000000 -> (X >> 32) >= 1
3972 // X <= 0x0ffffffff -> (X >> 32) < 1
3973 // X > 0x0ffffffff -> (X >> 32) >= 1
3976 ISD::CondCode NewCond = Cond;
3978 ShiftBits = C1.countTrailingOnes();
3980 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3982 ShiftBits = C1.countTrailingZeros();
3984 NewC.lshrInPlace(ShiftBits);
3985 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
3986 isLegalICmpImmediate(NewC.getSExtValue()) &&
3987 !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
3988 SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0,
3989 DAG.getConstant(ShiftBits, dl, ShiftTy));
3990 SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);
3991 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
3997 if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) {
3998 auto *CFP = cast<ConstantFPSDNode>(N1);
3999 assert(!CFP->getValueAPF().isNaN() && "Unexpected NaN value");
4001 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
4002 // constant if knowing that the operand is non-nan is enough. We prefer to
4003 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
4005 if (Cond == ISD::SETO || Cond == ISD::SETUO)
4006 return DAG.getSetCC(dl, VT, N0, N0, Cond);
4008 // setcc (fneg x), C -> setcc swap(pred) x, -C
4009 if (N0.getOpcode() == ISD::FNEG) {
4010 ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
4011 if (DCI.isBeforeLegalizeOps() ||
4012 isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
4013 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
4014 return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
4018 // If the condition is not legal, see if we can find an equivalent one
4020 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
4021 // If the comparison was an awkward floating-point == or != and one of
4022 // the comparison operands is infinity or negative infinity, convert the
4023 // condition to a less-awkward <= or >=.
4024 if (CFP->getValueAPF().isInfinity()) {
4025 bool IsNegInf = CFP->getValueAPF().isNegative();
4026 ISD::CondCode NewCond = ISD::SETCC_INVALID;
4028 case ISD::SETOEQ: NewCond = IsNegInf ? ISD::SETOLE : ISD::SETOGE; break;
4029 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break;
4030 case ISD::SETUNE: NewCond = IsNegInf ? ISD::SETUGT : ISD::SETULT; break;
4031 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break;
4034 if (NewCond != ISD::SETCC_INVALID &&
4035 isCondCodeLegal(NewCond, N0.getSimpleValueType()))
4036 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
4042 // The sext(setcc()) => setcc() optimization relies on the appropriate
4043 // constant being emitted.
4044 assert(!N0.getValueType().isInteger() &&
4045 "Integer types should be handled by FoldSetCC");
4047 bool EqTrue = ISD::isTrueWhenEqual(Cond);
4048 unsigned UOF = ISD::getUnorderedFlavor(Cond);
4049 if (UOF == 2) // FP operators that are undefined on NaNs.
4050 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
4051 if (UOF == unsigned(EqTrue))
4052 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
4053 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
4054 // if it is not already.
4055 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
4056 if (NewCond != Cond &&
4057 (DCI.isBeforeLegalizeOps() ||
4058 isCondCodeLegal(NewCond, N0.getSimpleValueType())))
4059 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
4062 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
4063 N0.getValueType().isInteger()) {
4064 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
4065 N0.getOpcode() == ISD::XOR) {
4066 // Simplify (X+Y) == (X+Z) --> Y == Z
4067 if (N0.getOpcode() == N1.getOpcode()) {
4068 if (N0.getOperand(0) == N1.getOperand(0))
4069 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
4070 if (N0.getOperand(1) == N1.getOperand(1))
4071 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
4072 if (isCommutativeBinOp(N0.getOpcode())) {
4073 // If X op Y == Y op X, try other combinations.
4074 if (N0.getOperand(0) == N1.getOperand(1))
4075 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
4077 if (N0.getOperand(1) == N1.getOperand(0))
4078 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
4083 // If RHS is a legal immediate value for a compare instruction, we need
4084 // to be careful about increasing register pressure needlessly.
4085 bool LegalRHSImm = false;
4087 if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
4088 if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4089 // Turn (X+C1) == C2 --> X == C2-C1
4090 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
4091 return DAG.getSetCC(dl, VT, N0.getOperand(0),
4092 DAG.getConstant(RHSC->getAPIntValue()-
4093 LHSR->getAPIntValue(),
4094 dl, N0.getValueType()), Cond);
4097 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
4098 if (N0.getOpcode() == ISD::XOR)
4099 // If we know that all of the inverted bits are zero, don't bother
4100 // performing the inversion.
4101 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
4103 DAG.getSetCC(dl, VT, N0.getOperand(0),
4104 DAG.getConstant(LHSR->getAPIntValue() ^
4105 RHSC->getAPIntValue(),
4106 dl, N0.getValueType()),
4110 // Turn (C1-X) == C2 --> X == C1-C2
4111 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
4112 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
4114 DAG.getSetCC(dl, VT, N0.getOperand(1),
4115 DAG.getConstant(SUBC->getAPIntValue() -
4116 RHSC->getAPIntValue(),
4117 dl, N0.getValueType()),
4122 // Could RHSC fold directly into a compare?
4123 if (RHSC->getValueType(0).getSizeInBits() <= 64)
4124 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
4127 // (X+Y) == X --> Y == 0 and similar folds.
4128 // Don't do this if X is an immediate that can fold into a cmp
4129 // instruction and X+Y has other uses. It could be an induction variable
4130 // chain, and the transform would increase register pressure.
4131 if (!LegalRHSImm || N0.hasOneUse())
4132 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI))
4136 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
4137 N1.getOpcode() == ISD::XOR)
4138 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI))
4141 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI))
4145 // Fold remainder of division by a constant.
4146 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
4147 N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
4148 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4150 // When division is cheap or optimizing for minimum size,
4151 // fall through to DIVREM creation by skipping this fold.
4152 if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize)) {
4153 if (N0.getOpcode() == ISD::UREM) {
4154 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
4156 } else if (N0.getOpcode() == ISD::SREM) {
4157 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl))
4163 // Fold away ALL boolean setcc's.
4164 if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
4167 default: llvm_unreachable("Unknown integer setcc!");
4168 case ISD::SETEQ: // X == Y -> ~(X^Y)
4169 Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
4170 N0 = DAG.getNOT(dl, Temp, OpVT);
4171 if (!DCI.isCalledByLegalizer())
4172 DCI.AddToWorklist(Temp.getNode());
4174 case ISD::SETNE: // X != Y --> (X^Y)
4175 N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
4177 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
4178 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
4179 Temp = DAG.getNOT(dl, N0, OpVT);
4180 N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
4181 if (!DCI.isCalledByLegalizer())
4182 DCI.AddToWorklist(Temp.getNode());
4184 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
4185 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
4186 Temp = DAG.getNOT(dl, N1, OpVT);
4187 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
4188 if (!DCI.isCalledByLegalizer())
4189 DCI.AddToWorklist(Temp.getNode());
4191 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
4192 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
4193 Temp = DAG.getNOT(dl, N0, OpVT);
4194 N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
4195 if (!DCI.isCalledByLegalizer())
4196 DCI.AddToWorklist(Temp.getNode());
4198 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
4199 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
4200 Temp = DAG.getNOT(dl, N1, OpVT);
4201 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
4204 if (VT.getScalarType() != MVT::i1) {
4205 if (!DCI.isCalledByLegalizer())
4206 DCI.AddToWorklist(N0.getNode());
4207 // FIXME: If running after legalize, we probably can't do this.
4208 ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT));
4209 N0 = DAG.getNode(ExtendCode, dl, VT, N0);
4214 // Could not fold it.
4218 /// Returns true (and the GlobalValue and the offset) if the node is a
4219 /// GlobalAddress + offset.
4220 bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA,
4221 int64_t &Offset) const {
4223 SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode();
4225 if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) {
4226 GA = GASD->getGlobal();
4227 Offset += GASD->getOffset();
4231 if (N->getOpcode() == ISD::ADD) {
4232 SDValue N1 = N->getOperand(0);
4233 SDValue N2 = N->getOperand(1);
4234 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
4235 if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
4236 Offset += V->getSExtValue();
4239 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
4240 if (auto *V = dyn_cast<ConstantSDNode>(N1)) {
4241 Offset += V->getSExtValue();
4250 SDValue TargetLowering::PerformDAGCombine(SDNode *N,
4251 DAGCombinerInfo &DCI) const {
4252 // Default implementation: no optimization.
4256 //===----------------------------------------------------------------------===//
4257 // Inline Assembler Implementation Methods
4258 //===----------------------------------------------------------------------===//
4260 TargetLowering::ConstraintType
4261 TargetLowering::getConstraintType(StringRef Constraint) const {
4262 unsigned S = Constraint.size();
4265 switch (Constraint[0]) {
4268 return C_RegisterClass;
4270 case 'o': // offsetable
4271 case 'V': // not offsetable
4273 case 'n': // Simple Integer
4274 case 'E': // Floating Point Constant
4275 case 'F': // Floating Point Constant
4277 case 'i': // Simple Integer or Relocatable Constant
4278 case 's': // Relocatable Constant
4279 case 'p': // Address.
4280 case 'X': // Allow ANY value.
4281 case 'I': // Target registers.
4295 if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') {
4296 if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
4303 /// Try to replace an X constraint, which matches anything, with another that
4304 /// has more specific requirements based on the type of the corresponding
4306 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
4307 if (ConstraintVT.isInteger())
4309 if (ConstraintVT.isFloatingPoint())
4310 return "f"; // works for many targets
4314 SDValue TargetLowering::LowerAsmOutputForConstraint(
4315 SDValue &Chain, SDValue &Flag, SDLoc DL, const AsmOperandInfo &OpInfo,
4316 SelectionDAG &DAG) const {
4320 /// Lower the specified operand into the Ops vector.
4321 /// If it is invalid, don't add anything to Ops.
4322 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4323 std::string &Constraint,
4324 std::vector<SDValue> &Ops,
4325 SelectionDAG &DAG) const {
4327 if (Constraint.length() > 1) return;
4329 char ConstraintLetter = Constraint[0];
4330 switch (ConstraintLetter) {
4332 case 'X': // Allows any operand; labels (basic block) use this.
4333 if (Op.getOpcode() == ISD::BasicBlock ||
4334 Op.getOpcode() == ISD::TargetBlockAddress) {
4339 case 'i': // Simple Integer or Relocatable Constant
4340 case 'n': // Simple Integer
4341 case 's': { // Relocatable Constant
4343 GlobalAddressSDNode *GA;
4345 BlockAddressSDNode *BA;
4346 uint64_t Offset = 0;
4348 // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C),
4349 // etc., since getelementpointer is variadic. We can't use
4350 // SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible
4351 // while in this case the GA may be furthest from the root node which is
4352 // likely an ISD::ADD.
4354 if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') {
4355 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
4356 GA->getValueType(0),
4357 Offset + GA->getOffset()));
4359 } else if ((C = dyn_cast<ConstantSDNode>(Op)) &&
4360 ConstraintLetter != 's') {
4361 // gcc prints these as sign extended. Sign extend value to 64 bits
4362 // now; without this it would get ZExt'd later in
4363 // ScheduleDAGSDNodes::EmitNode, which is very generic.
4364 bool IsBool = C->getConstantIntValue()->getBitWidth() == 1;
4365 BooleanContent BCont = getBooleanContents(MVT::i64);
4366 ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont)
4368 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue()
4369 : C->getSExtValue();
4370 Ops.push_back(DAG.getTargetConstant(Offset + ExtVal,
4371 SDLoc(C), MVT::i64));
4373 } else if ((BA = dyn_cast<BlockAddressSDNode>(Op)) &&
4374 ConstraintLetter != 'n') {
4375 Ops.push_back(DAG.getTargetBlockAddress(
4376 BA->getBlockAddress(), BA->getValueType(0),
4377 Offset + BA->getOffset(), BA->getTargetFlags()));
4380 const unsigned OpCode = Op.getOpcode();
4381 if (OpCode == ISD::ADD || OpCode == ISD::SUB) {
4382 if ((C = dyn_cast<ConstantSDNode>(Op.getOperand(0))))
4383 Op = Op.getOperand(1);
4384 // Subtraction is not commutative.
4385 else if (OpCode == ISD::ADD &&
4386 (C = dyn_cast<ConstantSDNode>(Op.getOperand(1))))
4387 Op = Op.getOperand(0);
4390 Offset += (OpCode == ISD::ADD ? 1 : -1) * C->getSExtValue();
4401 std::pair<unsigned, const TargetRegisterClass *>
4402 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
4403 StringRef Constraint,
4405 if (Constraint.empty() || Constraint[0] != '{')
4406 return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr));
4407 assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?");
4409 // Remove the braces from around the name.
4410 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
4412 std::pair<unsigned, const TargetRegisterClass *> R =
4413 std::make_pair(0u, static_cast<const TargetRegisterClass *>(nullptr));
4415 // Figure out which register class contains this reg.
4416 for (const TargetRegisterClass *RC : RI->regclasses()) {
4417 // If none of the value types for this register class are valid, we
4418 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4419 if (!isLegalRC(*RI, *RC))
4422 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
4424 if (RegName.equals_lower(RI->getRegAsmName(*I))) {
4425 std::pair<unsigned, const TargetRegisterClass *> S =
4426 std::make_pair(*I, RC);
4428 // If this register class has the requested value type, return it,
4429 // otherwise keep searching and return the first class found
4430 // if no other is found which explicitly has the requested type.
4431 if (RI->isTypeLegalForClass(*RC, VT))
4442 //===----------------------------------------------------------------------===//
4443 // Constraint Selection.
4445 /// Return true of this is an input operand that is a matching constraint like
4447 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
4448 assert(!ConstraintCode.empty() && "No known constraint!");
4449 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
4452 /// If this is an input matching constraint, this method returns the output
4453 /// operand it matches.
4454 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
4455 assert(!ConstraintCode.empty() && "No known constraint!");
4456 return atoi(ConstraintCode.c_str());
4459 /// Split up the constraint string from the inline assembly value into the
4460 /// specific constraints and their prefixes, and also tie in the associated
4462 /// If this returns an empty vector, and if the constraint string itself
4463 /// isn't empty, there was an error parsing.
4464 TargetLowering::AsmOperandInfoVector
4465 TargetLowering::ParseConstraints(const DataLayout &DL,
4466 const TargetRegisterInfo *TRI,
4467 const CallBase &Call) const {
4468 /// Information about all of the constraints.
4469 AsmOperandInfoVector ConstraintOperands;
4470 const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand());
4471 unsigned maCount = 0; // Largest number of multiple alternative constraints.
4473 // Do a prepass over the constraints, canonicalizing them, and building up the
4474 // ConstraintOperands list.
4475 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4476 unsigned ResNo = 0; // ResNo - The result number of the next output.
4478 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
4479 ConstraintOperands.emplace_back(std::move(CI));
4480 AsmOperandInfo &OpInfo = ConstraintOperands.back();
4482 // Update multiple alternative constraint count.
4483 if (OpInfo.multipleAlternatives.size() > maCount)
4484 maCount = OpInfo.multipleAlternatives.size();
4486 OpInfo.ConstraintVT = MVT::Other;
4488 // Compute the value type for each operand.
4489 switch (OpInfo.Type) {
4490 case InlineAsm::isOutput:
4491 // Indirect outputs just consume an argument.
4492 if (OpInfo.isIndirect) {
4493 OpInfo.CallOperandVal = Call.getArgOperand(ArgNo++);
4497 // The return value of the call is this value. As such, there is no
4498 // corresponding argument.
4499 assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
4500 if (StructType *STy = dyn_cast<StructType>(Call.getType())) {
4501 OpInfo.ConstraintVT =
4502 getSimpleValueType(DL, STy->getElementType(ResNo));
4504 assert(ResNo == 0 && "Asm only has one result!");
4505 OpInfo.ConstraintVT = getSimpleValueType(DL, Call.getType());
4509 case InlineAsm::isInput:
4510 OpInfo.CallOperandVal = Call.getArgOperand(ArgNo++);
4512 case InlineAsm::isClobber:
4517 if (OpInfo.CallOperandVal) {
4518 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
4519 if (OpInfo.isIndirect) {
4520 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4522 report_fatal_error("Indirect operand for inline asm not a pointer!");
4523 OpTy = PtrTy->getElementType();
4526 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
4527 if (StructType *STy = dyn_cast<StructType>(OpTy))
4528 if (STy->getNumElements() == 1)
4529 OpTy = STy->getElementType(0);
4531 // If OpTy is not a single value, it may be a struct/union that we
4532 // can tile with integers.
4533 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4534 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
4543 OpInfo.ConstraintVT =
4544 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
4547 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
4548 unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
4549 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
4551 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
4556 // If we have multiple alternative constraints, select the best alternative.
4557 if (!ConstraintOperands.empty()) {
4559 unsigned bestMAIndex = 0;
4560 int bestWeight = -1;
4561 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
4564 // Compute the sums of the weights for each alternative, keeping track
4565 // of the best (highest weight) one so far.
4566 for (maIndex = 0; maIndex < maCount; ++maIndex) {
4568 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
4569 cIndex != eIndex; ++cIndex) {
4570 AsmOperandInfo &OpInfo = ConstraintOperands[cIndex];
4571 if (OpInfo.Type == InlineAsm::isClobber)
4574 // If this is an output operand with a matching input operand,
4575 // look up the matching input. If their types mismatch, e.g. one
4576 // is an integer, the other is floating point, or their sizes are
4577 // different, flag it as an maCantMatch.
4578 if (OpInfo.hasMatchingInput()) {
4579 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
4580 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
4581 if ((OpInfo.ConstraintVT.isInteger() !=
4582 Input.ConstraintVT.isInteger()) ||
4583 (OpInfo.ConstraintVT.getSizeInBits() !=
4584 Input.ConstraintVT.getSizeInBits())) {
4585 weightSum = -1; // Can't match.
4590 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
4595 weightSum += weight;
4598 if (weightSum > bestWeight) {
4599 bestWeight = weightSum;
4600 bestMAIndex = maIndex;
4604 // Now select chosen alternative in each constraint.
4605 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
4606 cIndex != eIndex; ++cIndex) {
4607 AsmOperandInfo &cInfo = ConstraintOperands[cIndex];
4608 if (cInfo.Type == InlineAsm::isClobber)
4610 cInfo.selectAlternative(bestMAIndex);
4615 // Check and hook up tied operands, choose constraint code to use.
4616 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
4617 cIndex != eIndex; ++cIndex) {
4618 AsmOperandInfo &OpInfo = ConstraintOperands[cIndex];
4620 // If this is an output operand with a matching input operand, look up the
4621 // matching input. If their types mismatch, e.g. one is an integer, the
4622 // other is floating point, or their sizes are different, flag it as an
4624 if (OpInfo.hasMatchingInput()) {
4625 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
4627 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
4628 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
4629 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
4630 OpInfo.ConstraintVT);
4631 std::pair<unsigned, const TargetRegisterClass *> InputRC =
4632 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
4633 Input.ConstraintVT);
4634 if ((OpInfo.ConstraintVT.isInteger() !=
4635 Input.ConstraintVT.isInteger()) ||
4636 (MatchRC.second != InputRC.second)) {
4637 report_fatal_error("Unsupported asm: input constraint"
4638 " with a matching output constraint of"
4639 " incompatible type!");
4645 return ConstraintOperands;
4648 /// Return an integer indicating how general CT is.
4649 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
4651 case TargetLowering::C_Immediate:
4652 case TargetLowering::C_Other:
4653 case TargetLowering::C_Unknown:
4655 case TargetLowering::C_Register:
4657 case TargetLowering::C_RegisterClass:
4659 case TargetLowering::C_Memory:
4662 llvm_unreachable("Invalid constraint type");
4665 /// Examine constraint type and operand type and determine a weight value.
4666 /// This object must already have been set up with the operand type
4667 /// and the current alternative constraint selected.
4668 TargetLowering::ConstraintWeight
4669 TargetLowering::getMultipleConstraintMatchWeight(
4670 AsmOperandInfo &info, int maIndex) const {
4671 InlineAsm::ConstraintCodeVector *rCodes;
4672 if (maIndex >= (int)info.multipleAlternatives.size())
4673 rCodes = &info.Codes;
4675 rCodes = &info.multipleAlternatives[maIndex].Codes;
4676 ConstraintWeight BestWeight = CW_Invalid;
4678 // Loop over the options, keeping track of the most general one.
4679 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
4680 ConstraintWeight weight =
4681 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
4682 if (weight > BestWeight)
4683 BestWeight = weight;
4689 /// Examine constraint type and operand type and determine a weight value.
4690 /// This object must already have been set up with the operand type
4691 /// and the current alternative constraint selected.
4692 TargetLowering::ConstraintWeight
4693 TargetLowering::getSingleConstraintMatchWeight(
4694 AsmOperandInfo &info, const char *constraint) const {
4695 ConstraintWeight weight = CW_Invalid;
4696 Value *CallOperandVal = info.CallOperandVal;
4697 // If we don't have a value, we can't do a match,
4698 // but allow it at the lowest weight.
4699 if (!CallOperandVal)
4701 // Look at the constraint type.
4702 switch (*constraint) {
4703 case 'i': // immediate integer.
4704 case 'n': // immediate integer with a known value.
4705 if (isa<ConstantInt>(CallOperandVal))
4706 weight = CW_Constant;
4708 case 's': // non-explicit intregal immediate.
4709 if (isa<GlobalValue>(CallOperandVal))
4710 weight = CW_Constant;
4712 case 'E': // immediate float if host format.
4713 case 'F': // immediate float.
4714 if (isa<ConstantFP>(CallOperandVal))
4715 weight = CW_Constant;
4717 case '<': // memory operand with autodecrement.
4718 case '>': // memory operand with autoincrement.
4719 case 'm': // memory operand.
4720 case 'o': // offsettable memory operand
4721 case 'V': // non-offsettable memory operand
4724 case 'r': // general register.
4725 case 'g': // general register, memory operand or immediate integer.
4726 // note: Clang converts "g" to "imr".
4727 if (CallOperandVal->getType()->isIntegerTy())
4728 weight = CW_Register;
4730 case 'X': // any operand.
4732 weight = CW_Default;
4738 /// If there are multiple different constraints that we could pick for this
4739 /// operand (e.g. "imr") try to pick the 'best' one.
4740 /// This is somewhat tricky: constraints fall into four classes:
4741 /// Other -> immediates and magic values
4742 /// Register -> one specific register
4743 /// RegisterClass -> a group of regs
4744 /// Memory -> memory
4745 /// Ideally, we would pick the most specific constraint possible: if we have
4746 /// something that fits into a register, we would pick it. The problem here
4747 /// is that if we have something that could either be in a register or in
4748 /// memory that use of the register could cause selection of *other*
4749 /// operands to fail: they might only succeed if we pick memory. Because of
4750 /// this the heuristic we use is:
4752 /// 1) If there is an 'other' constraint, and if the operand is valid for
4753 /// that constraint, use it. This makes us take advantage of 'i'
4754 /// constraints when available.
4755 /// 2) Otherwise, pick the most general constraint present. This prefers
4756 /// 'm' over 'r', for example.
4758 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
4759 const TargetLowering &TLI,
4760 SDValue Op, SelectionDAG *DAG) {
4761 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
4762 unsigned BestIdx = 0;
4763 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
4764 int BestGenerality = -1;
4766 // Loop over the options, keeping track of the most general one.
4767 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
4768 TargetLowering::ConstraintType CType =
4769 TLI.getConstraintType(OpInfo.Codes[i]);
4771 // Indirect 'other' or 'immediate' constraints are not allowed.
4772 if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory ||
4773 CType == TargetLowering::C_Register ||
4774 CType == TargetLowering::C_RegisterClass))
4777 // If this is an 'other' or 'immediate' constraint, see if the operand is
4778 // valid for it. For example, on X86 we might have an 'rI' constraint. If
4779 // the operand is an integer in the range [0..31] we want to use I (saving a
4780 // load of a register), otherwise we must use 'r'.
4781 if ((CType == TargetLowering::C_Other ||
4782 CType == TargetLowering::C_Immediate) && Op.getNode()) {
4783 assert(OpInfo.Codes[i].size() == 1 &&
4784 "Unhandled multi-letter 'other' constraint");
4785 std::vector<SDValue> ResultOps;
4786 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
4788 if (!ResultOps.empty()) {
4795 // Things with matching constraints can only be registers, per gcc
4796 // documentation. This mainly affects "g" constraints.
4797 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
4800 // This constraint letter is more general than the previous one, use it.
4801 int Generality = getConstraintGenerality(CType);
4802 if (Generality > BestGenerality) {
4805 BestGenerality = Generality;
4809 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
4810 OpInfo.ConstraintType = BestType;
4813 /// Determines the constraint code and constraint type to use for the specific
4814 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
4815 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
4817 SelectionDAG *DAG) const {
4818 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
4820 // Single-letter constraints ('r') are very common.
4821 if (OpInfo.Codes.size() == 1) {
4822 OpInfo.ConstraintCode = OpInfo.Codes[0];
4823 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
4825 ChooseConstraint(OpInfo, *this, Op, DAG);
4828 // 'X' matches anything.
4829 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
4830 // Labels and constants are handled elsewhere ('X' is the only thing
4831 // that matches labels). For Functions, the type here is the type of
4832 // the result, which is not what we want to look at; leave them alone.
4833 Value *v = OpInfo.CallOperandVal;
4834 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
4835 OpInfo.CallOperandVal = v;
4839 if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress)
4842 // Otherwise, try to resolve it to something we know about by looking at
4843 // the actual operand type.
4844 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
4845 OpInfo.ConstraintCode = Repl;
4846 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
4851 /// Given an exact SDIV by a constant, create a multiplication
4852 /// with the multiplicative inverse of the constant.
4853 static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
4854 const SDLoc &dl, SelectionDAG &DAG,
4855 SmallVectorImpl<SDNode *> &Created) {
4856 SDValue Op0 = N->getOperand(0);
4857 SDValue Op1 = N->getOperand(1);
4858 EVT VT = N->getValueType(0);
4859 EVT SVT = VT.getScalarType();
4860 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
4861 EVT ShSVT = ShVT.getScalarType();
4863 bool UseSRA = false;
4864 SmallVector<SDValue, 16> Shifts, Factors;
4866 auto BuildSDIVPattern = [&](ConstantSDNode *C) {
4867 if (C->isNullValue())
4869 APInt Divisor = C->getAPIntValue();
4870 unsigned Shift = Divisor.countTrailingZeros();
4872 Divisor.ashrInPlace(Shift);
4875 // Calculate the multiplicative inverse, using Newton's method.
4877 APInt Factor = Divisor;
4878 while ((t = Divisor * Factor) != 1)
4879 Factor *= APInt(Divisor.getBitWidth(), 2) - t;
4880 Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT));
4881 Factors.push_back(DAG.getConstant(Factor, dl, SVT));
4885 // Collect all magic values from the build vector.
4886 if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern))
4889 SDValue Shift, Factor;
4890 if (VT.isVector()) {
4891 Shift = DAG.getBuildVector(ShVT, dl, Shifts);
4892 Factor = DAG.getBuildVector(VT, dl, Factors);
4895 Factor = Factors[0];
4900 // Shift the value upfront if it is even, so the LSB is one.
4902 // TODO: For UDIV use SRL instead of SRA.
4904 Flags.setExact(true);
4905 Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
4906 Created.push_back(Res.getNode());
4909 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor);
4912 SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
4914 SmallVectorImpl<SDNode *> &Created) const {
4915 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4916 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4917 if (TLI.isIntDivCheap(N->getValueType(0), Attr))
4918 return SDValue(N, 0); // Lower SDIV as SDIV
4922 /// Given an ISD::SDIV node expressing a divide by constant,
4923 /// return a DAG expression to select that will generate the same value by
4924 /// multiplying by a magic number.
4925 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
4926 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
4927 bool IsAfterLegalization,
4928 SmallVectorImpl<SDNode *> &Created) const {
4930 EVT VT = N->getValueType(0);
4931 EVT SVT = VT.getScalarType();
4932 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4933 EVT ShSVT = ShVT.getScalarType();
4934 unsigned EltBits = VT.getScalarSizeInBits();
4936 // Check to see if we can do this.
4937 // FIXME: We should be more aggressive here.
4938 if (!isTypeLegal(VT))
4941 // If the sdiv has an 'exact' bit we can use a simpler lowering.
4942 if (N->getFlags().hasExact())
4943 return BuildExactSDIV(*this, N, dl, DAG, Created);
4945 SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks;
4947 auto BuildSDIVPattern = [&](ConstantSDNode *C) {
4948 if (C->isNullValue())
4951 const APInt &Divisor = C->getAPIntValue();
4952 APInt::ms magics = Divisor.magic();
4953 int NumeratorFactor = 0;
4956 if (Divisor.isOneValue() || Divisor.isAllOnesValue()) {
4957 // If d is +1/-1, we just multiply the numerator by +1/-1.
4958 NumeratorFactor = Divisor.getSExtValue();
4962 } else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
4963 // If d > 0 and m < 0, add the numerator.
4964 NumeratorFactor = 1;
4965 } else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
4966 // If d < 0 and m > 0, subtract the numerator.
4967 NumeratorFactor = -1;
4970 MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT));
4971 Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
4972 Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT));
4973 ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
4977 SDValue N0 = N->getOperand(0);
4978 SDValue N1 = N->getOperand(1);
4980 // Collect the shifts / magic values from each element.
4981 if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
4984 SDValue MagicFactor, Factor, Shift, ShiftMask;
4985 if (VT.isVector()) {
4986 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
4987 Factor = DAG.getBuildVector(VT, dl, Factors);
4988 Shift = DAG.getBuildVector(ShVT, dl, Shifts);
4989 ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
4991 MagicFactor = MagicFactors[0];
4992 Factor = Factors[0];
4994 ShiftMask = ShiftMasks[0];
4997 // Multiply the numerator (operand 0) by the magic value.
4998 // FIXME: We should support doing a MUL in a wider type.
5000 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
5001 : isOperationLegalOrCustom(ISD::MULHS, VT))
5002 Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor);
5003 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT)
5004 : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
5006 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
5007 Q = SDValue(LoHi.getNode(), 1);
5009 return SDValue(); // No mulhs or equivalent.
5010 Created.push_back(Q.getNode());
5012 // (Optionally) Add/subtract the numerator using Factor.
5013 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
5014 Created.push_back(Factor.getNode());
5015 Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor);
5016 Created.push_back(Q.getNode());
5018 // Shift right algebraic by shift value.
5019 Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
5020 Created.push_back(Q.getNode());
5022 // Extract the sign bit, mask it and add it to the quotient.
5023 SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT);
5024 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift);
5025 Created.push_back(T.getNode());
5026 T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
5027 Created.push_back(T.getNode());
5028 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
5031 /// Given an ISD::UDIV node expressing a divide by constant,
5032 /// return a DAG expression to select that will generate the same value by
5033 /// multiplying by a magic number.
5034 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
5035 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
5036 bool IsAfterLegalization,
5037 SmallVectorImpl<SDNode *> &Created) const {
5039 EVT VT = N->getValueType(0);
5040 EVT SVT = VT.getScalarType();
5041 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5042 EVT ShSVT = ShVT.getScalarType();
5043 unsigned EltBits = VT.getScalarSizeInBits();
5045 // Check to see if we can do this.
5046 // FIXME: We should be more aggressive here.
5047 if (!isTypeLegal(VT))
5050 bool UseNPQ = false;
5051 SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors;
5053 auto BuildUDIVPattern = [&](ConstantSDNode *C) {
5054 if (C->isNullValue())
5056 // FIXME: We should use a narrower constant when the upper
5057 // bits are known to be zero.
5058 APInt Divisor = C->getAPIntValue();
5059 APInt::mu magics = Divisor.magicu();
5060 unsigned PreShift = 0, PostShift = 0;
5062 // If the divisor is even, we can avoid using the expensive fixup by
5063 // shifting the divided value upfront.
5064 if (magics.a != 0 && !Divisor[0]) {
5065 PreShift = Divisor.countTrailingZeros();
5066 // Get magic number for the shifted divisor.
5067 magics = Divisor.lshr(PreShift).magicu(PreShift);
5068 assert(magics.a == 0 && "Should use cheap fixup now");
5071 APInt Magic = magics.m;
5074 if (magics.a == 0 || Divisor.isOneValue()) {
5075 assert(magics.s < Divisor.getBitWidth() &&
5076 "We shouldn't generate an undefined shift!");
5077 PostShift = magics.s;
5080 PostShift = magics.s - 1;
5084 PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT));
5085 MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT));
5086 NPQFactors.push_back(
5087 DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1)
5088 : APInt::getNullValue(EltBits),
5090 PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT));
5095 SDValue N0 = N->getOperand(0);
5096 SDValue N1 = N->getOperand(1);
5098 // Collect the shifts/magic values from each element.
5099 if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern))
5102 SDValue PreShift, PostShift, MagicFactor, NPQFactor;
5103 if (VT.isVector()) {
5104 PreShift = DAG.getBuildVector(ShVT, dl, PreShifts);
5105 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
5106 NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors);
5107 PostShift = DAG.getBuildVector(ShVT, dl, PostShifts);
5109 PreShift = PreShifts[0];
5110 MagicFactor = MagicFactors[0];
5111 PostShift = PostShifts[0];
5115 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift);
5116 Created.push_back(Q.getNode());
5118 // FIXME: We should support doing a MUL in a wider type.
5119 auto GetMULHU = [&](SDValue X, SDValue Y) {
5120 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
5121 : isOperationLegalOrCustom(ISD::MULHU, VT))
5122 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
5123 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT)
5124 : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
5126 DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
5127 return SDValue(LoHi.getNode(), 1);
5129 return SDValue(); // No mulhu or equivalent
5132 // Multiply the numerator (operand 0) by the magic value.
5133 Q = GetMULHU(Q, MagicFactor);
5137 Created.push_back(Q.getNode());
5140 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q);
5141 Created.push_back(NPQ.getNode());
5143 // For vectors we might have a mix of non-NPQ/NPQ paths, so use
5144 // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
5146 NPQ = GetMULHU(NPQ, NPQFactor);
5148 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT));
5150 Created.push_back(NPQ.getNode());
5152 Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
5153 Created.push_back(Q.getNode());
5156 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift);
5157 Created.push_back(Q.getNode());
5159 SDValue One = DAG.getConstant(1, dl, VT);
5160 SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ);
5161 return DAG.getSelect(dl, VT, IsOne, N0, Q);
5164 /// If all values in Values that *don't* match the predicate are same 'splat'
5165 /// value, then replace all values with that splat value.
5166 /// Else, if AlternativeReplacement was provided, then replace all values that
5167 /// do match predicate with AlternativeReplacement value.
5169 turnVectorIntoSplatVector(MutableArrayRef<SDValue> Values,
5170 std::function<bool(SDValue)> Predicate,
5171 SDValue AlternativeReplacement = SDValue()) {
5172 SDValue Replacement;
5173 // Is there a value for which the Predicate does *NOT* match? What is it?
5174 auto SplatValue = llvm::find_if_not(Values, Predicate);
5175 if (SplatValue != Values.end()) {
5176 // Does Values consist only of SplatValue's and values matching Predicate?
5177 if (llvm::all_of(Values, [Predicate, SplatValue](SDValue Value) {
5178 return Value == *SplatValue || Predicate(Value);
5179 })) // Then we shall replace values matching predicate with SplatValue.
5180 Replacement = *SplatValue;
5183 // Oops, we did not find the "baseline" splat value.
5184 if (!AlternativeReplacement)
5185 return; // Nothing to do.
5186 // Let's replace with provided value then.
5187 Replacement = AlternativeReplacement;
5189 std::replace_if(Values.begin(), Values.end(), Predicate, Replacement);
5192 /// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE
5193 /// where the divisor is constant and the comparison target is zero,
5194 /// return a DAG expression that will generate the same comparison result
5195 /// using only multiplications, additions and shifts/rotations.
5196 /// Ref: "Hacker's Delight" 10-17.
5197 SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode,
5198 SDValue CompTargetNode,
5200 DAGCombinerInfo &DCI,
5201 const SDLoc &DL) const {
5202 SmallVector<SDNode *, 5> Built;
5203 if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond,
5205 for (SDNode *N : Built)
5206 DCI.AddToWorklist(N);
5214 TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
5215 SDValue CompTargetNode, ISD::CondCode Cond,
5216 DAGCombinerInfo &DCI, const SDLoc &DL,
5217 SmallVectorImpl<SDNode *> &Created) const {
5218 // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q)
5219 // - D must be constant, with D = D0 * 2^K where D0 is odd
5220 // - P is the multiplicative inverse of D0 modulo 2^W
5221 // - Q = floor(((2^W) - 1) / D)
5222 // where W is the width of the common type of N and D.
5223 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
5224 "Only applicable for (in)equality comparisons.");
5226 SelectionDAG &DAG = DCI.DAG;
5228 EVT VT = REMNode.getValueType();
5229 EVT SVT = VT.getScalarType();
5230 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5231 EVT ShSVT = ShVT.getScalarType();
5233 // If MUL is unavailable, we cannot proceed in any case.
5234 if (!isOperationLegalOrCustom(ISD::MUL, VT))
5237 bool ComparingWithAllZeros = true;
5238 bool AllComparisonsWithNonZerosAreTautological = true;
5239 bool HadTautologicalLanes = false;
5240 bool AllLanesAreTautological = true;
5241 bool HadEvenDivisor = false;
5242 bool AllDivisorsArePowerOfTwo = true;
5243 bool HadTautologicalInvertedLanes = false;
5244 SmallVector<SDValue, 16> PAmts, KAmts, QAmts, IAmts;
5246 auto BuildUREMPattern = [&](ConstantSDNode *CDiv, ConstantSDNode *CCmp) {
5247 // Division by 0 is UB. Leave it to be constant-folded elsewhere.
5248 if (CDiv->isNullValue())
5251 const APInt &D = CDiv->getAPIntValue();
5252 const APInt &Cmp = CCmp->getAPIntValue();
5254 ComparingWithAllZeros &= Cmp.isNullValue();
5256 // x u% C1` is *always* less than C1. So given `x u% C1 == C2`,
5257 // if C2 is not less than C1, the comparison is always false.
5258 // But we will only be able to produce the comparison that will give the
5259 // opposive tautological answer. So this lane would need to be fixed up.
5260 bool TautologicalInvertedLane = D.ule(Cmp);
5261 HadTautologicalInvertedLanes |= TautologicalInvertedLane;
5263 // If all lanes are tautological (either all divisors are ones, or divisor
5264 // is not greater than the constant we are comparing with),
5265 // we will prefer to avoid the fold.
5266 bool TautologicalLane = D.isOneValue() || TautologicalInvertedLane;
5267 HadTautologicalLanes |= TautologicalLane;
5268 AllLanesAreTautological &= TautologicalLane;
5270 // If we are comparing with non-zero, we need'll need to subtract said
5271 // comparison value from the LHS. But there is no point in doing that if
5272 // every lane where we are comparing with non-zero is tautological..
5273 if (!Cmp.isNullValue())
5274 AllComparisonsWithNonZerosAreTautological &= TautologicalLane;
5276 // Decompose D into D0 * 2^K
5277 unsigned K = D.countTrailingZeros();
5278 assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.");
5279 APInt D0 = D.lshr(K);
5281 // D is even if it has trailing zeros.
5282 HadEvenDivisor |= (K != 0);
5283 // D is a power-of-two if D0 is one.
5284 // If all divisors are power-of-two, we will prefer to avoid the fold.
5285 AllDivisorsArePowerOfTwo &= D0.isOneValue();
5288 // 2^W requires W + 1 bits, so we have to extend and then truncate.
5289 unsigned W = D.getBitWidth();
5290 APInt P = D0.zext(W + 1)
5291 .multiplicativeInverse(APInt::getSignedMinValue(W + 1))
5293 assert(!P.isNullValue() && "No multiplicative inverse!"); // unreachable
5294 assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.");
5296 // Q = floor((2^W - 1) u/ D)
5297 // R = ((2^W - 1) u% D)
5299 APInt::udivrem(APInt::getAllOnesValue(W), D, Q, R);
5301 // If we are comparing with zero, then that comparison constant is okay,
5302 // else it may need to be one less than that.
5306 assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
5307 "We are expecting that K is always less than all-ones for ShSVT");
5309 // If the lane is tautological the result can be constant-folded.
5310 if (TautologicalLane) {
5311 // Set P and K amount to a bogus values so we can try to splat them.
5314 // And ensure that comparison constant is tautological,
5315 // it will always compare true/false.
5319 PAmts.push_back(DAG.getConstant(P, DL, SVT));
5321 DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT));
5322 QAmts.push_back(DAG.getConstant(Q, DL, SVT));
5326 SDValue N = REMNode.getOperand(0);
5327 SDValue D = REMNode.getOperand(1);
5329 // Collect the values from each element.
5330 if (!ISD::matchBinaryPredicate(D, CompTargetNode, BuildUREMPattern))
5333 // If all lanes are tautological, the result can be constant-folded.
5334 if (AllLanesAreTautological)
5337 // If this is a urem by a powers-of-two, avoid the fold since it can be
5338 // best implemented as a bit test.
5339 if (AllDivisorsArePowerOfTwo)
5342 SDValue PVal, KVal, QVal;
5343 if (VT.isVector()) {
5344 if (HadTautologicalLanes) {
5345 // Try to turn PAmts into a splat, since we don't care about the values
5346 // that are currently '0'. If we can't, just keep '0'`s.
5347 turnVectorIntoSplatVector(PAmts, isNullConstant);
5348 // Try to turn KAmts into a splat, since we don't care about the values
5349 // that are currently '-1'. If we can't, change them to '0'`s.
5350 turnVectorIntoSplatVector(KAmts, isAllOnesConstant,
5351 DAG.getConstant(0, DL, ShSVT));
5354 PVal = DAG.getBuildVector(VT, DL, PAmts);
5355 KVal = DAG.getBuildVector(ShVT, DL, KAmts);
5356 QVal = DAG.getBuildVector(VT, DL, QAmts);
5363 if (!ComparingWithAllZeros && !AllComparisonsWithNonZerosAreTautological) {
5364 if (!isOperationLegalOrCustom(ISD::SUB, VT))
5365 return SDValue(); // FIXME: Could/should use `ISD::ADD`?
5366 assert(CompTargetNode.getValueType() == N.getValueType() &&
5367 "Expecting that the types on LHS and RHS of comparisons match.");
5368 N = DAG.getNode(ISD::SUB, DL, VT, N, CompTargetNode);
5372 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5373 Created.push_back(Op0.getNode());
5375 // Rotate right only if any divisor was even. We avoid rotates for all-odd
5376 // divisors as a performance improvement, since rotating by 0 is a no-op.
5377 if (HadEvenDivisor) {
5378 // We need ROTR to do this.
5379 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5382 Flags.setExact(true);
5383 // UREM: (rotr (mul N, P), K)
5384 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5385 Created.push_back(Op0.getNode());
5388 // UREM: (setule/setugt (rotr (mul N, P), K), Q)
5390 DAG.getSetCC(DL, SETCCVT, Op0, QVal,
5391 ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
5392 if (!HadTautologicalInvertedLanes)
5395 // If any lanes previously compared always-false, the NewCC will give
5396 // always-true result for them, so we need to fixup those lanes.
5397 // Or the other way around for inequality predicate.
5398 assert(VT.isVector() && "Can/should only get here for vectors.");
5399 Created.push_back(NewCC.getNode());
5401 // x u% C1` is *always* less than C1. So given `x u% C1 == C2`,
5402 // if C2 is not less than C1, the comparison is always false.
5403 // But we have produced the comparison that will give the
5404 // opposive tautological answer. So these lanes would need to be fixed up.
5405 SDValue TautologicalInvertedChannels =
5406 DAG.getSetCC(DL, SETCCVT, D, CompTargetNode, ISD::SETULE);
5407 Created.push_back(TautologicalInvertedChannels.getNode());
5409 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) {
5410 // If we have a vector select, let's replace the comparison results in the
5411 // affected lanes with the correct tautological result.
5412 SDValue Replacement = DAG.getBoolConstant(Cond == ISD::SETEQ ? false : true,
5413 DL, SETCCVT, SETCCVT);
5414 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels,
5415 Replacement, NewCC);
5418 // Else, we can just invert the comparison result in the appropriate lanes.
5419 if (isOperationLegalOrCustom(ISD::XOR, SETCCVT))
5420 return DAG.getNode(ISD::XOR, DL, SETCCVT, NewCC,
5421 TautologicalInvertedChannels);
5423 return SDValue(); // Don't know how to lower.
5426 /// Given an ISD::SREM used only by an ISD::SETEQ or ISD::SETNE
5427 /// where the divisor is constant and the comparison target is zero,
5428 /// return a DAG expression that will generate the same comparison result
5429 /// using only multiplications, additions and shifts/rotations.
5430 /// Ref: "Hacker's Delight" 10-17.
5431 SDValue TargetLowering::buildSREMEqFold(EVT SETCCVT, SDValue REMNode,
5432 SDValue CompTargetNode,
5434 DAGCombinerInfo &DCI,
5435 const SDLoc &DL) const {
5436 SmallVector<SDNode *, 7> Built;
5437 if (SDValue Folded = prepareSREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond,
5439 assert(Built.size() <= 7 && "Max size prediction failed.");
5440 for (SDNode *N : Built)
5441 DCI.AddToWorklist(N);
5449 TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
5450 SDValue CompTargetNode, ISD::CondCode Cond,
5451 DAGCombinerInfo &DCI, const SDLoc &DL,
5452 SmallVectorImpl<SDNode *> &Created) const {
5454 // (seteq/ne (srem N, D), 0)
5456 // (setule/ugt (rotr (add (mul N, P), A), K), Q)
5458 // - D must be constant, with D = D0 * 2^K where D0 is odd
5459 // - P is the multiplicative inverse of D0 modulo 2^W
5460 // - A = bitwiseand(floor((2^(W - 1) - 1) / D0), (-(2^k)))
5461 // - Q = floor((2 * A) / (2^K))
5462 // where W is the width of the common type of N and D.
5463 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
5464 "Only applicable for (in)equality comparisons.");
5466 SelectionDAG &DAG = DCI.DAG;
5468 EVT VT = REMNode.getValueType();
5469 EVT SVT = VT.getScalarType();
5470 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5471 EVT ShSVT = ShVT.getScalarType();
5473 // If MUL is unavailable, we cannot proceed in any case.
5474 if (!isOperationLegalOrCustom(ISD::MUL, VT))
5477 // TODO: Could support comparing with non-zero too.
5478 ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode);
5479 if (!CompTarget || !CompTarget->isNullValue())
5482 bool HadIntMinDivisor = false;
5483 bool HadOneDivisor = false;
5484 bool AllDivisorsAreOnes = true;
5485 bool HadEvenDivisor = false;
5486 bool NeedToApplyOffset = false;
5487 bool AllDivisorsArePowerOfTwo = true;
5488 SmallVector<SDValue, 16> PAmts, AAmts, KAmts, QAmts;
5490 auto BuildSREMPattern = [&](ConstantSDNode *C) {
5491 // Division by 0 is UB. Leave it to be constant-folded elsewhere.
5492 if (C->isNullValue())
5495 // FIXME: we don't fold `rem %X, -C` to `rem %X, C` in DAGCombine.
5497 // WARNING: this fold is only valid for positive divisors!
5498 APInt D = C->getAPIntValue();
5500 D.negate(); // `rem %X, -C` is equivalent to `rem %X, C`
5502 HadIntMinDivisor |= D.isMinSignedValue();
5504 // If all divisors are ones, we will prefer to avoid the fold.
5505 HadOneDivisor |= D.isOneValue();
5506 AllDivisorsAreOnes &= D.isOneValue();
5508 // Decompose D into D0 * 2^K
5509 unsigned K = D.countTrailingZeros();
5510 assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.");
5511 APInt D0 = D.lshr(K);
5513 if (!D.isMinSignedValue()) {
5514 // D is even if it has trailing zeros; unless it's INT_MIN, in which case
5515 // we don't care about this lane in this fold, we'll special-handle it.
5516 HadEvenDivisor |= (K != 0);
5519 // D is a power-of-two if D0 is one. This includes INT_MIN.
5520 // If all divisors are power-of-two, we will prefer to avoid the fold.
5521 AllDivisorsArePowerOfTwo &= D0.isOneValue();
5524 // 2^W requires W + 1 bits, so we have to extend and then truncate.
5525 unsigned W = D.getBitWidth();
5526 APInt P = D0.zext(W + 1)
5527 .multiplicativeInverse(APInt::getSignedMinValue(W + 1))
5529 assert(!P.isNullValue() && "No multiplicative inverse!"); // unreachable
5530 assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.");
5532 // A = floor((2^(W - 1) - 1) / D0) & -2^K
5533 APInt A = APInt::getSignedMaxValue(W).udiv(D0);
5536 if (!D.isMinSignedValue()) {
5537 // If divisor INT_MIN, then we don't care about this lane in this fold,
5538 // we'll special-handle it.
5539 NeedToApplyOffset |= A != 0;
5542 // Q = floor((2 * A) / (2^K))
5543 APInt Q = (2 * A).udiv(APInt::getOneBitSet(W, K));
5545 assert(APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) &&
5546 "We are expecting that A is always less than all-ones for SVT");
5547 assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
5548 "We are expecting that K is always less than all-ones for ShSVT");
5550 // If the divisor is 1 the result can be constant-folded. Likewise, we
5551 // don't care about INT_MIN lanes, those can be set to undef if appropriate.
5552 if (D.isOneValue()) {
5553 // Set P, A and K to a bogus values so we can try to splat them.
5558 // x ?% 1 == 0 <--> true <--> x u<= -1
5562 PAmts.push_back(DAG.getConstant(P, DL, SVT));
5563 AAmts.push_back(DAG.getConstant(A, DL, SVT));
5565 DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT));
5566 QAmts.push_back(DAG.getConstant(Q, DL, SVT));
5570 SDValue N = REMNode.getOperand(0);
5571 SDValue D = REMNode.getOperand(1);
5573 // Collect the values from each element.
5574 if (!ISD::matchUnaryPredicate(D, BuildSREMPattern))
5577 // If this is a srem by a one, avoid the fold since it can be constant-folded.
5578 if (AllDivisorsAreOnes)
5581 // If this is a srem by a powers-of-two (including INT_MIN), avoid the fold
5582 // since it can be best implemented as a bit test.
5583 if (AllDivisorsArePowerOfTwo)
5586 SDValue PVal, AVal, KVal, QVal;
5587 if (VT.isVector()) {
5588 if (HadOneDivisor) {
5589 // Try to turn PAmts into a splat, since we don't care about the values
5590 // that are currently '0'. If we can't, just keep '0'`s.
5591 turnVectorIntoSplatVector(PAmts, isNullConstant);
5592 // Try to turn AAmts into a splat, since we don't care about the
5593 // values that are currently '-1'. If we can't, change them to '0'`s.
5594 turnVectorIntoSplatVector(AAmts, isAllOnesConstant,
5595 DAG.getConstant(0, DL, SVT));
5596 // Try to turn KAmts into a splat, since we don't care about the values
5597 // that are currently '-1'. If we can't, change them to '0'`s.
5598 turnVectorIntoSplatVector(KAmts, isAllOnesConstant,
5599 DAG.getConstant(0, DL, ShSVT));
5602 PVal = DAG.getBuildVector(VT, DL, PAmts);
5603 AVal = DAG.getBuildVector(VT, DL, AAmts);
5604 KVal = DAG.getBuildVector(ShVT, DL, KAmts);
5605 QVal = DAG.getBuildVector(VT, DL, QAmts);
5614 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5615 Created.push_back(Op0.getNode());
5617 if (NeedToApplyOffset) {
5618 // We need ADD to do this.
5619 if (!isOperationLegalOrCustom(ISD::ADD, VT))
5622 // (add (mul N, P), A)
5623 Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal);
5624 Created.push_back(Op0.getNode());
5627 // Rotate right only if any divisor was even. We avoid rotates for all-odd
5628 // divisors as a performance improvement, since rotating by 0 is a no-op.
5629 if (HadEvenDivisor) {
5630 // We need ROTR to do this.
5631 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5634 Flags.setExact(true);
5635 // SREM: (rotr (add (mul N, P), A), K)
5636 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5637 Created.push_back(Op0.getNode());
5640 // SREM: (setule/setugt (rotr (add (mul N, P), A), K), Q)
5642 DAG.getSetCC(DL, SETCCVT, Op0, QVal,
5643 ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
5645 // If we didn't have lanes with INT_MIN divisor, then we're done.
5646 if (!HadIntMinDivisor)
5649 // That fold is only valid for positive divisors. Which effectively means,
5650 // it is invalid for INT_MIN divisors. So if we have such a lane,
5651 // we must fix-up results for said lanes.
5652 assert(VT.isVector() && "Can/should only get here for vectors.");
5654 if (!isOperationLegalOrCustom(ISD::SETEQ, VT) ||
5655 !isOperationLegalOrCustom(ISD::AND, VT) ||
5656 !isOperationLegalOrCustom(Cond, VT) ||
5657 !isOperationLegalOrCustom(ISD::VSELECT, VT))
5660 Created.push_back(Fold.getNode());
5662 SDValue IntMin = DAG.getConstant(
5663 APInt::getSignedMinValue(SVT.getScalarSizeInBits()), DL, VT);
5664 SDValue IntMax = DAG.getConstant(
5665 APInt::getSignedMaxValue(SVT.getScalarSizeInBits()), DL, VT);
5667 DAG.getConstant(APInt::getNullValue(SVT.getScalarSizeInBits()), DL, VT);
5669 // Which lanes had INT_MIN divisors? Divisor is constant, so const-folded.
5670 SDValue DivisorIsIntMin = DAG.getSetCC(DL, SETCCVT, D, IntMin, ISD::SETEQ);
5671 Created.push_back(DivisorIsIntMin.getNode());
5673 // (N s% INT_MIN) ==/!= 0 <--> (N & INT_MAX) ==/!= 0
5674 SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax);
5675 Created.push_back(Masked.getNode());
5676 SDValue MaskedIsZero = DAG.getSetCC(DL, SETCCVT, Masked, Zero, Cond);
5677 Created.push_back(MaskedIsZero.getNode());
5679 // To produce final result we need to blend 2 vectors: 'SetCC' and
5680 // 'MaskedIsZero'. If the divisor for channel was *NOT* INT_MIN, we pick
5681 // from 'Fold', else pick from 'MaskedIsZero'. Since 'DivisorIsIntMin' is
5682 // constant-folded, select can get lowered to a shuffle with constant mask.
5684 DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold);
5689 bool TargetLowering::
5690 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
5691 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
5692 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
5693 "be a constant integer");
5700 SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
5701 bool LegalOps, bool OptForSize,
5702 NegatibleCost &Cost,
5703 unsigned Depth) const {
5704 // fneg is removable even if it has multiple uses.
5705 if (Op.getOpcode() == ISD::FNEG) {
5706 Cost = NegatibleCost::Cheaper;
5707 return Op.getOperand(0);
5710 // Don't recurse exponentially.
5711 if (Depth > SelectionDAG::MaxRecursionDepth)
5714 // Pre-increment recursion depth for use in recursive calls.
5716 const SDNodeFlags Flags = Op->getFlags();
5717 const TargetOptions &Options = DAG.getTarget().Options;
5718 EVT VT = Op.getValueType();
5719 unsigned Opcode = Op.getOpcode();
5721 // Don't allow anything with multiple uses unless we know it is free.
5722 if (!Op.hasOneUse() && Opcode != ISD::ConstantFP) {
5723 bool IsFreeExtend = Opcode == ISD::FP_EXTEND &&
5724 isFPExtFree(VT, Op.getOperand(0).getValueType());
5729 auto RemoveDeadNode = [&](SDValue N) {
5730 if (N && N.getNode()->use_empty())
5731 DAG.RemoveDeadNode(N.getNode());
5737 case ISD::ConstantFP: {
5738 // Don't invert constant FP values after legalization unless the target says
5739 // the negated constant is legal.
5741 isOperationLegal(ISD::ConstantFP, VT) ||
5742 isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT,
5745 if (LegalOps && !IsOpLegal)
5748 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
5750 SDValue CFP = DAG.getConstantFP(V, DL, VT);
5752 // If we already have the use of the negated floating constant, it is free
5753 // to negate it even it has multiple uses.
5754 if (!Op.hasOneUse() && CFP.use_empty())
5756 Cost = NegatibleCost::Neutral;
5759 case ISD::BUILD_VECTOR: {
5760 // Only permit BUILD_VECTOR of constants.
5761 if (llvm::any_of(Op->op_values(), [&](SDValue N) {
5762 return !N.isUndef() && !isa<ConstantFPSDNode>(N);
5767 (isOperationLegal(ISD::ConstantFP, VT) &&
5768 isOperationLegal(ISD::BUILD_VECTOR, VT)) ||
5769 llvm::all_of(Op->op_values(), [&](SDValue N) {
5770 return N.isUndef() ||
5771 isFPImmLegal(neg(cast<ConstantFPSDNode>(N)->getValueAPF()), VT,
5775 if (LegalOps && !IsOpLegal)
5778 SmallVector<SDValue, 4> Ops;
5779 for (SDValue C : Op->op_values()) {
5784 APFloat V = cast<ConstantFPSDNode>(C)->getValueAPF();
5786 Ops.push_back(DAG.getConstantFP(V, DL, C.getValueType()));
5788 Cost = NegatibleCost::Neutral;
5789 return DAG.getBuildVector(VT, DL, Ops);
5792 if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
5795 // After operation legalization, it might not be legal to create new FSUBs.
5796 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT))
5798 SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
5800 // fold (fneg (fadd X, Y)) -> (fsub (fneg X), Y)
5801 NegatibleCost CostX = NegatibleCost::Expensive;
5803 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth);
5804 // fold (fneg (fadd X, Y)) -> (fsub (fneg Y), X)
5805 NegatibleCost CostY = NegatibleCost::Expensive;
5807 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth);
5809 // Negate the X if its cost is less or equal than Y.
5810 if (NegX && (CostX <= CostY)) {
5812 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegX, Y, Flags);
5814 RemoveDeadNode(NegY);
5818 // Negate the Y if it is not expensive.
5821 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegY, X, Flags);
5823 RemoveDeadNode(NegX);
5829 // We can't turn -(A-B) into B-A when we honor signed zeros.
5830 if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
5833 SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
5834 // fold (fneg (fsub 0, Y)) -> Y
5835 if (ConstantFPSDNode *C = isConstOrConstSplatFP(X, /*AllowUndefs*/ true))
5837 Cost = NegatibleCost::Cheaper;
5841 // fold (fneg (fsub X, Y)) -> (fsub Y, X)
5842 Cost = NegatibleCost::Neutral;
5843 return DAG.getNode(ISD::FSUB, DL, VT, Y, X, Flags);
5847 SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
5849 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
5850 NegatibleCost CostX = NegatibleCost::Expensive;
5852 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth);
5853 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
5854 NegatibleCost CostY = NegatibleCost::Expensive;
5856 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth);
5858 // Negate the X if its cost is less or equal than Y.
5859 if (NegX && (CostX <= CostY)) {
5861 SDValue N = DAG.getNode(Opcode, DL, VT, NegX, Y, Flags);
5863 RemoveDeadNode(NegY);
5867 // Ignore X * 2.0 because that is expected to be canonicalized to X + X.
5868 if (auto *C = isConstOrConstSplatFP(Op.getOperand(1)))
5869 if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL)
5872 // Negate the Y if it is not expensive.
5875 SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, Flags);
5877 RemoveDeadNode(NegX);
5884 if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
5887 SDValue X = Op.getOperand(0), Y = Op.getOperand(1), Z = Op.getOperand(2);
5888 NegatibleCost CostZ = NegatibleCost::Expensive;
5890 getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth);
5891 // Give up if fail to negate the Z.
5895 // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z))
5896 NegatibleCost CostX = NegatibleCost::Expensive;
5898 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth);
5899 // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z))
5900 NegatibleCost CostY = NegatibleCost::Expensive;
5902 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth);
5904 // Negate the X if its cost is less or equal than Y.
5905 if (NegX && (CostX <= CostY)) {
5906 Cost = std::min(CostX, CostZ);
5907 SDValue N = DAG.getNode(Opcode, DL, VT, NegX, Y, NegZ, Flags);
5909 RemoveDeadNode(NegY);
5913 // Negate the Y if it is not expensive.
5915 Cost = std::min(CostY, CostZ);
5916 SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, NegZ, Flags);
5918 RemoveDeadNode(NegX);
5924 case ISD::FP_EXTEND:
5926 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps,
5927 OptForSize, Cost, Depth))
5928 return DAG.getNode(Opcode, DL, VT, NegV);
5931 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps,
5932 OptForSize, Cost, Depth))
5933 return DAG.getNode(ISD::FP_ROUND, DL, VT, NegV, Op.getOperand(1));
5940 //===----------------------------------------------------------------------===//
5941 // Legalization Utilities
5942 //===----------------------------------------------------------------------===//
5944 bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl,
5945 SDValue LHS, SDValue RHS,
5946 SmallVectorImpl<SDValue> &Result,
5947 EVT HiLoVT, SelectionDAG &DAG,
5948 MulExpansionKind Kind, SDValue LL,
5949 SDValue LH, SDValue RL, SDValue RH) const {
5950 assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||
5951 Opcode == ISD::SMUL_LOHI);
5953 bool HasMULHS = (Kind == MulExpansionKind::Always) ||
5954 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
5955 bool HasMULHU = (Kind == MulExpansionKind::Always) ||
5956 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
5957 bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) ||
5958 isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
5959 bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) ||
5960 isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
5962 if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI)
5965 unsigned OuterBitSize = VT.getScalarSizeInBits();
5966 unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
5967 unsigned LHSSB = DAG.ComputeNumSignBits(LHS);
5968 unsigned RHSSB = DAG.ComputeNumSignBits(RHS);
5970 // LL, LH, RL, and RH must be either all NULL or all set to a value.
5971 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
5972 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
5974 SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
5975 auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi,
5976 bool Signed) -> bool {
5977 if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) {
5978 Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
5979 Hi = SDValue(Lo.getNode(), 1);
5982 if ((Signed && HasMULHS) || (!Signed && HasMULHU)) {
5983 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
5984 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
5992 if (!LL.getNode() && !RL.getNode() &&
5993 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
5994 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
5995 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
6001 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6002 if (DAG.MaskedValueIsZero(LHS, HighMask) &&
6003 DAG.MaskedValueIsZero(RHS, HighMask)) {
6004 // The inputs are both zero-extended.
6005 if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
6006 Result.push_back(Lo);
6007 Result.push_back(Hi);
6008 if (Opcode != ISD::MUL) {
6009 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
6010 Result.push_back(Zero);
6011 Result.push_back(Zero);
6017 if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
6018 RHSSB > InnerBitSize) {
6019 // The input values are both sign-extended.
6020 // TODO non-MUL case?
6021 if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
6022 Result.push_back(Lo);
6023 Result.push_back(Hi);
6028 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
6029 EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
6030 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
6031 // FIXME getShiftAmountTy does not always return a sensible result when VT
6032 // is an illegal type, and so the type may be too small to fit the shift
6033 // amount. Override it with i32. The shift will have to be legalized.
6034 ShiftAmountTy = MVT::i32;
6036 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
6038 if (!LH.getNode() && !RH.getNode() &&
6039 isOperationLegalOrCustom(ISD::SRL, VT) &&
6040 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
6041 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
6042 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
6043 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
6044 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
6050 if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
6053 Result.push_back(Lo);
6055 if (Opcode == ISD::MUL) {
6056 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
6057 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
6058 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
6059 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
6060 Result.push_back(Hi);
6064 // Compute the full width result.
6065 auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue {
6066 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
6067 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
6068 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
6069 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
6072 SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
6073 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
6076 // This is effectively the add part of a multiply-add of half-sized operands,
6077 // so it cannot overflow.
6078 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
6080 if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false))
6083 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
6084 EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
6086 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) &&
6087 isOperationLegalOrCustom(ISD::ADDE, VT));
6089 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
6092 Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
6093 Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType));
6095 SDValue Carry = Next.getValue(1);
6096 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
6097 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
6099 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
6103 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
6106 Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
6109 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
6111 if (Opcode == ISD::SMUL_LOHI) {
6112 SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
6113 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL));
6114 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
6116 NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
6117 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
6118 Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT);
6121 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
6122 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
6123 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
6127 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
6128 SelectionDAG &DAG, MulExpansionKind Kind,
6129 SDValue LL, SDValue LH, SDValue RL,
6131 SmallVector<SDValue, 2> Result;
6132 bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), N,
6133 N->getOperand(0), N->getOperand(1), Result, HiLoVT,
6134 DAG, Kind, LL, LH, RL, RH);
6136 assert(Result.size() == 2);
6143 // Check that (every element of) Z is undef or not an exact multiple of BW.
6144 static bool isNonZeroModBitWidth(SDValue Z, unsigned BW) {
6145 return ISD::matchUnaryPredicate(
6147 [=](ConstantSDNode *C) { return !C || C->getAPIntValue().urem(BW) != 0; },
6151 bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,
6152 SelectionDAG &DAG) const {
6153 EVT VT = Node->getValueType(0);
6155 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
6156 !isOperationLegalOrCustom(ISD::SRL, VT) ||
6157 !isOperationLegalOrCustom(ISD::SUB, VT) ||
6158 !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
6161 SDValue X = Node->getOperand(0);
6162 SDValue Y = Node->getOperand(1);
6163 SDValue Z = Node->getOperand(2);
6165 unsigned BW = VT.getScalarSizeInBits();
6166 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
6167 SDLoc DL(SDValue(Node, 0));
6169 EVT ShVT = Z.getValueType();
6172 SDValue ShAmt, InvShAmt;
6173 if (isNonZeroModBitWidth(Z, BW)) {
6174 // fshl: X << C | Y >> (BW - C)
6175 // fshr: X << (BW - C) | Y >> C
6176 // where C = Z % BW is not zero
6177 SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT);
6178 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC);
6179 InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, ShAmt);
6180 ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt);
6181 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt);
6183 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW))
6184 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW)
6185 SDValue Mask = DAG.getConstant(BW - 1, DL, ShVT);
6186 if (isPowerOf2_32(BW)) {
6187 // Z % BW -> Z & (BW - 1)
6188 ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Z, Mask);
6189 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1)
6190 InvShAmt = DAG.getNode(ISD::AND, DL, ShVT, DAG.getNOT(DL, Z, ShVT), Mask);
6192 SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT);
6193 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC);
6194 InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, Mask, ShAmt);
6197 SDValue One = DAG.getConstant(1, DL, ShVT);
6199 ShX = DAG.getNode(ISD::SHL, DL, VT, X, ShAmt);
6200 SDValue ShY1 = DAG.getNode(ISD::SRL, DL, VT, Y, One);
6201 ShY = DAG.getNode(ISD::SRL, DL, VT, ShY1, InvShAmt);
6203 SDValue ShX1 = DAG.getNode(ISD::SHL, DL, VT, X, One);
6204 ShX = DAG.getNode(ISD::SHL, DL, VT, ShX1, InvShAmt);
6205 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, ShAmt);
6208 Result = DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
6212 // TODO: Merge with expandFunnelShift.
6213 bool TargetLowering::expandROT(SDNode *Node, SDValue &Result,
6214 SelectionDAG &DAG) const {
6215 EVT VT = Node->getValueType(0);
6216 unsigned EltSizeInBits = VT.getScalarSizeInBits();
6217 bool IsLeft = Node->getOpcode() == ISD::ROTL;
6218 SDValue Op0 = Node->getOperand(0);
6219 SDValue Op1 = Node->getOperand(1);
6220 SDLoc DL(SDValue(Node, 0));
6222 EVT ShVT = Op1.getValueType();
6223 SDValue Zero = DAG.getConstant(0, DL, ShVT);
6225 assert(isPowerOf2_32(EltSizeInBits) && EltSizeInBits > 1 &&
6226 "Expecting the type bitwidth to be a power of 2");
6228 // If a rotate in the other direction is supported, use it.
6229 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
6230 if (isOperationLegalOrCustom(RevRot, VT)) {
6231 SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1);
6232 Result = DAG.getNode(RevRot, DL, VT, Op0, Sub);
6236 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
6237 !isOperationLegalOrCustom(ISD::SRL, VT) ||
6238 !isOperationLegalOrCustom(ISD::SUB, VT) ||
6239 !isOperationLegalOrCustomOrPromote(ISD::OR, VT) ||
6240 !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
6244 // (rotl x, c) -> (or (shl x, (and c, w-1)), (srl x, (and -c, w-1)))
6245 // (rotr x, c) -> (or (srl x, (and c, w-1)), (shl x, (and -c, w-1)))
6247 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
6248 unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL;
6249 SDValue BitWidthMinusOneC = DAG.getConstant(EltSizeInBits - 1, DL, ShVT);
6250 SDValue NegOp1 = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1);
6251 SDValue And0 = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC);
6252 SDValue And1 = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC);
6253 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
6254 DAG.getNode(HsOpc, DL, VT, Op0, And1));
6258 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
6259 SelectionDAG &DAG) const {
6260 unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0;
6261 SDValue Src = Node->getOperand(OpNo);
6262 EVT SrcVT = Src.getValueType();
6263 EVT DstVT = Node->getValueType(0);
6264 SDLoc dl(SDValue(Node, 0));
6266 // FIXME: Only f32 to i64 conversions are supported.
6267 if (SrcVT != MVT::f32 || DstVT != MVT::i64)
6270 if (Node->isStrictFPOpcode())
6271 // When a NaN is converted to an integer a trap is allowed. We can't
6272 // use this expansion here because it would eliminate that trap. Other
6273 // traps are also allowed and cannot be eliminated. See
6274 // IEEE 754-2008 sec 5.8.
6277 // Expand f32 -> i64 conversion
6278 // This algorithm comes from compiler-rt's implementation of fixsfdi:
6279 // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c
6280 unsigned SrcEltBits = SrcVT.getScalarSizeInBits();
6281 EVT IntVT = SrcVT.changeTypeToInteger();
6282 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout());
6284 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
6285 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
6286 SDValue Bias = DAG.getConstant(127, dl, IntVT);
6287 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT);
6288 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT);
6289 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
6291 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src);
6293 SDValue ExponentBits = DAG.getNode(
6294 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
6295 DAG.getZExtOrTrunc(ExponentLoBit, dl, IntShVT));
6296 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
6298 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
6299 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
6300 DAG.getZExtOrTrunc(SignLowBit, dl, IntShVT));
6301 Sign = DAG.getSExtOrTrunc(Sign, dl, DstVT);
6303 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
6304 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
6305 DAG.getConstant(0x00800000, dl, IntVT));
6307 R = DAG.getZExtOrTrunc(R, dl, DstVT);
6309 R = DAG.getSelectCC(
6310 dl, Exponent, ExponentLoBit,
6311 DAG.getNode(ISD::SHL, dl, DstVT, R,
6313 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
6315 DAG.getNode(ISD::SRL, dl, DstVT, R,
6317 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
6321 SDValue Ret = DAG.getNode(ISD::SUB, dl, DstVT,
6322 DAG.getNode(ISD::XOR, dl, DstVT, R, Sign), Sign);
6324 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
6325 DAG.getConstant(0, dl, DstVT), Ret, ISD::SETLT);
6329 bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result,
6331 SelectionDAG &DAG) const {
6332 SDLoc dl(SDValue(Node, 0));
6333 unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0;
6334 SDValue Src = Node->getOperand(OpNo);
6336 EVT SrcVT = Src.getValueType();
6337 EVT DstVT = Node->getValueType(0);
6339 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
6341 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT);
6343 // Only expand vector types if we have the appropriate vector bit operations.
6344 unsigned SIntOpcode = Node->isStrictFPOpcode() ? ISD::STRICT_FP_TO_SINT :
6346 if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) ||
6347 !isOperationLegalOrCustomOrPromote(ISD::XOR, SrcVT)))
6350 // If the maximum float value is smaller then the signed integer range,
6351 // the destination signmask can't be represented by the float, so we can
6352 // just use FP_TO_SINT directly.
6353 const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT);
6354 APFloat APF(APFSem, APInt::getNullValue(SrcVT.getScalarSizeInBits()));
6355 APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits());
6356 if (APFloat::opOverflow &
6357 APF.convertFromAPInt(SignMask, false, APFloat::rmNearestTiesToEven)) {
6358 if (Node->isStrictFPOpcode()) {
6359 Result = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl, { DstVT, MVT::Other },
6360 { Node->getOperand(0), Src });
6361 Chain = Result.getValue(1);
6363 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
6367 SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT);
6370 if (Node->isStrictFPOpcode()) {
6371 Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT,
6372 Node->getOperand(0), /*IsSignaling*/ true);
6373 Chain = Sel.getValue(1);
6375 Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT);
6378 bool Strict = Node->isStrictFPOpcode() ||
6379 shouldUseStrictFP_TO_INT(SrcVT, DstVT, /*IsSigned*/ false);
6382 // Expand based on maximum range of FP_TO_SINT, if the value exceeds the
6383 // signmask then offset (the result of which should be fully representable).
6384 // Sel = Src < 0x8000000000000000
6385 // FltOfs = select Sel, 0, 0x8000000000000000
6386 // IntOfs = select Sel, 0, 0x8000000000000000
6387 // Result = fp_to_sint(Src - FltOfs) ^ IntOfs
6389 // TODO: Should any fast-math-flags be set for the FSUB?
6390 SDValue FltOfs = DAG.getSelect(dl, SrcVT, Sel,
6391 DAG.getConstantFP(0.0, dl, SrcVT), Cst);
6392 Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT);
6393 SDValue IntOfs = DAG.getSelect(dl, DstVT, Sel,
6394 DAG.getConstant(0, dl, DstVT),
6395 DAG.getConstant(SignMask, dl, DstVT));
6397 if (Node->isStrictFPOpcode()) {
6398 SDValue Val = DAG.getNode(ISD::STRICT_FSUB, dl, { SrcVT, MVT::Other },
6399 { Chain, Src, FltOfs });
6400 SInt = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl, { DstVT, MVT::Other },
6401 { Val.getValue(1), Val });
6402 Chain = SInt.getValue(1);
6404 SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs);
6405 SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val);
6407 Result = DAG.getNode(ISD::XOR, dl, DstVT, SInt, IntOfs);
6409 // Expand based on maximum range of FP_TO_SINT:
6410 // True = fp_to_sint(Src)
6411 // False = 0x8000000000000000 + fp_to_sint(Src - 0x8000000000000000)
6412 // Result = select (Src < 0x8000000000000000), True, False
6414 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
6415 // TODO: Should any fast-math-flags be set for the FSUB?
6416 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT,
6417 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst));
6418 False = DAG.getNode(ISD::XOR, dl, DstVT, False,
6419 DAG.getConstant(SignMask, dl, DstVT));
6420 Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT);
6421 Result = DAG.getSelect(dl, DstVT, Sel, True, False);
6426 bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result,
6428 SelectionDAG &DAG) const {
6429 unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0;
6430 SDValue Src = Node->getOperand(OpNo);
6431 EVT SrcVT = Src.getValueType();
6432 EVT DstVT = Node->getValueType(0);
6434 if (SrcVT.getScalarType() != MVT::i64 || DstVT.getScalarType() != MVT::f64)
6437 // Only expand vector types if we have the appropriate vector bit operations.
6438 if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) ||
6439 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6440 !isOperationLegalOrCustom(ISD::FSUB, DstVT) ||
6441 !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
6442 !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
6445 SDLoc dl(SDValue(Node, 0));
6446 EVT ShiftVT = getShiftAmountTy(SrcVT, DAG.getDataLayout());
6448 // Implementation of unsigned i64 to f64 following the algorithm in
6449 // __floatundidf in compiler_rt. This implementation has the advantage
6450 // of performing rounding correctly, both in the default rounding mode
6451 // and in all alternate rounding modes.
6452 SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000), dl, SrcVT);
6453 SDValue TwoP84PlusTwoP52 = DAG.getConstantFP(
6454 BitsToDouble(UINT64_C(0x4530000000100000)), dl, DstVT);
6455 SDValue TwoP84 = DAG.getConstant(UINT64_C(0x4530000000000000), dl, SrcVT);
6456 SDValue LoMask = DAG.getConstant(UINT64_C(0x00000000FFFFFFFF), dl, SrcVT);
6457 SDValue HiShift = DAG.getConstant(32, dl, ShiftVT);
6459 SDValue Lo = DAG.getNode(ISD::AND, dl, SrcVT, Src, LoMask);
6460 SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift);
6461 SDValue LoOr = DAG.getNode(ISD::OR, dl, SrcVT, Lo, TwoP52);
6462 SDValue HiOr = DAG.getNode(ISD::OR, dl, SrcVT, Hi, TwoP84);
6463 SDValue LoFlt = DAG.getBitcast(DstVT, LoOr);
6464 SDValue HiFlt = DAG.getBitcast(DstVT, HiOr);
6465 if (Node->isStrictFPOpcode()) {
6467 DAG.getNode(ISD::STRICT_FSUB, dl, {DstVT, MVT::Other},
6468 {Node->getOperand(0), HiFlt, TwoP84PlusTwoP52});
6469 Result = DAG.getNode(ISD::STRICT_FADD, dl, {DstVT, MVT::Other},
6470 {HiSub.getValue(1), LoFlt, HiSub});
6471 Chain = Result.getValue(1);
6474 DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52);
6475 Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
6480 SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
6481 SelectionDAG &DAG) const {
6483 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
6484 ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
6485 EVT VT = Node->getValueType(0);
6486 if (isOperationLegalOrCustom(NewOp, VT)) {
6487 SDValue Quiet0 = Node->getOperand(0);
6488 SDValue Quiet1 = Node->getOperand(1);
6490 if (!Node->getFlags().hasNoNaNs()) {
6491 // Insert canonicalizes if it's possible we need to quiet to get correct
6493 if (!DAG.isKnownNeverSNaN(Quiet0)) {
6494 Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0,
6497 if (!DAG.isKnownNeverSNaN(Quiet1)) {
6498 Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1,
6503 return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags());
6506 // If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that
6507 // instead if there are no NaNs.
6508 if (Node->getFlags().hasNoNaNs()) {
6509 unsigned IEEE2018Op =
6510 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
6511 if (isOperationLegalOrCustom(IEEE2018Op, VT)) {
6512 return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0),
6513 Node->getOperand(1), Node->getFlags());
6517 // If none of the above worked, but there are no NaNs, then expand to
6518 // a compare/select sequence. This is required for correctness since
6519 // InstCombine might have canonicalized a fcmp+select sequence to a
6520 // FMINNUM/FMAXNUM node. If we were to fall through to the default
6521 // expansion to libcall, we might introduce a link-time dependency
6522 // on libm into a file that originally did not have one.
6523 if (Node->getFlags().hasNoNaNs()) {
6524 ISD::CondCode Pred =
6525 Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
6526 SDValue Op1 = Node->getOperand(0);
6527 SDValue Op2 = Node->getOperand(1);
6528 SDValue SelCC = DAG.getSelectCC(dl, Op1, Op2, Op1, Op2, Pred);
6529 // Copy FMF flags, but always set the no-signed-zeros flag
6530 // as this is implied by the FMINNUM/FMAXNUM semantics.
6531 SDNodeFlags Flags = Node->getFlags();
6532 Flags.setNoSignedZeros(true);
6533 SelCC->setFlags(Flags);
6540 bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result,
6541 SelectionDAG &DAG) const {
6543 EVT VT = Node->getValueType(0);
6544 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
6545 SDValue Op = Node->getOperand(0);
6546 unsigned Len = VT.getScalarSizeInBits();
6547 assert(VT.isInteger() && "CTPOP not implemented for this type.");
6549 // TODO: Add support for irregular type lengths.
6550 if (!(Len <= 128 && Len % 8 == 0))
6553 // Only expand vector types if we have the appropriate vector bit operations.
6554 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) ||
6555 !isOperationLegalOrCustom(ISD::SUB, VT) ||
6556 !isOperationLegalOrCustom(ISD::SRL, VT) ||
6557 (Len != 8 && !isOperationLegalOrCustom(ISD::MUL, VT)) ||
6558 !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
6561 // This is the "best" algorithm from
6562 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
6564 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT);
6566 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT);
6568 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT);
6570 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT);
6572 // v = v - ((v >> 1) & 0x55555555...)
6573 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
6574 DAG.getNode(ISD::AND, dl, VT,
6575 DAG.getNode(ISD::SRL, dl, VT, Op,
6576 DAG.getConstant(1, dl, ShVT)),
6578 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
6579 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
6580 DAG.getNode(ISD::AND, dl, VT,
6581 DAG.getNode(ISD::SRL, dl, VT, Op,
6582 DAG.getConstant(2, dl, ShVT)),
6584 // v = (v + (v >> 4)) & 0x0F0F0F0F...
6585 Op = DAG.getNode(ISD::AND, dl, VT,
6586 DAG.getNode(ISD::ADD, dl, VT, Op,
6587 DAG.getNode(ISD::SRL, dl, VT, Op,
6588 DAG.getConstant(4, dl, ShVT))),
6590 // v = (v * 0x01010101...) >> (Len - 8)
6593 DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
6594 DAG.getConstant(Len - 8, dl, ShVT));
6600 bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
6601 SelectionDAG &DAG) const {
6603 EVT VT = Node->getValueType(0);
6604 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
6605 SDValue Op = Node->getOperand(0);
6606 unsigned NumBitsPerElt = VT.getScalarSizeInBits();
6608 // If the non-ZERO_UNDEF version is supported we can use that instead.
6609 if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
6610 isOperationLegalOrCustom(ISD::CTLZ, VT)) {
6611 Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
6615 // If the ZERO_UNDEF version is supported use that and handle the zero case.
6616 if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
6618 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
6619 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
6620 SDValue Zero = DAG.getConstant(0, dl, VT);
6621 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
6622 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
6623 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
6627 // Only expand vector types if we have the appropriate vector bit operations.
6628 if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
6629 !isOperationLegalOrCustom(ISD::CTPOP, VT) ||
6630 !isOperationLegalOrCustom(ISD::SRL, VT) ||
6631 !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
6634 // for now, we do this:
6635 // x = x | (x >> 1);
6636 // x = x | (x >> 2);
6638 // x = x | (x >>16);
6639 // x = x | (x >>32); // for 64-bit input
6640 // return popcount(~x);
6642 // Ref: "Hacker's Delight" by Henry Warren
6643 for (unsigned i = 0; (1U << i) <= (NumBitsPerElt / 2); ++i) {
6644 SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT);
6645 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6646 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp));
6648 Op = DAG.getNOT(dl, Op, VT);
6649 Result = DAG.getNode(ISD::CTPOP, dl, VT, Op);
6653 bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
6654 SelectionDAG &DAG) const {
6656 EVT VT = Node->getValueType(0);
6657 SDValue Op = Node->getOperand(0);
6658 unsigned NumBitsPerElt = VT.getScalarSizeInBits();
6660 // If the non-ZERO_UNDEF version is supported we can use that instead.
6661 if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
6662 isOperationLegalOrCustom(ISD::CTTZ, VT)) {
6663 Result = DAG.getNode(ISD::CTTZ, dl, VT, Op);
6667 // If the ZERO_UNDEF version is supported use that and handle the zero case.
6668 if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {
6670 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
6671 SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
6672 SDValue Zero = DAG.getConstant(0, dl, VT);
6673 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
6674 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
6675 DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
6679 // Only expand vector types if we have the appropriate vector bit operations.
6680 if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
6681 (!isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6682 !isOperationLegalOrCustom(ISD::CTLZ, VT)) ||
6683 !isOperationLegalOrCustom(ISD::SUB, VT) ||
6684 !isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
6685 !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
6688 // for now, we use: { return popcount(~x & (x - 1)); }
6689 // unless the target has ctlz but not ctpop, in which case we use:
6690 // { return 32 - nlz(~x & (x-1)); }
6691 // Ref: "Hacker's Delight" by Henry Warren
6692 SDValue Tmp = DAG.getNode(
6693 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT),
6694 DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT)));
6696 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6697 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
6699 DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT),
6700 DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
6704 Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
6708 bool TargetLowering::expandABS(SDNode *N, SDValue &Result,
6709 SelectionDAG &DAG) const {
6711 EVT VT = N->getValueType(0);
6712 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
6713 SDValue Op = N->getOperand(0);
6715 // Only expand vector types if we have the appropriate vector operations.
6716 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) ||
6717 !isOperationLegalOrCustom(ISD::ADD, VT) ||
6718 !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
6722 DAG.getNode(ISD::SRA, dl, VT, Op,
6723 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT));
6724 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Op, Shift);
6725 Result = DAG.getNode(ISD::XOR, dl, VT, Add, Shift);
6729 std::pair<SDValue, SDValue>
6730 TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
6731 SelectionDAG &DAG) const {
6733 SDValue Chain = LD->getChain();
6734 SDValue BasePTR = LD->getBasePtr();
6735 EVT SrcVT = LD->getMemoryVT();
6736 EVT DstVT = LD->getValueType(0);
6737 ISD::LoadExtType ExtType = LD->getExtensionType();
6739 unsigned NumElem = SrcVT.getVectorNumElements();
6741 EVT SrcEltVT = SrcVT.getScalarType();
6742 EVT DstEltVT = DstVT.getScalarType();
6744 // A vector must always be stored in memory as-is, i.e. without any padding
6745 // between the elements, since various code depend on it, e.g. in the
6746 // handling of a bitcast of a vector type to int, which may be done with a
6747 // vector store followed by an integer load. A vector that does not have
6748 // elements that are byte-sized must therefore be stored as an integer
6749 // built out of the extracted vector elements.
6750 if (!SrcEltVT.isByteSized()) {
6751 unsigned NumLoadBits = SrcVT.getStoreSizeInBits();
6752 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits);
6754 unsigned NumSrcBits = SrcVT.getSizeInBits();
6755 EVT SrcIntVT = EVT::getIntegerVT(*DAG.getContext(), NumSrcBits);
6757 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
6758 SDValue SrcEltBitMask = DAG.getConstant(
6759 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT);
6761 // Load the whole vector and avoid masking off the top bits as it makes
6762 // the codegen worse.
6764 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR,
6765 LD->getPointerInfo(), SrcIntVT, LD->getAlignment(),
6766 LD->getMemOperand()->getFlags(), LD->getAAInfo());
6768 SmallVector<SDValue, 8> Vals;
6769 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
6770 unsigned ShiftIntoIdx =
6771 (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
6772 SDValue ShiftAmount =
6773 DAG.getShiftAmountConstant(ShiftIntoIdx * SrcEltVT.getSizeInBits(),
6774 LoadVT, SL, /*LegalTypes=*/false);
6775 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount);
6777 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);
6778 SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt);
6780 if (ExtType != ISD::NON_EXTLOAD) {
6781 unsigned ExtendOp = ISD::getExtForLoadExtType(false, ExtType);
6782 Scalar = DAG.getNode(ExtendOp, SL, DstEltVT, Scalar);
6785 Vals.push_back(Scalar);
6788 SDValue Value = DAG.getBuildVector(DstVT, SL, Vals);
6789 return std::make_pair(Value, Load.getValue(1));
6792 unsigned Stride = SrcEltVT.getSizeInBits() / 8;
6793 assert(SrcEltVT.isByteSized());
6795 SmallVector<SDValue, 8> Vals;
6796 SmallVector<SDValue, 8> LoadChains;
6798 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
6799 SDValue ScalarLoad =
6800 DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
6801 LD->getPointerInfo().getWithOffset(Idx * Stride),
6802 SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
6803 LD->getMemOperand()->getFlags(), LD->getAAInfo());
6805 BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, Stride);
6807 Vals.push_back(ScalarLoad.getValue(0));
6808 LoadChains.push_back(ScalarLoad.getValue(1));
6811 SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains);
6812 SDValue Value = DAG.getBuildVector(DstVT, SL, Vals);
6814 return std::make_pair(Value, NewChain);
6817 SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
6818 SelectionDAG &DAG) const {
6821 SDValue Chain = ST->getChain();
6822 SDValue BasePtr = ST->getBasePtr();
6823 SDValue Value = ST->getValue();
6824 EVT StVT = ST->getMemoryVT();
6826 // The type of the data we want to save
6827 EVT RegVT = Value.getValueType();
6828 EVT RegSclVT = RegVT.getScalarType();
6830 // The type of data as saved in memory.
6831 EVT MemSclVT = StVT.getScalarType();
6833 unsigned NumElem = StVT.getVectorNumElements();
6835 // A vector must always be stored in memory as-is, i.e. without any padding
6836 // between the elements, since various code depend on it, e.g. in the
6837 // handling of a bitcast of a vector type to int, which may be done with a
6838 // vector store followed by an integer load. A vector that does not have
6839 // elements that are byte-sized must therefore be stored as an integer
6840 // built out of the extracted vector elements.
6841 if (!MemSclVT.isByteSized()) {
6842 unsigned NumBits = StVT.getSizeInBits();
6843 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
6845 SDValue CurrVal = DAG.getConstant(0, SL, IntVT);
6847 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
6848 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
6849 DAG.getVectorIdxConstant(Idx, SL));
6850 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt);
6851 SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc);
6852 unsigned ShiftIntoIdx =
6853 (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
6854 SDValue ShiftAmount =
6855 DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT);
6856 SDValue ShiftedElt =
6857 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
6858 CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt);
6861 return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
6862 ST->getAlignment(), ST->getMemOperand()->getFlags(),
6866 // Store Stride in bytes
6867 unsigned Stride = MemSclVT.getSizeInBits() / 8;
6868 assert(Stride && "Zero stride!");
6869 // Extract each of the elements from the original vector and save them into
6870 // memory individually.
6871 SmallVector<SDValue, 8> Stores;
6872 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
6873 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
6874 DAG.getVectorIdxConstant(Idx, SL));
6876 SDValue Ptr = DAG.getObjectPtrOffset(SL, BasePtr, Idx * Stride);
6878 // This scalar TruncStore may be illegal, but we legalize it later.
6879 SDValue Store = DAG.getTruncStore(
6880 Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride),
6881 MemSclVT, MinAlign(ST->getAlignment(), Idx * Stride),
6882 ST->getMemOperand()->getFlags(), ST->getAAInfo());
6884 Stores.push_back(Store);
6887 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Stores);
6890 std::pair<SDValue, SDValue>
6891 TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
6892 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
6893 "unaligned indexed loads not implemented!");
6894 SDValue Chain = LD->getChain();
6895 SDValue Ptr = LD->getBasePtr();
6896 EVT VT = LD->getValueType(0);
6897 EVT LoadedVT = LD->getMemoryVT();
6899 auto &MF = DAG.getMachineFunction();
6901 if (VT.isFloatingPoint() || VT.isVector()) {
6902 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
6903 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) {
6904 if (!isOperationLegalOrCustom(ISD::LOAD, intVT) &&
6905 LoadedVT.isVector()) {
6906 // Scalarize the load and let the individual components be handled.
6907 return scalarizeVectorLoad(LD, DAG);
6910 // Expand to a (misaligned) integer load of the same size,
6911 // then bitconvert to floating point or vector.
6912 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
6913 LD->getMemOperand());
6914 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
6916 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
6917 ISD::ANY_EXTEND, dl, VT, Result);
6919 return std::make_pair(Result, newLoad.getValue(1));
6922 // Copy the value to a (aligned) stack slot using (unaligned) integer
6923 // loads and stores, then do a (aligned) load from the stack slot.
6924 MVT RegVT = getRegisterType(*DAG.getContext(), intVT);
6925 unsigned LoadedBytes = LoadedVT.getStoreSize();
6926 unsigned RegBytes = RegVT.getSizeInBits() / 8;
6927 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
6929 // Make sure the stack slot is also aligned for the register type.
6930 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
6931 auto FrameIndex = cast<FrameIndexSDNode>(StackBase.getNode())->getIndex();
6932 SmallVector<SDValue, 8> Stores;
6933 SDValue StackPtr = StackBase;
6934 unsigned Offset = 0;
6936 EVT PtrVT = Ptr.getValueType();
6937 EVT StackPtrVT = StackPtr.getValueType();
6939 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
6940 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
6942 // Do all but one copies using the full register width.
6943 for (unsigned i = 1; i < NumRegs; i++) {
6944 // Load one integer register's worth from the original location.
6945 SDValue Load = DAG.getLoad(
6946 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
6947 MinAlign(LD->getAlignment(), Offset), LD->getMemOperand()->getFlags(),
6949 // Follow the load with a store to the stack slot. Remember the store.
6950 Stores.push_back(DAG.getStore(
6951 Load.getValue(1), dl, Load, StackPtr,
6952 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset)));
6953 // Increment the pointers.
6956 Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
6957 StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
6960 // The last copy may be partial. Do an extending load.
6961 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
6962 8 * (LoadedBytes - Offset));
6964 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
6965 LD->getPointerInfo().getWithOffset(Offset), MemVT,
6966 MinAlign(LD->getAlignment(), Offset),
6967 LD->getMemOperand()->getFlags(), LD->getAAInfo());
6968 // Follow the load with a store to the stack slot. Remember the store.
6969 // On big-endian machines this requires a truncating store to ensure
6970 // that the bits end up in the right place.
6971 Stores.push_back(DAG.getTruncStore(
6972 Load.getValue(1), dl, Load, StackPtr,
6973 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT));
6975 // The order of the stores doesn't matter - say it with a TokenFactor.
6976 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6978 // Finally, perform the original load only redirected to the stack slot.
6979 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
6980 MachinePointerInfo::getFixedStack(MF, FrameIndex, 0),
6983 // Callers expect a MERGE_VALUES node.
6984 return std::make_pair(Load, TF);
6987 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
6988 "Unaligned load of unsupported type.");
6990 // Compute the new VT that is half the size of the old one. This is an
6992 unsigned NumBits = LoadedVT.getSizeInBits();
6994 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
6997 unsigned Alignment = LD->getAlignment();
6998 unsigned IncrementSize = NumBits / 8;
6999 ISD::LoadExtType HiExtType = LD->getExtensionType();
7001 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
7002 if (HiExtType == ISD::NON_EXTLOAD)
7003 HiExtType = ISD::ZEXTLOAD;
7005 // Load the value in two parts
7007 if (DAG.getDataLayout().isLittleEndian()) {
7008 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
7009 NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
7012 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
7013 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
7014 LD->getPointerInfo().getWithOffset(IncrementSize),
7015 NewLoadedVT, MinAlign(Alignment, IncrementSize),
7016 LD->getMemOperand()->getFlags(), LD->getAAInfo());
7018 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
7019 NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
7022 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
7023 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
7024 LD->getPointerInfo().getWithOffset(IncrementSize),
7025 NewLoadedVT, MinAlign(Alignment, IncrementSize),
7026 LD->getMemOperand()->getFlags(), LD->getAAInfo());
7029 // aggregate the two parts
7030 SDValue ShiftAmount =
7031 DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(),
7032 DAG.getDataLayout()));
7033 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
7034 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
7036 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7039 return std::make_pair(Result, TF);
7042 SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
7043 SelectionDAG &DAG) const {
7044 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
7045 "unaligned indexed stores not implemented!");
7046 SDValue Chain = ST->getChain();
7047 SDValue Ptr = ST->getBasePtr();
7048 SDValue Val = ST->getValue();
7049 EVT VT = Val.getValueType();
7050 int Alignment = ST->getAlignment();
7051 auto &MF = DAG.getMachineFunction();
7052 EVT StoreMemVT = ST->getMemoryVT();
7055 if (StoreMemVT.isFloatingPoint() || StoreMemVT.isVector()) {
7056 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7057 if (isTypeLegal(intVT)) {
7058 if (!isOperationLegalOrCustom(ISD::STORE, intVT) &&
7059 StoreMemVT.isVector()) {
7060 // Scalarize the store and let the individual components be handled.
7061 SDValue Result = scalarizeVectorStore(ST, DAG);
7064 // Expand to a bitconvert of the value to the integer type of the
7065 // same size, then a (misaligned) int store.
7066 // FIXME: Does not handle truncating floating point stores!
7067 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
7068 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
7069 Alignment, ST->getMemOperand()->getFlags());
7072 // Do a (aligned) store to a stack slot, then copy from the stack slot
7073 // to the final destination using (unaligned) integer loads and stores.
7074 MVT RegVT = getRegisterType(
7076 EVT::getIntegerVT(*DAG.getContext(), StoreMemVT.getSizeInBits()));
7077 EVT PtrVT = Ptr.getValueType();
7078 unsigned StoredBytes = StoreMemVT.getStoreSize();
7079 unsigned RegBytes = RegVT.getSizeInBits() / 8;
7080 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
7082 // Make sure the stack slot is also aligned for the register type.
7083 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT);
7084 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
7086 // Perform the original store, only redirected to the stack slot.
7087 SDValue Store = DAG.getTruncStore(
7088 Chain, dl, Val, StackPtr,
7089 MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), StoreMemVT);
7091 EVT StackPtrVT = StackPtr.getValueType();
7093 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
7094 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
7095 SmallVector<SDValue, 8> Stores;
7096 unsigned Offset = 0;
7098 // Do all but one copies using the full register width.
7099 for (unsigned i = 1; i < NumRegs; i++) {
7100 // Load one integer register's worth from the stack slot.
7101 SDValue Load = DAG.getLoad(
7102 RegVT, dl, Store, StackPtr,
7103 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset));
7104 // Store it to the final location. Remember the store.
7105 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
7106 ST->getPointerInfo().getWithOffset(Offset),
7107 MinAlign(ST->getAlignment(), Offset),
7108 ST->getMemOperand()->getFlags()));
7109 // Increment the pointers.
7111 StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
7112 Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
7115 // The last store may be partial. Do a truncating store. On big-endian
7116 // machines this requires an extending load from the stack slot to ensure
7117 // that the bits are in the right place.
7119 EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
7121 // Load from the stack slot.
7122 SDValue Load = DAG.getExtLoad(
7123 ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
7124 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), LoadMemVT);
7127 DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
7128 ST->getPointerInfo().getWithOffset(Offset), LoadMemVT,
7129 MinAlign(ST->getAlignment(), Offset),
7130 ST->getMemOperand()->getFlags(), ST->getAAInfo()));
7131 // The order of the stores doesn't matter - say it with a TokenFactor.
7132 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7136 assert(StoreMemVT.isInteger() && !StoreMemVT.isVector() &&
7137 "Unaligned store of unknown type.");
7138 // Get the half-size VT
7139 EVT NewStoredVT = StoreMemVT.getHalfSizedIntegerVT(*DAG.getContext());
7140 int NumBits = NewStoredVT.getSizeInBits();
7141 int IncrementSize = NumBits / 8;
7143 // Divide the stored value in two parts.
7144 SDValue ShiftAmount = DAG.getConstant(
7145 NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout()));
7147 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
7149 // Store the two parts
7150 SDValue Store1, Store2;
7151 Store1 = DAG.getTruncStore(Chain, dl,
7152 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
7153 Ptr, ST->getPointerInfo(), NewStoredVT, Alignment,
7154 ST->getMemOperand()->getFlags());
7156 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
7157 Alignment = MinAlign(Alignment, IncrementSize);
7158 Store2 = DAG.getTruncStore(
7159 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
7160 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment,
7161 ST->getMemOperand()->getFlags(), ST->getAAInfo());
7164 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
7169 TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask,
7170 const SDLoc &DL, EVT DataVT,
7172 bool IsCompressedMemory) const {
7174 EVT AddrVT = Addr.getValueType();
7175 EVT MaskVT = Mask.getValueType();
7176 assert(DataVT.getVectorNumElements() == MaskVT.getVectorNumElements() &&
7177 "Incompatible types of Data and Mask");
7178 if (IsCompressedMemory) {
7179 // Incrementing the pointer according to number of '1's in the mask.
7180 EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits());
7181 SDValue MaskInIntReg = DAG.getBitcast(MaskIntVT, Mask);
7182 if (MaskIntVT.getSizeInBits() < 32) {
7183 MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg);
7184 MaskIntVT = MVT::i32;
7187 // Count '1's with POPCNT.
7188 Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg);
7189 Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT);
7190 // Scale is an element size in bytes.
7191 SDValue Scale = DAG.getConstant(DataVT.getScalarSizeInBits() / 8, DL,
7193 Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale);
7195 Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT);
7197 return DAG.getNode(ISD::ADD, DL, AddrVT, Addr, Increment);
7200 static SDValue clampDynamicVectorIndex(SelectionDAG &DAG,
7204 if (isa<ConstantSDNode>(Idx))
7207 EVT IdxVT = Idx.getValueType();
7208 unsigned NElts = VecVT.getVectorNumElements();
7209 if (isPowerOf2_32(NElts)) {
7210 APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(),
7212 return DAG.getNode(ISD::AND, dl, IdxVT, Idx,
7213 DAG.getConstant(Imm, dl, IdxVT));
7216 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx,
7217 DAG.getConstant(NElts - 1, dl, IdxVT));
7220 SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG,
7221 SDValue VecPtr, EVT VecVT,
7222 SDValue Index) const {
7224 // Make sure the index type is big enough to compute in.
7225 Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType());
7227 EVT EltVT = VecVT.getVectorElementType();
7229 // Calculate the element offset and add it to the pointer.
7230 unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
7231 assert(EltSize * 8 == EltVT.getSizeInBits() &&
7232 "Converting bits to bytes lost precision");
7234 Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl);
7236 EVT IdxVT = Index.getValueType();
7238 Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index,
7239 DAG.getConstant(EltSize, dl, IdxVT));
7240 return DAG.getMemBasePlusOffset(VecPtr, Index, dl);
7243 //===----------------------------------------------------------------------===//
7244 // Implementation of Emulated TLS Model
7245 //===----------------------------------------------------------------------===//
7247 SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
7248 SelectionDAG &DAG) const {
7249 // Access to address of TLS varialbe xyz is lowered to a function call:
7250 // __emutls_get_address( address of global variable named "__emutls_v.xyz" )
7251 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7252 PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext());
7257 std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str();
7258 Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent());
7259 StringRef EmuTlsVarName(NameString);
7260 GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName);
7261 assert(EmuTlsVar && "Cannot find EmuTlsVar ");
7262 Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT);
7263 Entry.Ty = VoidPtrType;
7264 Args.push_back(Entry);
7266 SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT);
7268 TargetLowering::CallLoweringInfo CLI(DAG);
7269 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode());
7270 CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args));
7271 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
7273 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7274 // At last for X86 targets, maybe good for other targets too?
7275 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
7276 MFI.setAdjustsStack(true); // Is this only for X86 target?
7277 MFI.setHasCalls(true);
7279 assert((GA->getOffset() == 0) &&
7280 "Emulated TLS must have zero offset in GlobalAddressSDNode");
7281 return CallResult.first;
7284 SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
7285 SelectionDAG &DAG) const {
7286 assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
7289 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
7292 if (C->isNullValue() && CC == ISD::SETEQ) {
7293 EVT VT = Op.getOperand(0).getValueType();
7294 SDValue Zext = Op.getOperand(0);
7295 if (VT.bitsLT(MVT::i32)) {
7297 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
7299 unsigned Log2b = Log2_32(VT.getSizeInBits());
7300 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
7301 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
7302 DAG.getConstant(Log2b, dl, MVT::i32));
7303 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
7309 SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
7310 unsigned Opcode = Node->getOpcode();
7311 SDValue LHS = Node->getOperand(0);
7312 SDValue RHS = Node->getOperand(1);
7313 EVT VT = LHS.getValueType();
7316 assert(VT == RHS.getValueType() && "Expected operands to be the same type");
7317 assert(VT.isInteger() && "Expected operands to be integers");
7319 // usub.sat(a, b) -> umax(a, b) - b
7320 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
7321 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
7322 return DAG.getNode(ISD::SUB, dl, VT, Max, RHS);
7325 if (Opcode == ISD::UADDSAT && isOperationLegalOrCustom(ISD::UMIN, VT)) {
7326 SDValue InvRHS = DAG.getNOT(dl, RHS, VT);
7327 SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS);
7328 return DAG.getNode(ISD::ADD, dl, VT, Min, RHS);
7331 unsigned OverflowOp;
7334 OverflowOp = ISD::SADDO;
7337 OverflowOp = ISD::UADDO;
7340 OverflowOp = ISD::SSUBO;
7343 OverflowOp = ISD::USUBO;
7346 llvm_unreachable("Expected method to receive signed or unsigned saturation "
7347 "addition or subtraction node.");
7350 unsigned BitWidth = LHS.getScalarValueSizeInBits();
7351 EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
7352 SDValue Result = DAG.getNode(OverflowOp, dl, DAG.getVTList(VT, BoolVT),
7354 SDValue SumDiff = Result.getValue(0);
7355 SDValue Overflow = Result.getValue(1);
7356 SDValue Zero = DAG.getConstant(0, dl, VT);
7357 SDValue AllOnes = DAG.getAllOnesConstant(dl, VT);
7359 if (Opcode == ISD::UADDSAT) {
7360 if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) {
7361 // (LHS + RHS) | OverflowMask
7362 SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT);
7363 return DAG.getNode(ISD::OR, dl, VT, SumDiff, OverflowMask);
7365 // Overflow ? 0xffff.... : (LHS + RHS)
7366 return DAG.getSelect(dl, VT, Overflow, AllOnes, SumDiff);
7367 } else if (Opcode == ISD::USUBSAT) {
7368 if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) {
7369 // (LHS - RHS) & ~OverflowMask
7370 SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT);
7371 SDValue Not = DAG.getNOT(dl, OverflowMask, VT);
7372 return DAG.getNode(ISD::AND, dl, VT, SumDiff, Not);
7374 // Overflow ? 0 : (LHS - RHS)
7375 return DAG.getSelect(dl, VT, Overflow, Zero, SumDiff);
7377 // SatMax -> Overflow && SumDiff < 0
7378 // SatMin -> Overflow && SumDiff >= 0
7379 APInt MinVal = APInt::getSignedMinValue(BitWidth);
7380 APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
7381 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
7382 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
7383 SDValue SumNeg = DAG.getSetCC(dl, BoolVT, SumDiff, Zero, ISD::SETLT);
7384 Result = DAG.getSelect(dl, VT, SumNeg, SatMax, SatMin);
7385 return DAG.getSelect(dl, VT, Overflow, Result, SumDiff);
7390 TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
7391 assert((Node->getOpcode() == ISD::SMULFIX ||
7392 Node->getOpcode() == ISD::UMULFIX ||
7393 Node->getOpcode() == ISD::SMULFIXSAT ||
7394 Node->getOpcode() == ISD::UMULFIXSAT) &&
7395 "Expected a fixed point multiplication opcode");
7398 SDValue LHS = Node->getOperand(0);
7399 SDValue RHS = Node->getOperand(1);
7400 EVT VT = LHS.getValueType();
7401 unsigned Scale = Node->getConstantOperandVal(2);
7402 bool Saturating = (Node->getOpcode() == ISD::SMULFIXSAT ||
7403 Node->getOpcode() == ISD::UMULFIXSAT);
7404 bool Signed = (Node->getOpcode() == ISD::SMULFIX ||
7405 Node->getOpcode() == ISD::SMULFIXSAT);
7406 EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
7407 unsigned VTSize = VT.getScalarSizeInBits();
7410 // [us]mul.fix(a, b, 0) -> mul(a, b)
7412 if (isOperationLegalOrCustom(ISD::MUL, VT))
7413 return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
7414 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) {
7416 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
7417 SDValue Product = Result.getValue(0);
7418 SDValue Overflow = Result.getValue(1);
7419 SDValue Zero = DAG.getConstant(0, dl, VT);
7421 APInt MinVal = APInt::getSignedMinValue(VTSize);
7422 APInt MaxVal = APInt::getSignedMaxValue(VTSize);
7423 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
7424 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
7425 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
7426 Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin);
7427 return DAG.getSelect(dl, VT, Overflow, Result, Product);
7428 } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) {
7430 DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
7431 SDValue Product = Result.getValue(0);
7432 SDValue Overflow = Result.getValue(1);
7434 APInt MaxVal = APInt::getMaxValue(VTSize);
7435 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
7436 return DAG.getSelect(dl, VT, Overflow, SatMax, Product);
7440 assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) &&
7441 "Expected scale to be less than the number of bits if signed or at "
7442 "most the number of bits if unsigned.");
7443 assert(LHS.getValueType() == RHS.getValueType() &&
7444 "Expected both operands to be the same type");
7446 // Get the upper and lower bits of the result.
7448 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
7449 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
7450 if (isOperationLegalOrCustom(LoHiOp, VT)) {
7451 SDValue Result = DAG.getNode(LoHiOp, dl, DAG.getVTList(VT, VT), LHS, RHS);
7452 Lo = Result.getValue(0);
7453 Hi = Result.getValue(1);
7454 } else if (isOperationLegalOrCustom(HiOp, VT)) {
7455 Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
7456 Hi = DAG.getNode(HiOp, dl, VT, LHS, RHS);
7457 } else if (VT.isVector()) {
7460 report_fatal_error("Unable to expand fixed point multiplication.");
7463 if (Scale == VTSize)
7464 // Result is just the top half since we'd be shifting by the width of the
7465 // operand. Overflow impossible so this works for both UMULFIX and
7469 // The result will need to be shifted right by the scale since both operands
7470 // are scaled. The result is given to us in 2 halves, so we only want part of
7471 // both in the result.
7472 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
7473 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo,
7474 DAG.getConstant(Scale, dl, ShiftTy));
7479 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of the
7480 // widened multiplication) aren't all zeroes.
7482 // Saturate to max if ((Hi >> Scale) != 0),
7483 // which is the same as if (Hi > ((1 << Scale) - 1))
7484 APInt MaxVal = APInt::getMaxValue(VTSize);
7485 SDValue LowMask = DAG.getConstant(APInt::getLowBitsSet(VTSize, Scale),
7487 Result = DAG.getSelectCC(dl, Hi, LowMask,
7488 DAG.getConstant(MaxVal, dl, VT), Result,
7494 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of the
7495 // widened multiplication) aren't all ones or all zeroes.
7497 SDValue SatMin = DAG.getConstant(APInt::getSignedMinValue(VTSize), dl, VT);
7498 SDValue SatMax = DAG.getConstant(APInt::getSignedMaxValue(VTSize), dl, VT);
7501 SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo,
7502 DAG.getConstant(VTSize - 1, dl, ShiftTy));
7503 SDValue Overflow = DAG.getSetCC(dl, BoolVT, Hi, Sign, ISD::SETNE);
7504 // Saturated to SatMin if wide product is negative, and SatMax if wide
7505 // product is positive ...
7506 SDValue Zero = DAG.getConstant(0, dl, VT);
7507 SDValue ResultIfOverflow = DAG.getSelectCC(dl, Hi, Zero, SatMin, SatMax,
7509 // ... but only if we overflowed.
7510 return DAG.getSelect(dl, VT, Overflow, ResultIfOverflow, Result);
7513 // We handled Scale==0 above so all the bits to examine is in Hi.
7515 // Saturate to max if ((Hi >> (Scale - 1)) > 0),
7516 // which is the same as if (Hi > (1 << (Scale - 1)) - 1)
7517 SDValue LowMask = DAG.getConstant(APInt::getLowBitsSet(VTSize, Scale - 1),
7519 Result = DAG.getSelectCC(dl, Hi, LowMask, SatMax, Result, ISD::SETGT);
7520 // Saturate to min if (Hi >> (Scale - 1)) < -1),
7521 // which is the same as if (HI < (-1 << (Scale - 1))
7523 DAG.getConstant(APInt::getHighBitsSet(VTSize, VTSize - Scale + 1),
7525 Result = DAG.getSelectCC(dl, Hi, HighMask, SatMin, Result, ISD::SETLT);
7530 TargetLowering::expandFixedPointDiv(unsigned Opcode, const SDLoc &dl,
7531 SDValue LHS, SDValue RHS,
7532 unsigned Scale, SelectionDAG &DAG) const {
7533 assert((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT ||
7534 Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) &&
7535 "Expected a fixed point division opcode");
7537 EVT VT = LHS.getValueType();
7538 bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT;
7539 bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT;
7540 EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
7542 // If there is enough room in the type to upscale the LHS or downscale the
7543 // RHS before the division, we can perform it in this type without having to
7544 // resize. For signed operations, the LHS headroom is the number of
7545 // redundant sign bits, and for unsigned ones it is the number of zeroes.
7546 // The headroom for the RHS is the number of trailing zeroes.
7547 unsigned LHSLead = Signed ? DAG.ComputeNumSignBits(LHS) - 1
7548 : DAG.computeKnownBits(LHS).countMinLeadingZeros();
7549 unsigned RHSTrail = DAG.computeKnownBits(RHS).countMinTrailingZeros();
7551 // For signed saturating operations, we need to be able to detect true integer
7552 // division overflow; that is, when you have MIN / -EPS. However, this
7553 // is undefined behavior and if we emit divisions that could take such
7554 // values it may cause undesired behavior (arithmetic exceptions on x86, for
7556 // Avoid this by requiring an extra bit so that we never get this case.
7557 // FIXME: This is a bit unfortunate as it means that for an 8-bit 7-scale
7558 // signed saturating division, we need to emit a whopping 32-bit division.
7559 if (LHSLead + RHSTrail < Scale + (unsigned)(Saturating && Signed))
7562 unsigned LHSShift = std::min(LHSLead, Scale);
7563 unsigned RHSShift = Scale - LHSShift;
7565 // At this point, we know that if we shift the LHS up by LHSShift and the
7566 // RHS down by RHSShift, we can emit a regular division with a final scaling
7569 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
7571 LHS = DAG.getNode(ISD::SHL, dl, VT, LHS,
7572 DAG.getConstant(LHSShift, dl, ShiftTy));
7574 RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS,
7575 DAG.getConstant(RHSShift, dl, ShiftTy));
7579 // For signed operations, if the resulting quotient is negative and the
7580 // remainder is nonzero, subtract 1 from the quotient to round towards
7581 // negative infinity.
7583 // FIXME: Ideally we would always produce an SDIVREM here, but if the
7584 // type isn't legal, SDIVREM cannot be expanded. There is no reason why
7585 // we couldn't just form a libcall, but the type legalizer doesn't do it.
7586 if (isTypeLegal(VT) &&
7587 isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
7588 Quot = DAG.getNode(ISD::SDIVREM, dl,
7589 DAG.getVTList(VT, VT),
7591 Rem = Quot.getValue(1);
7592 Quot = Quot.getValue(0);
7594 Quot = DAG.getNode(ISD::SDIV, dl, VT,
7596 Rem = DAG.getNode(ISD::SREM, dl, VT,
7599 SDValue Zero = DAG.getConstant(0, dl, VT);
7600 SDValue RemNonZero = DAG.getSetCC(dl, BoolVT, Rem, Zero, ISD::SETNE);
7601 SDValue LHSNeg = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETLT);
7602 SDValue RHSNeg = DAG.getSetCC(dl, BoolVT, RHS, Zero, ISD::SETLT);
7603 SDValue QuotNeg = DAG.getNode(ISD::XOR, dl, BoolVT, LHSNeg, RHSNeg);
7604 SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot,
7605 DAG.getConstant(1, dl, VT));
7606 Quot = DAG.getSelect(dl, VT,
7607 DAG.getNode(ISD::AND, dl, BoolVT, RemNonZero, QuotNeg),
7610 Quot = DAG.getNode(ISD::UDIV, dl, VT,
7616 void TargetLowering::expandUADDSUBO(
7617 SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const {
7619 SDValue LHS = Node->getOperand(0);
7620 SDValue RHS = Node->getOperand(1);
7621 bool IsAdd = Node->getOpcode() == ISD::UADDO;
7623 // If ADD/SUBCARRY is legal, use that instead.
7624 unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
7625 if (isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {
7626 SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1));
7627 SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(),
7628 { LHS, RHS, CarryIn });
7629 Result = SDValue(NodeCarry.getNode(), 0);
7630 Overflow = SDValue(NodeCarry.getNode(), 1);
7634 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
7635 LHS.getValueType(), LHS, RHS);
7637 EVT ResultType = Node->getValueType(1);
7638 EVT SetCCType = getSetCCResultType(
7639 DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0));
7640 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
7641 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC);
7642 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType);
7645 void TargetLowering::expandSADDSUBO(
7646 SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const {
7648 SDValue LHS = Node->getOperand(0);
7649 SDValue RHS = Node->getOperand(1);
7650 bool IsAdd = Node->getOpcode() == ISD::SADDO;
7652 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
7653 LHS.getValueType(), LHS, RHS);
7655 EVT ResultType = Node->getValueType(1);
7656 EVT OType = getSetCCResultType(
7657 DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0));
7659 // If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
7660 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT;
7661 if (isOperationLegalOrCustom(OpcSat, LHS.getValueType())) {
7662 SDValue Sat = DAG.getNode(OpcSat, dl, LHS.getValueType(), LHS, RHS);
7663 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE);
7664 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType);
7668 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
7670 // For an addition, the result should be less than one of the operands (LHS)
7671 // if and only if the other operand (RHS) is negative, otherwise there will
7673 // For a subtraction, the result should be less than one of the operands
7674 // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
7675 // otherwise there will be overflow.
7676 SDValue ResultLowerThanLHS = DAG.getSetCC(dl, OType, Result, LHS, ISD::SETLT);
7677 SDValue ConditionRHS =
7678 DAG.getSetCC(dl, OType, RHS, Zero, IsAdd ? ISD::SETLT : ISD::SETGT);
7680 Overflow = DAG.getBoolExtOrTrunc(
7681 DAG.getNode(ISD::XOR, dl, OType, ConditionRHS, ResultLowerThanLHS), dl,
7682 ResultType, ResultType);
7685 bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result,
7686 SDValue &Overflow, SelectionDAG &DAG) const {
7688 EVT VT = Node->getValueType(0);
7689 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
7690 SDValue LHS = Node->getOperand(0);
7691 SDValue RHS = Node->getOperand(1);
7692 bool isSigned = Node->getOpcode() == ISD::SMULO;
7694 // For power-of-two multiplications we can use a simpler shift expansion.
7695 if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) {
7696 const APInt &C = RHSC->getAPIntValue();
7697 // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X }
7698 if (C.isPowerOf2()) {
7699 // smulo(x, signed_min) is same as umulo(x, signed_min).
7700 bool UseArithShift = isSigned && !C.isMinSignedValue();
7701 EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout());
7702 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy);
7703 Result = DAG.getNode(ISD::SHL, dl, VT, LHS, ShiftAmt);
7704 Overflow = DAG.getSetCC(dl, SetCCVT,
7705 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
7706 dl, VT, Result, ShiftAmt),
7712 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
7714 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
7715 VT.getVectorNumElements());
7719 static const unsigned Ops[2][3] =
7720 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
7721 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
7722 if (isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
7723 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
7724 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
7725 } else if (isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
7726 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
7728 TopHalf = BottomHalf.getValue(1);
7729 } else if (isTypeLegal(WideVT)) {
7730 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
7731 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
7732 SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
7733 BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Mul);
7734 SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits(), dl,
7735 getShiftAmountTy(WideVT, DAG.getDataLayout()));
7736 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT,
7737 DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt));
7742 // We can fall back to a libcall with an illegal type for the MUL if we
7743 // have a libcall big enough.
7744 // Also, we can fall back to a division in some cases, but that's a big
7745 // performance hit in the general case.
7746 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7747 if (WideVT == MVT::i16)
7748 LC = RTLIB::MUL_I16;
7749 else if (WideVT == MVT::i32)
7750 LC = RTLIB::MUL_I32;
7751 else if (WideVT == MVT::i64)
7752 LC = RTLIB::MUL_I64;
7753 else if (WideVT == MVT::i128)
7754 LC = RTLIB::MUL_I128;
7755 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
7760 // The high part is obtained by SRA'ing all but one of the bits of low
7762 unsigned LoSize = VT.getSizeInBits();
7764 DAG.getNode(ISD::SRA, dl, VT, LHS,
7765 DAG.getConstant(LoSize - 1, dl,
7766 getPointerTy(DAG.getDataLayout())));
7768 DAG.getNode(ISD::SRA, dl, VT, RHS,
7769 DAG.getConstant(LoSize - 1, dl,
7770 getPointerTy(DAG.getDataLayout())));
7772 HiLHS = DAG.getConstant(0, dl, VT);
7773 HiRHS = DAG.getConstant(0, dl, VT);
7776 // Here we're passing the 2 arguments explicitly as 4 arguments that are
7777 // pre-lowered to the correct types. This all depends upon WideVT not
7778 // being a legal type for the architecture and thus has to be split to
7781 TargetLowering::MakeLibCallOptions CallOptions;
7782 CallOptions.setSExt(isSigned);
7783 CallOptions.setIsPostTypeLegalization(true);
7784 if (shouldSplitFunctionArgumentsAsLittleEndian(DAG.getDataLayout())) {
7785 // Halves of WideVT are packed into registers in different order
7786 // depending on platform endianness. This is usually handled by
7787 // the C calling convention, but we can't defer to it in
7789 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
7790 Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first;
7792 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
7793 Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first;
7795 assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
7796 "Ret value is a collection of constituent nodes holding result.");
7797 if (DAG.getDataLayout().isLittleEndian()) {
7799 BottomHalf = Ret.getOperand(0);
7800 TopHalf = Ret.getOperand(1);
7802 BottomHalf = Ret.getOperand(1);
7803 TopHalf = Ret.getOperand(0);
7807 Result = BottomHalf;
7809 SDValue ShiftAmt = DAG.getConstant(
7810 VT.getScalarSizeInBits() - 1, dl,
7811 getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
7812 SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
7813 Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, Sign, ISD::SETNE);
7815 Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf,
7816 DAG.getConstant(0, dl, VT), ISD::SETNE);
7819 // Truncate the result if SetCC returns a larger type than needed.
7820 EVT RType = Node->getValueType(1);
7821 if (RType.getSizeInBits() < Overflow.getValueSizeInBits())
7822 Overflow = DAG.getNode(ISD::TRUNCATE, dl, RType, Overflow);
7824 assert(RType.getSizeInBits() == Overflow.getValueSizeInBits() &&
7825 "Unexpected result type for S/UMULO legalization");
7829 SDValue TargetLowering::expandVecReduce(SDNode *Node, SelectionDAG &DAG) const {
7831 bool NoNaN = Node->getFlags().hasNoNaNs();
7832 unsigned BaseOpcode = 0;
7833 switch (Node->getOpcode()) {
7834 default: llvm_unreachable("Expected VECREDUCE opcode");
7835 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
7836 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break;
7837 case ISD::VECREDUCE_ADD: BaseOpcode = ISD::ADD; break;
7838 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break;
7839 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
7840 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break;
7841 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break;
7842 case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break;
7843 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;
7844 case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break;
7845 case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;
7846 case ISD::VECREDUCE_FMAX:
7847 BaseOpcode = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
7849 case ISD::VECREDUCE_FMIN:
7850 BaseOpcode = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
7854 SDValue Op = Node->getOperand(0);
7855 EVT VT = Op.getValueType();
7857 // Try to use a shuffle reduction for power of two vectors.
7858 if (VT.isPow2VectorType()) {
7859 while (VT.getVectorNumElements() > 1) {
7860 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
7861 if (!isOperationLegalOrCustom(BaseOpcode, HalfVT))
7865 std::tie(Lo, Hi) = DAG.SplitVector(Op, dl);
7866 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi);
7871 EVT EltVT = VT.getVectorElementType();
7872 unsigned NumElts = VT.getVectorNumElements();
7874 SmallVector<SDValue, 8> Ops;
7875 DAG.ExtractVectorElements(Op, Ops, 0, NumElts);
7877 SDValue Res = Ops[0];
7878 for (unsigned i = 1; i < NumElts; i++)
7879 Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Node->getFlags());
7881 // Result type may be wider than element type.
7882 if (EltVT != Node->getValueType(0))
7883 Res = DAG.getNode(ISD::ANY_EXTEND, dl, Node->getValueType(0), Res);
7887 bool TargetLowering::expandREM(SDNode *Node, SDValue &Result,
7888 SelectionDAG &DAG) const {
7889 EVT VT = Node->getValueType(0);
7891 bool isSigned = Node->getOpcode() == ISD::SREM;
7892 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
7893 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
7894 SDValue Dividend = Node->getOperand(0);
7895 SDValue Divisor = Node->getOperand(1);
7896 if (isOperationLegalOrCustom(DivRemOpc, VT)) {
7897 SDVTList VTs = DAG.getVTList(VT, VT);
7898 Result = DAG.getNode(DivRemOpc, dl, VTs, Dividend, Divisor).getValue(1);
7900 } else if (isOperationLegalOrCustom(DivOpc, VT)) {
7902 SDValue Divide = DAG.getNode(DivOpc, dl, VT, Dividend, Divisor);
7903 SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Divide, Divisor);
7904 Result = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);