1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// \file This file describes the general parts of a Subtarget.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/TargetSubtargetInfo.h"
17 TargetSubtargetInfo::TargetSubtargetInfo(
18 const Triple &TT, StringRef CPU, StringRef FS,
19 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
20 const MCWriteProcResEntry *WPR,
21 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
22 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
23 : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
26 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
28 bool TargetSubtargetInfo::enableAtomicExpand() const {
32 bool TargetSubtargetInfo::enableIndirectBrExpand() const {
36 bool TargetSubtargetInfo::enableMachineScheduler() const {
40 bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
41 return enableMachineScheduler();
44 bool TargetSubtargetInfo::enableRALocalReassignment(
45 CodeGenOpt::Level OptLevel) const {
49 bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
53 bool TargetSubtargetInfo::enablePostRAScheduler() const {
54 return getSchedModel().PostRAScheduler;
57 bool TargetSubtargetInfo::useAA() const {
61 void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }