1 //===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the TwoAddress instruction pass which is used
10 // by most register allocators. Two-Address instructions are rewritten
20 // Note that if a register allocator chooses to use this pass, that it
21 // has to be capable of handling the non-SSA nature of these rewritten
24 // It is also worth noting that the duplicate operand of the two
25 // address instruction is removed.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/iterator_range.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/LiveInterval.h"
37 #include "llvm/CodeGen/LiveIntervals.h"
38 #include "llvm/CodeGen/LiveVariables.h"
39 #include "llvm/CodeGen/MachineBasicBlock.h"
40 #include "llvm/CodeGen/MachineFunction.h"
41 #include "llvm/CodeGen/MachineFunctionPass.h"
42 #include "llvm/CodeGen/MachineInstr.h"
43 #include "llvm/CodeGen/MachineInstrBuilder.h"
44 #include "llvm/CodeGen/MachineOperand.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/CodeGen/SlotIndexes.h"
48 #include "llvm/CodeGen/TargetInstrInfo.h"
49 #include "llvm/CodeGen/TargetOpcodes.h"
50 #include "llvm/CodeGen/TargetRegisterInfo.h"
51 #include "llvm/CodeGen/TargetSubtargetInfo.h"
52 #include "llvm/MC/MCInstrDesc.h"
53 #include "llvm/MC/MCInstrItineraries.h"
54 #include "llvm/Pass.h"
55 #include "llvm/Support/CodeGen.h"
56 #include "llvm/Support/CommandLine.h"
57 #include "llvm/Support/Debug.h"
58 #include "llvm/Support/ErrorHandling.h"
59 #include "llvm/Support/raw_ostream.h"
60 #include "llvm/Target/TargetMachine.h"
67 #define DEBUG_TYPE "twoaddressinstruction"
69 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
70 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
71 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
72 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
73 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
74 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
76 // Temporary flag to disable rescheduling.
78 EnableRescheduling("twoaddr-reschedule",
79 cl::desc("Coalesce copies by rescheduling (default=true)"),
80 cl::init(true), cl::Hidden);
82 // Limit the number of dataflow edges to traverse when evaluating the benefit
83 // of commuting operands.
84 static cl::opt<unsigned> MaxDataFlowEdge(
85 "dataflow-edge-limit", cl::Hidden, cl::init(3),
86 cl::desc("Maximum number of dataflow edges to traverse when evaluating "
87 "the benefit of commuting operands"));
91 class TwoAddressInstructionPass : public MachineFunctionPass {
93 const TargetInstrInfo *TII;
94 const TargetRegisterInfo *TRI;
95 const InstrItineraryData *InstrItins;
96 MachineRegisterInfo *MRI;
100 CodeGenOpt::Level OptLevel;
102 // The current basic block being processed.
103 MachineBasicBlock *MBB;
105 // Keep track the distance of a MI from the start of the current basic block.
106 DenseMap<MachineInstr*, unsigned> DistanceMap;
108 // Set of already processed instructions in the current block.
109 SmallPtrSet<MachineInstr*, 8> Processed;
111 // A map from virtual registers to physical registers which are likely targets
112 // to be coalesced to due to copies from physical registers to virtual
113 // registers. e.g. v1024 = move r0.
114 DenseMap<unsigned, unsigned> SrcRegMap;
116 // A map from virtual registers to physical registers which are likely targets
117 // to be coalesced to due to copies to physical registers from virtual
118 // registers. e.g. r1 = move v1024.
119 DenseMap<unsigned, unsigned> DstRegMap;
121 bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
123 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
125 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
126 MachineInstr *MI, unsigned Dist);
128 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
129 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
131 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
133 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
134 MachineBasicBlock::iterator &nmi,
135 unsigned RegA, unsigned RegB, unsigned Dist);
137 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
139 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
140 MachineBasicBlock::iterator &nmi,
142 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
143 MachineBasicBlock::iterator &nmi,
146 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
147 MachineBasicBlock::iterator &nmi,
148 unsigned SrcIdx, unsigned DstIdx,
149 unsigned Dist, bool shouldOnlyCommute);
151 bool tryInstructionCommute(MachineInstr *MI,
156 void scanUses(unsigned DstReg);
158 void processCopy(MachineInstr *MI);
160 using TiedPairList = SmallVector<std::pair<unsigned, unsigned>, 4>;
161 using TiedOperandMap = SmallDenseMap<unsigned, TiedPairList>;
163 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
164 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
165 void eliminateRegSequence(MachineBasicBlock::iterator&);
168 static char ID; // Pass identification, replacement for typeid
170 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
171 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
174 void getAnalysisUsage(AnalysisUsage &AU) const override {
175 AU.setPreservesCFG();
176 AU.addUsedIfAvailable<AAResultsWrapperPass>();
177 AU.addUsedIfAvailable<LiveVariables>();
178 AU.addPreserved<LiveVariables>();
179 AU.addPreserved<SlotIndexes>();
180 AU.addPreserved<LiveIntervals>();
181 AU.addPreservedID(MachineLoopInfoID);
182 AU.addPreservedID(MachineDominatorsID);
183 MachineFunctionPass::getAnalysisUsage(AU);
186 /// Pass entry point.
187 bool runOnMachineFunction(MachineFunction&) override;
190 } // end anonymous namespace
192 char TwoAddressInstructionPass::ID = 0;
194 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
196 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE,
197 "Two-Address instruction pass", false, false)
198 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
199 INITIALIZE_PASS_END(TwoAddressInstructionPass, DEBUG_TYPE,
200 "Two-Address instruction pass", false, false)
202 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
204 /// Return the MachineInstr* if it is the single def of the Reg in current BB.
205 static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
206 const MachineRegisterInfo *MRI) {
207 MachineInstr *Ret = nullptr;
208 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
209 if (DefMI.getParent() != BB || DefMI.isDebugValue())
213 else if (Ret != &DefMI)
219 /// Check if there is a reversed copy chain from FromReg to ToReg:
220 /// %Tmp1 = copy %Tmp2;
221 /// %FromReg = copy %Tmp1;
222 /// %ToReg = add %FromReg ...
223 /// %Tmp2 = copy %ToReg;
224 /// MaxLen specifies the maximum length of the copy chain the func
225 /// can walk through.
226 bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
228 unsigned TmpReg = FromReg;
229 for (int i = 0; i < Maxlen; i++) {
230 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
231 if (!Def || !Def->isCopy())
234 TmpReg = Def->getOperand(1).getReg();
242 /// Return true if there are no intervening uses between the last instruction
243 /// in the MBB that defines the specified register and the two-address
244 /// instruction which is being processed. It also returns the last def location
246 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
249 unsigned LastUse = Dist;
250 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
251 MachineInstr *MI = MO.getParent();
252 if (MI->getParent() != MBB || MI->isDebugValue())
254 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
255 if (DI == DistanceMap.end())
257 if (MO.isUse() && DI->second < LastUse)
258 LastUse = DI->second;
259 if (MO.isDef() && DI->second > LastDef)
260 LastDef = DI->second;
263 return !(LastUse > LastDef && LastUse < Dist);
266 /// Return true if the specified MI is a copy instruction or an extract_subreg
267 /// instruction. It also returns the source and destination registers and
268 /// whether they are physical registers by reference.
269 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
270 unsigned &SrcReg, unsigned &DstReg,
271 bool &IsSrcPhys, bool &IsDstPhys) {
275 DstReg = MI.getOperand(0).getReg();
276 SrcReg = MI.getOperand(1).getReg();
277 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
278 DstReg = MI.getOperand(0).getReg();
279 SrcReg = MI.getOperand(2).getReg();
283 IsSrcPhys = Register::isPhysicalRegister(SrcReg);
284 IsDstPhys = Register::isPhysicalRegister(DstReg);
288 /// Test if the given register value, which is used by the
289 /// given instruction, is killed by the given instruction.
290 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
291 LiveIntervals *LIS) {
292 if (LIS && Register::isVirtualRegister(Reg) && !LIS->isNotInMIMap(*MI)) {
293 // FIXME: Sometimes tryInstructionTransform() will add instructions and
294 // test whether they can be folded before keeping them. In this case it
295 // sets a kill before recursively calling tryInstructionTransform() again.
296 // If there is no interval available, we assume that this instruction is
297 // one of those. A kill flag is manually inserted on the operand so the
298 // check below will handle it.
299 LiveInterval &LI = LIS->getInterval(Reg);
300 // This is to match the kill flag version where undefs don't have kill
302 if (!LI.hasAtLeastOneValue())
305 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
306 LiveInterval::const_iterator I = LI.find(useIdx);
307 assert(I != LI.end() && "Reg must be live-in to use.");
308 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
311 return MI->killsRegister(Reg);
314 /// Test if the given register value, which is used by the given
315 /// instruction, is killed by the given instruction. This looks through
316 /// coalescable copies to see if the original value is potentially not killed.
318 /// For example, in this code:
320 /// %reg1034 = copy %reg1024
321 /// %reg1035 = copy killed %reg1025
322 /// %reg1036 = add killed %reg1034, killed %reg1035
324 /// %reg1034 is not considered to be killed, since it is copied from a
325 /// register which is not killed. Treating it as not killed lets the
326 /// normal heuristics commute the (two-address) add, which lets
327 /// coalescing eliminate the extra copy.
329 /// If allowFalsePositives is true then likely kills are treated as kills even
330 /// if it can't be proven that they are kills.
331 static bool isKilled(MachineInstr &MI, unsigned Reg,
332 const MachineRegisterInfo *MRI,
333 const TargetInstrInfo *TII,
335 bool allowFalsePositives) {
336 MachineInstr *DefMI = &MI;
338 // All uses of physical registers are likely to be kills.
339 if (Register::isPhysicalRegister(Reg) &&
340 (allowFalsePositives || MRI->hasOneUse(Reg)))
342 if (!isPlainlyKilled(DefMI, Reg, LIS))
344 if (Register::isPhysicalRegister(Reg))
346 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
347 // If there are multiple defs, we can't do a simple analysis, so just
348 // go with what the kill flag says.
349 if (std::next(Begin) != MRI->def_end())
351 DefMI = Begin->getParent();
352 bool IsSrcPhys, IsDstPhys;
353 unsigned SrcReg, DstReg;
354 // If the def is something other than a copy, then it isn't going to
355 // be coalesced, so follow the kill flag.
356 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
362 /// Return true if the specified MI uses the specified register as a two-address
363 /// use. If so, return the destination register by reference.
364 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
365 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
366 const MachineOperand &MO = MI.getOperand(i);
367 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
370 if (MI.isRegTiedToDefOperand(i, &ti)) {
371 DstReg = MI.getOperand(ti).getReg();
378 /// Given a register, if has a single in-basic block use, return the use
379 /// instruction if it's a copy or a two-address use.
381 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
382 MachineRegisterInfo *MRI,
383 const TargetInstrInfo *TII,
385 unsigned &DstReg, bool &IsDstPhys) {
386 if (!MRI->hasOneNonDBGUse(Reg))
387 // None or more than one use.
389 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
390 if (UseMI.getParent() != MBB)
394 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
399 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
400 IsDstPhys = Register::isPhysicalRegister(DstReg);
406 /// Return the physical register the specified virtual register might be mapped
409 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
410 while (Register::isVirtualRegister(Reg)) {
411 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
412 if (SI == RegMap.end())
416 if (Register::isPhysicalRegister(Reg))
421 /// Return true if the two registers are equal or aliased.
423 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
428 return TRI->regsOverlap(RegA, RegB);
431 // Returns true if Reg is equal or aliased to at least one register in Set.
432 static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg,
433 const TargetRegisterInfo *TRI) {
434 for (unsigned R : Set)
435 if (TRI->regsOverlap(R, Reg))
441 /// Return true if it's potentially profitable to commute the two-address
442 /// instruction that's being processed.
444 TwoAddressInstructionPass::
445 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
446 MachineInstr *MI, unsigned Dist) {
447 if (OptLevel == CodeGenOpt::None)
450 // Determine if it's profitable to commute this two address instruction. In
451 // general, we want no uses between this instruction and the definition of
452 // the two-address register.
454 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
455 // %reg1029 = COPY %reg1028
456 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
457 // insert => %reg1030 = COPY %reg1028
458 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
459 // In this case, it might not be possible to coalesce the second COPY
460 // instruction if the first one is coalesced. So it would be profitable to
462 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
463 // %reg1029 = COPY %reg1028
464 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
465 // insert => %reg1030 = COPY %reg1029
466 // %reg1030 = ADD8rr killed %reg1029, killed %reg1028, implicit dead %eflags
468 if (!isPlainlyKilled(MI, regC, LIS))
471 // Ok, we have something like:
472 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
473 // let's see if it's worth commuting it.
475 // Look for situations like this:
478 // %reg1026 = ADD %reg1024, %reg1025
480 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
481 unsigned ToRegA = getMappedReg(regA, DstRegMap);
483 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
484 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
485 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
486 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
488 // Compute if any of the following are true:
489 // -RegB is not tied to a register and RegC is compatible with RegA.
490 // -RegB is tied to the wrong physical register, but RegC is.
491 // -RegB is tied to the wrong physical register, and RegC isn't tied.
492 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
494 // Don't compute if any of the following are true:
495 // -RegC is not tied to a register and RegB is compatible with RegA.
496 // -RegC is tied to the wrong physical register, but RegB is.
497 // -RegC is tied to the wrong physical register, and RegB isn't tied.
498 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
502 // If there is a use of regC between its last def (could be livein) and this
503 // instruction, then bail.
504 unsigned LastDefC = 0;
505 if (!noUseAfterLastDef(regC, Dist, LastDefC))
508 // If there is a use of regB between its last def (could be livein) and this
509 // instruction, then go ahead and make this transformation.
510 unsigned LastDefB = 0;
511 if (!noUseAfterLastDef(regB, Dist, LastDefB))
514 // Look for situation like this:
515 // %reg101 = MOV %reg100
517 // %reg103 = ADD %reg102, %reg101
519 // %reg100 = MOV %reg103
520 // If there is a reversed copy chain from reg101 to reg103, commute the ADD
521 // to eliminate an otherwise unavoidable copy.
523 // We can extend the logic further: If an pair of operands in an insn has
524 // been merged, the insn could be regarded as a virtual copy, and the virtual
525 // copy could also be used to construct a copy chain.
526 // To more generally minimize register copies, ideally the logic of two addr
527 // instruction pass should be integrated with register allocation pass where
528 // interference graph is available.
529 if (isRevCopyChain(regC, regA, MaxDataFlowEdge))
532 if (isRevCopyChain(regB, regA, MaxDataFlowEdge))
535 // Since there are no intervening uses for both registers, then commute
536 // if the def of regC is closer. Its live interval is shorter.
537 return LastDefB && LastDefC && LastDefC > LastDefB;
540 /// Commute a two-address instruction and update the basic block, distance map,
541 /// and live variables if needed. Return true if it is successful.
542 bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
547 Register RegC = MI->getOperand(RegCIdx).getReg();
548 LLVM_DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
549 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
551 if (NewMI == nullptr) {
552 LLVM_DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
556 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
557 assert(NewMI == MI &&
558 "TargetInstrInfo::commuteInstruction() should not return a new "
559 "instruction unless it was requested.");
561 // Update source register map.
562 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
564 Register RegA = MI->getOperand(DstIdx).getReg();
565 SrcRegMap[RegA] = FromRegC;
571 /// Return true if it is profitable to convert the given 2-address instruction
572 /// to a 3-address one.
574 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
575 // Look for situations like this:
578 // %reg1026 = ADD %reg1024, %reg1025
580 // Turn ADD into a 3-address instruction to avoid a copy.
581 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
584 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
585 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
588 /// Convert the specified two-address instruction into a three address one.
589 /// Return true if this transformation was successful.
591 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
592 MachineBasicBlock::iterator &nmi,
593 unsigned RegA, unsigned RegB,
595 // FIXME: Why does convertToThreeAddress() need an iterator reference?
596 MachineFunction::iterator MFI = MBB->getIterator();
597 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
598 assert(MBB->getIterator() == MFI &&
599 "convertToThreeAddress changed iterator reference");
603 LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
604 LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
607 LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
609 MBB->erase(mi); // Nuke the old inst.
611 DistanceMap.insert(std::make_pair(NewMI, Dist));
615 // Update source and destination register maps.
616 SrcRegMap.erase(RegA);
617 DstRegMap.erase(RegB);
621 /// Scan forward recursively for only uses, update maps if the use is a copy or
622 /// a two-address instruction.
624 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
625 SmallVector<unsigned, 4> VirtRegPairs;
629 unsigned Reg = DstReg;
630 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
631 NewReg, IsDstPhys)) {
632 if (IsCopy && !Processed.insert(UseMI).second)
635 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
636 if (DI != DistanceMap.end())
637 // Earlier in the same MBB.Reached via a back edge.
641 VirtRegPairs.push_back(NewReg);
644 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
646 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
647 VirtRegPairs.push_back(NewReg);
651 if (!VirtRegPairs.empty()) {
652 unsigned ToReg = VirtRegPairs.back();
653 VirtRegPairs.pop_back();
654 while (!VirtRegPairs.empty()) {
655 unsigned FromReg = VirtRegPairs.back();
656 VirtRegPairs.pop_back();
657 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
659 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
662 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
664 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
668 /// If the specified instruction is not yet processed, process it if it's a
669 /// copy. For a copy instruction, we find the physical registers the
670 /// source and destination registers might be mapped to. These are kept in
671 /// point-to maps used to determine future optimizations. e.g.
674 /// v1026 = add v1024, v1025
676 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
677 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
678 /// potentially joined with r1 on the output side. It's worthwhile to commute
679 /// 'add' to eliminate a copy.
680 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
681 if (Processed.count(MI))
684 bool IsSrcPhys, IsDstPhys;
685 unsigned SrcReg, DstReg;
686 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
689 if (IsDstPhys && !IsSrcPhys)
690 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
691 else if (!IsDstPhys && IsSrcPhys) {
692 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
694 assert(SrcRegMap[DstReg] == SrcReg &&
695 "Can't map to two src physical registers!");
700 Processed.insert(MI);
703 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
704 /// consider moving the instruction below the kill instruction in order to
705 /// eliminate the need for the copy.
706 bool TwoAddressInstructionPass::
707 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
708 MachineBasicBlock::iterator &nmi,
710 // Bail immediately if we don't have LV or LIS available. We use them to find
711 // kills efficiently.
715 MachineInstr *MI = &*mi;
716 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
717 if (DI == DistanceMap.end())
718 // Must be created from unfolded load. Don't waste time trying this.
721 MachineInstr *KillMI = nullptr;
723 LiveInterval &LI = LIS->getInterval(Reg);
724 assert(LI.end() != LI.begin() &&
725 "Reg should not have empty live interval.");
727 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
728 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
729 if (I != LI.end() && I->start < MBBEndIdx)
733 KillMI = LIS->getInstructionFromIndex(I->end);
735 KillMI = LV->getVarInfo(Reg).findKill(MBB);
737 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
738 // Don't mess with copies, they may be coalesced later.
741 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
742 KillMI->isBranch() || KillMI->isTerminator())
743 // Don't move pass calls, etc.
747 if (isTwoAddrUse(*KillMI, Reg, DstReg))
750 bool SeenStore = true;
751 if (!MI->isSafeToMove(AA, SeenStore))
754 if (TII->getInstrLatency(InstrItins, *MI) > 1)
755 // FIXME: Needs more sophisticated heuristics.
758 SmallVector<unsigned, 2> Uses;
759 SmallVector<unsigned, 2> Kills;
760 SmallVector<unsigned, 2> Defs;
761 for (const MachineOperand &MO : MI->operands()) {
764 Register MOReg = MO.getReg();
768 Defs.push_back(MOReg);
770 Uses.push_back(MOReg);
771 if (MOReg != Reg && (MO.isKill() ||
772 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
773 Kills.push_back(MOReg);
777 // Move the copies connected to MI down as well.
778 MachineBasicBlock::iterator Begin = MI;
779 MachineBasicBlock::iterator AfterMI = std::next(Begin);
780 MachineBasicBlock::iterator End = AfterMI;
781 while (End != MBB->end()) {
782 End = skipDebugInstructionsForward(End, MBB->end());
783 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI))
784 Defs.push_back(End->getOperand(0).getReg());
790 // Check if the reschedule will not break dependencies.
791 unsigned NumVisited = 0;
792 MachineBasicBlock::iterator KillPos = KillMI;
794 for (MachineInstr &OtherMI : make_range(End, KillPos)) {
795 // Debug instructions cannot be counted against the limit.
796 if (OtherMI.isDebugInstr())
798 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
801 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
802 OtherMI.isBranch() || OtherMI.isTerminator())
803 // Don't move pass calls, etc.
805 for (const MachineOperand &MO : OtherMI.operands()) {
808 Register MOReg = MO.getReg();
812 if (regOverlapsSet(Uses, MOReg, TRI))
813 // Physical register use would be clobbered.
815 if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
816 // May clobber a physical register def.
817 // FIXME: This may be too conservative. It's ok if the instruction
818 // is sunken completely below the use.
821 if (regOverlapsSet(Defs, MOReg, TRI))
824 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
825 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
826 regOverlapsSet(Kills, MOReg, TRI)))
827 // Don't want to extend other live ranges and update kills.
829 if (MOReg == Reg && !isKill)
830 // We can't schedule across a use of the register in question.
832 // Ensure that if this is register in question, its the kill we expect.
833 assert((MOReg != Reg || &OtherMI == KillMI) &&
834 "Found multiple kills of a register in a basic block");
839 // Move debug info as well.
840 while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr())
844 MachineBasicBlock::iterator InsertPos = KillPos;
846 // We have to move the copies first so that the MBB is still well-formed
847 // when calling handleMove().
848 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
849 auto CopyMI = MBBI++;
850 MBB->splice(InsertPos, MBB, CopyMI);
851 LIS->handleMove(*CopyMI);
854 End = std::next(MachineBasicBlock::iterator(MI));
857 // Copies following MI may have been moved as well.
858 MBB->splice(InsertPos, MBB, Begin, End);
859 DistanceMap.erase(DI);
861 // Update live variables
863 LIS->handleMove(*MI);
865 LV->removeVirtualRegisterKilled(Reg, *KillMI);
866 LV->addVirtualRegisterKilled(Reg, *MI);
869 LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
873 /// Return true if the re-scheduling will put the given instruction too close
874 /// to the defs of its register dependencies.
875 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
877 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
878 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
881 return true; // MI is defining something KillMI uses
882 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
883 if (DDI == DistanceMap.end())
884 return true; // Below MI
885 unsigned DefDist = DDI->second;
886 assert(Dist > DefDist && "Visited def already?");
887 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
893 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
894 /// consider moving the kill instruction above the current two-address
895 /// instruction in order to eliminate the need for the copy.
896 bool TwoAddressInstructionPass::
897 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
898 MachineBasicBlock::iterator &nmi,
900 // Bail immediately if we don't have LV or LIS available. We use them to find
901 // kills efficiently.
905 MachineInstr *MI = &*mi;
906 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
907 if (DI == DistanceMap.end())
908 // Must be created from unfolded load. Don't waste time trying this.
911 MachineInstr *KillMI = nullptr;
913 LiveInterval &LI = LIS->getInterval(Reg);
914 assert(LI.end() != LI.begin() &&
915 "Reg should not have empty live interval.");
917 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
918 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
919 if (I != LI.end() && I->start < MBBEndIdx)
923 KillMI = LIS->getInstructionFromIndex(I->end);
925 KillMI = LV->getVarInfo(Reg).findKill(MBB);
927 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
928 // Don't mess with copies, they may be coalesced later.
932 if (isTwoAddrUse(*KillMI, Reg, DstReg))
935 bool SeenStore = true;
936 if (!KillMI->isSafeToMove(AA, SeenStore))
939 SmallSet<unsigned, 2> Uses;
940 SmallSet<unsigned, 2> Kills;
941 SmallSet<unsigned, 2> Defs;
942 SmallSet<unsigned, 2> LiveDefs;
943 for (const MachineOperand &MO : KillMI->operands()) {
946 Register MOReg = MO.getReg();
950 if (isDefTooClose(MOReg, DI->second, MI))
952 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
953 if (MOReg == Reg && !isKill)
956 if (isKill && MOReg != Reg)
958 } else if (Register::isPhysicalRegister(MOReg)) {
961 LiveDefs.insert(MOReg);
965 // Check if the reschedule will not break depedencies.
966 unsigned NumVisited = 0;
967 for (MachineInstr &OtherMI :
968 make_range(mi, MachineBasicBlock::iterator(KillMI))) {
969 // Debug instructions cannot be counted against the limit.
970 if (OtherMI.isDebugInstr())
972 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
975 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
976 OtherMI.isBranch() || OtherMI.isTerminator())
977 // Don't move pass calls, etc.
979 SmallVector<unsigned, 2> OtherDefs;
980 for (const MachineOperand &MO : OtherMI.operands()) {
983 Register MOReg = MO.getReg();
987 if (Defs.count(MOReg))
988 // Moving KillMI can clobber the physical register if the def has
991 if (Kills.count(MOReg))
992 // Don't want to extend other live ranges and update kills.
994 if (&OtherMI != MI && MOReg == Reg &&
995 !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
996 // We can't schedule across a use of the register in question.
999 OtherDefs.push_back(MOReg);
1003 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1004 unsigned MOReg = OtherDefs[i];
1005 if (Uses.count(MOReg))
1007 if (Register::isPhysicalRegister(MOReg) && LiveDefs.count(MOReg))
1009 // Physical register def is seen.
1014 // Move the old kill above MI, don't forget to move debug info as well.
1015 MachineBasicBlock::iterator InsertPos = mi;
1016 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr())
1018 MachineBasicBlock::iterator From = KillMI;
1019 MachineBasicBlock::iterator To = std::next(From);
1020 while (std::prev(From)->isDebugInstr())
1022 MBB->splice(InsertPos, MBB, From, To);
1024 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
1025 DistanceMap.erase(DI);
1027 // Update live variables
1029 LIS->handleMove(*KillMI);
1031 LV->removeVirtualRegisterKilled(Reg, *KillMI);
1032 LV->addVirtualRegisterKilled(Reg, *MI);
1035 LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1039 /// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1040 /// given machine instruction to improve opportunities for coalescing and
1041 /// elimination of a register to register copy.
1043 /// 'DstOpIdx' specifies the index of MI def operand.
1044 /// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1045 /// operand is killed by the given instruction.
1046 /// The 'Dist' arguments provides the distance of MI from the start of the
1047 /// current basic block and it is used to determine if it is profitable
1048 /// to commute operands in the instruction.
1050 /// Returns true if the transformation happened. Otherwise, returns false.
1051 bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
1056 if (!MI->isCommutable())
1059 bool MadeChange = false;
1060 Register DstOpReg = MI->getOperand(DstOpIdx).getReg();
1061 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1062 unsigned OpsNum = MI->getDesc().getNumOperands();
1063 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1064 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1065 // The call of findCommutedOpIndices below only checks if BaseOpIdx
1066 // and OtherOpIdx are commutable, it does not really search for
1067 // other commutable operands and does not change the values of passed
1069 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
1070 !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
1073 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1074 bool AggressiveCommute = false;
1076 // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1077 // operands. This makes the live ranges of DstOp and OtherOp joinable.
1078 bool OtherOpKilled = isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
1079 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1082 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
1084 AggressiveCommute = true;
1087 // If it's profitable to commute, try to do so.
1088 if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1092 if (AggressiveCommute)
1095 // There might be more than two commutable operands, update BaseOp and
1096 // continue scanning.
1097 // FIXME: This assumes that the new instruction's operands are in the
1098 // same positions and were simply swapped.
1099 BaseOpReg = OtherOpReg;
1100 BaseOpKilled = OtherOpKilled;
1101 // Resamples OpsNum in case the number of operands was reduced. This
1102 // happens with X86.
1103 OpsNum = MI->getDesc().getNumOperands();
1109 /// For the case where an instruction has a single pair of tied register
1110 /// operands, attempt some transformations that may either eliminate the tied
1111 /// operands or improve the opportunities for coalescing away the register copy.
1112 /// Returns true if no copy needs to be inserted to untie mi's operands
1113 /// (either because they were untied, or because mi was rescheduled, and will
1114 /// be visited again later). If the shouldOnlyCommute flag is true, only
1115 /// instruction commutation is attempted.
1116 bool TwoAddressInstructionPass::
1117 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1118 MachineBasicBlock::iterator &nmi,
1119 unsigned SrcIdx, unsigned DstIdx,
1120 unsigned Dist, bool shouldOnlyCommute) {
1121 if (OptLevel == CodeGenOpt::None)
1124 MachineInstr &MI = *mi;
1125 Register regA = MI.getOperand(DstIdx).getReg();
1126 Register regB = MI.getOperand(SrcIdx).getReg();
1128 assert(Register::isVirtualRegister(regB) &&
1129 "cannot make instruction into two-address form");
1130 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1132 if (Register::isVirtualRegister(regA))
1135 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
1137 // If the instruction is convertible to 3 Addr, instead
1138 // of returning try 3 Addr transformation aggressively and
1139 // use this variable to check later. Because it might be better.
1140 // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1141 // instead of the following code.
1145 if (Commuted && !MI.isConvertibleTo3Addr())
1148 if (shouldOnlyCommute)
1151 // If there is one more use of regB later in the same MBB, consider
1152 // re-schedule this MI below it.
1153 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1158 // If we commuted, regB may have changed so we should re-sample it to avoid
1159 // confusing the three address conversion below.
1161 regB = MI.getOperand(SrcIdx).getReg();
1162 regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1165 if (MI.isConvertibleTo3Addr()) {
1166 // This instruction is potentially convertible to a true
1167 // three-address instruction. Check if it is profitable.
1168 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1169 // Try to convert it.
1170 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1171 ++NumConvertedTo3Addr;
1172 return true; // Done with this instruction.
1177 // Return if it is commuted but 3 addr conversion is failed.
1181 // If there is one more use of regB later in the same MBB, consider
1182 // re-schedule it before this MI if it's legal.
1183 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1188 // If this is an instruction with a load folded into it, try unfolding
1189 // the load, e.g. avoid this:
1191 // addq (%rax), %rcx
1192 // in favor of this:
1193 // movq (%rax), %rcx
1195 // because it's preferable to schedule a load than a register copy.
1196 if (MI.mayLoad() && !regBKilled) {
1197 // Determine if a load can be unfolded.
1198 unsigned LoadRegIndex;
1200 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1201 /*UnfoldLoad=*/true,
1202 /*UnfoldStore=*/false,
1205 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1206 if (UnfoldMCID.getNumDefs() == 1) {
1208 LLVM_DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1209 const TargetRegisterClass *RC =
1210 TRI->getAllocatableClass(
1211 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1212 Register Reg = MRI->createVirtualRegister(RC);
1213 SmallVector<MachineInstr *, 2> NewMIs;
1214 if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
1215 /*UnfoldLoad=*/true,
1216 /*UnfoldStore=*/false, NewMIs)) {
1217 LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1220 assert(NewMIs.size() == 2 &&
1221 "Unfolded a load into multiple instructions!");
1222 // The load was previously folded, so this is the only use.
1223 NewMIs[1]->addRegisterKilled(Reg, TRI);
1225 // Tentatively insert the instructions into the block so that they
1226 // look "normal" to the transformation logic.
1227 MBB->insert(mi, NewMIs[0]);
1228 MBB->insert(mi, NewMIs[1]);
1230 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1231 << "2addr: NEW INST: " << *NewMIs[1]);
1233 // Transform the instruction, now that it no longer has a load.
1234 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1235 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1236 MachineBasicBlock::iterator NewMI = NewMIs[1];
1237 bool TransformResult =
1238 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1239 (void)TransformResult;
1240 assert(!TransformResult &&
1241 "tryInstructionTransform() should return false.");
1242 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1243 // Success, or at least we made an improvement. Keep the unfolded
1244 // instructions and discard the original.
1246 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1247 MachineOperand &MO = MI.getOperand(i);
1248 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1251 if (NewMIs[0]->killsRegister(MO.getReg()))
1252 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
1254 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1255 "Kill missing after load unfold!");
1256 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
1259 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
1260 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1261 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
1263 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1264 "Dead flag missing after load unfold!");
1265 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
1270 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
1273 SmallVector<Register, 4> OrigRegs;
1275 for (const MachineOperand &MO : MI.operands()) {
1277 OrigRegs.push_back(MO.getReg());
1281 MI.eraseFromParent();
1283 // Update LiveIntervals.
1285 MachineBasicBlock::iterator Begin(NewMIs[0]);
1286 MachineBasicBlock::iterator End(NewMIs[1]);
1287 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1292 // Transforming didn't eliminate the tie and didn't lead to an
1293 // improvement. Clean up the unfolded instructions and keep the
1295 LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1296 NewMIs[0]->eraseFromParent();
1297 NewMIs[1]->eraseFromParent();
1306 // Collect tied operands of MI that need to be handled.
1307 // Rewrite trivial cases immediately.
1308 // Return true if any tied operands where found, including the trivial ones.
1309 bool TwoAddressInstructionPass::
1310 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1311 const MCInstrDesc &MCID = MI->getDesc();
1312 bool AnyOps = false;
1313 unsigned NumOps = MI->getNumOperands();
1315 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1316 unsigned DstIdx = 0;
1317 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1320 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1321 MachineOperand &DstMO = MI->getOperand(DstIdx);
1322 Register SrcReg = SrcMO.getReg();
1323 Register DstReg = DstMO.getReg();
1324 // Tied constraint already satisfied?
1325 if (SrcReg == DstReg)
1328 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1330 // Deal with undef uses immediately - simply rewrite the src operand.
1331 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1332 // Constrain the DstReg register class if required.
1333 if (Register::isVirtualRegister(DstReg))
1334 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1336 MRI->constrainRegClass(DstReg, RC);
1337 SrcMO.setReg(DstReg);
1339 LLVM_DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1342 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1347 // Process a list of tied MI operands that all use the same source register.
1348 // The tied pairs are of the form (SrcIdx, DstIdx).
1350 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1351 TiedPairList &TiedPairs,
1353 bool IsEarlyClobber = false;
1354 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1355 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1356 IsEarlyClobber |= DstMO.isEarlyClobber();
1359 bool RemovedKillFlag = false;
1360 bool AllUsesCopied = true;
1361 unsigned LastCopiedReg = 0;
1362 SlotIndex LastCopyIdx;
1364 unsigned SubRegB = 0;
1365 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1366 unsigned SrcIdx = TiedPairs[tpi].first;
1367 unsigned DstIdx = TiedPairs[tpi].second;
1369 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1370 Register RegA = DstMO.getReg();
1372 // Grab RegB from the instruction because it may have changed if the
1373 // instruction was commuted.
1374 RegB = MI->getOperand(SrcIdx).getReg();
1375 SubRegB = MI->getOperand(SrcIdx).getSubReg();
1378 // The register is tied to multiple destinations (or else we would
1379 // not have continued this far), but this use of the register
1380 // already matches the tied destination. Leave it.
1381 AllUsesCopied = false;
1384 LastCopiedReg = RegA;
1386 assert(Register::isVirtualRegister(RegB) &&
1387 "cannot make instruction into two-address form");
1390 // First, verify that we don't have a use of "a" in the instruction
1391 // (a = b + a for example) because our transformation will not
1392 // work. This should never occur because we are in SSA form.
1393 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1394 assert(i == DstIdx ||
1395 !MI->getOperand(i).isReg() ||
1396 MI->getOperand(i).getReg() != RegA);
1400 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1401 TII->get(TargetOpcode::COPY), RegA);
1402 // If this operand is folding a truncation, the truncation now moves to the
1403 // copy so that the register classes remain valid for the operands.
1404 MIB.addReg(RegB, 0, SubRegB);
1405 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1407 if (Register::isVirtualRegister(RegA)) {
1408 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1410 "tied subregister must be a truncation");
1411 // The superreg class will not be used to constrain the subreg class.
1414 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1415 && "tied subregister must be a truncation");
1419 // Update DistanceMap.
1420 MachineBasicBlock::iterator PrevMI = MI;
1422 DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
1423 DistanceMap[MI] = ++Dist;
1426 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
1428 if (Register::isVirtualRegister(RegA)) {
1429 LiveInterval &LI = LIS->getInterval(RegA);
1430 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1432 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
1433 LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1437 LLVM_DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1439 MachineOperand &MO = MI->getOperand(SrcIdx);
1440 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1441 "inconsistent operand info for 2-reg pass");
1443 MO.setIsKill(false);
1444 RemovedKillFlag = true;
1447 // Make sure regA is a legal regclass for the SrcIdx operand.
1448 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
1449 MRI->constrainRegClass(RegA, RC);
1451 // The getMatchingSuper asserts guarantee that the register class projected
1452 // by SubRegB is compatible with RegA with no subregister. So regardless of
1453 // whether the dest oper writes a subreg, the source oper should not.
1456 // Propagate SrcRegMap.
1457 SrcRegMap[RegA] = RegB;
1460 if (AllUsesCopied) {
1461 bool ReplacedAllUntiedUses = true;
1462 if (!IsEarlyClobber) {
1463 // Replace other (un-tied) uses of regB with LastCopiedReg.
1464 for (MachineOperand &MO : MI->operands()) {
1465 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1466 if (MO.getSubReg() == SubRegB) {
1468 MO.setIsKill(false);
1469 RemovedKillFlag = true;
1471 MO.setReg(LastCopiedReg);
1474 ReplacedAllUntiedUses = false;
1480 // Update live variables for regB.
1481 if (RemovedKillFlag && ReplacedAllUntiedUses &&
1482 LV && LV->getVarInfo(RegB).removeKill(*MI)) {
1483 MachineBasicBlock::iterator PrevMI = MI;
1485 LV->addVirtualRegisterKilled(RegB, *PrevMI);
1488 // Update LiveIntervals.
1490 LiveInterval &LI = LIS->getInterval(RegB);
1491 SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
1492 LiveInterval::const_iterator I = LI.find(MIIdx);
1493 assert(I != LI.end() && "RegB must be live-in to use.");
1495 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1496 if (I->end == UseIdx)
1497 LI.removeSegment(LastCopyIdx, UseIdx);
1499 } else if (RemovedKillFlag) {
1500 // Some tied uses of regB matched their destination registers, so
1501 // regB is still used in this instruction, but a kill flag was
1502 // removed from a different tied use of regB, so now we need to add
1503 // a kill flag to one of the remaining uses of regB.
1504 for (MachineOperand &MO : MI->operands()) {
1505 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1513 /// Reduce two-address instructions to two operands.
1514 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1516 const TargetMachine &TM = MF->getTarget();
1517 MRI = &MF->getRegInfo();
1518 TII = MF->getSubtarget().getInstrInfo();
1519 TRI = MF->getSubtarget().getRegisterInfo();
1520 InstrItins = MF->getSubtarget().getInstrItineraryData();
1521 LV = getAnalysisIfAvailable<LiveVariables>();
1522 LIS = getAnalysisIfAvailable<LiveIntervals>();
1523 if (auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
1524 AA = &AAPass->getAAResults();
1527 OptLevel = TM.getOptLevel();
1528 // Disable optimizations if requested. We cannot skip the whole pass as some
1529 // fixups are necessary for correctness.
1530 if (skipFunction(Func.getFunction()))
1531 OptLevel = CodeGenOpt::None;
1533 bool MadeChange = false;
1535 LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1536 LLVM_DEBUG(dbgs() << "********** Function: " << MF->getName() << '\n');
1538 // This pass takes the function out of SSA form.
1541 // This pass will rewrite the tied-def to meet the RegConstraint.
1543 .set(MachineFunctionProperties::Property::TiedOpsRewritten);
1545 TiedOperandMap TiedOperands;
1546 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1547 MBBI != MBBE; ++MBBI) {
1550 DistanceMap.clear();
1554 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1556 MachineBasicBlock::iterator nmi = std::next(mi);
1557 // Skip debug instructions.
1558 if (mi->isDebugInstr()) {
1563 // Expand REG_SEQUENCE instructions. This will position mi at the first
1564 // expanded instruction.
1565 if (mi->isRegSequence())
1566 eliminateRegSequence(mi);
1568 DistanceMap.insert(std::make_pair(&*mi, ++Dist));
1572 // First scan through all the tied register uses in this instruction
1573 // and record a list of pairs of tied operands for each register.
1574 if (!collectTiedOperands(&*mi, TiedOperands)) {
1579 ++NumTwoAddressInstrs;
1581 LLVM_DEBUG(dbgs() << '\t' << *mi);
1583 // If the instruction has a single pair of tied operands, try some
1584 // transformations that may either eliminate the tied operands or
1585 // improve the opportunities for coalescing away the register copy.
1586 if (TiedOperands.size() == 1) {
1587 SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
1588 = TiedOperands.begin()->second;
1589 if (TiedPairs.size() == 1) {
1590 unsigned SrcIdx = TiedPairs[0].first;
1591 unsigned DstIdx = TiedPairs[0].second;
1592 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1593 Register DstReg = mi->getOperand(DstIdx).getReg();
1594 if (SrcReg != DstReg &&
1595 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1596 // The tied operands have been eliminated or shifted further down
1597 // the block to ease elimination. Continue processing with 'nmi'.
1598 TiedOperands.clear();
1605 // Now iterate over the information collected above.
1606 for (auto &TO : TiedOperands) {
1607 processTiedPairs(&*mi, TO.second, Dist);
1608 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1611 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1612 if (mi->isInsertSubreg()) {
1613 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1614 // To %reg:subidx = COPY %subreg
1615 unsigned SubIdx = mi->getOperand(3).getImm();
1616 mi->RemoveOperand(3);
1617 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1618 mi->getOperand(0).setSubReg(SubIdx);
1619 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1620 mi->RemoveOperand(1);
1621 mi->setDesc(TII->get(TargetOpcode::COPY));
1622 LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1625 // Clear TiedOperands here instead of at the top of the loop
1626 // since most instructions do not have tied operands.
1627 TiedOperands.clear();
1633 MF->verify(this, "After two-address instruction pass");
1638 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1640 /// The instruction is turned into a sequence of sub-register copies:
1642 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1646 /// undef %dst:ssub0 = COPY %v1
1647 /// %dst:ssub1 = COPY %v2
1648 void TwoAddressInstructionPass::
1649 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1650 MachineInstr &MI = *MBBI;
1651 Register DstReg = MI.getOperand(0).getReg();
1652 if (MI.getOperand(0).getSubReg() || Register::isPhysicalRegister(DstReg) ||
1653 !(MI.getNumOperands() & 1)) {
1654 LLVM_DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
1655 llvm_unreachable(nullptr);
1658 SmallVector<Register, 4> OrigRegs;
1660 OrigRegs.push_back(MI.getOperand(0).getReg());
1661 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
1662 OrigRegs.push_back(MI.getOperand(i).getReg());
1665 bool DefEmitted = false;
1666 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
1667 MachineOperand &UseMO = MI.getOperand(i);
1668 Register SrcReg = UseMO.getReg();
1669 unsigned SubIdx = MI.getOperand(i+1).getImm();
1670 // Nothing needs to be inserted for undef operands.
1671 if (UseMO.isUndef())
1674 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1675 // might insert a COPY that uses SrcReg after is was killed.
1676 bool isKill = UseMO.isKill();
1678 for (unsigned j = i + 2; j < e; j += 2)
1679 if (MI.getOperand(j).getReg() == SrcReg) {
1680 MI.getOperand(j).setIsKill();
1681 UseMO.setIsKill(false);
1686 // Insert the sub-register copy.
1687 MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
1688 TII->get(TargetOpcode::COPY))
1689 .addReg(DstReg, RegState::Define, SubIdx)
1692 // The first def needs an undef flag because there is no live register
1695 CopyMI->getOperand(0).setIsUndef(true);
1696 // Return an iterator pointing to the first inserted instr.
1701 // Update LiveVariables' kill info.
1702 if (LV && isKill && !Register::isPhysicalRegister(SrcReg))
1703 LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
1705 LLVM_DEBUG(dbgs() << "Inserted: " << *CopyMI);
1708 MachineBasicBlock::iterator EndMBBI =
1709 std::next(MachineBasicBlock::iterator(MI));
1712 LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
1713 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1714 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1715 MI.RemoveOperand(j);
1717 LLVM_DEBUG(dbgs() << "Eliminated: " << MI);
1718 MI.eraseFromParent();
1721 // Udpate LiveIntervals.
1723 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);