1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the table-generated and custom routines for the AArch64
10 // Calling Convention.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64CallingConvention.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64Subtarget.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
20 #include "llvm/IR/CallingConv.h"
23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7};
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
27 AArch64::H3, AArch64::H4, AArch64::H5,
28 AArch64::H6, AArch64::H7};
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
30 AArch64::S3, AArch64::S4, AArch64::S5,
31 AArch64::S6, AArch64::S7};
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
33 AArch64::D3, AArch64::D4, AArch64::D5,
34 AArch64::D6, AArch64::D7};
35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
37 AArch64::Q6, AArch64::Q7};
39 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
40 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
41 CCState &State, Align SlotAlign) {
42 unsigned Size = LocVT.getSizeInBits() / 8;
43 const Align StackAlign =
44 State.getMachineFunction().getDataLayout().getStackAlignment();
45 const Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
46 const Align Alignment = std::min(OrigAlign, StackAlign);
48 for (auto &It : PendingMembers) {
49 It.convertToMem(State.AllocateStack(Size, std::max(Alignment, SlotAlign)));
54 // All pending members have now been allocated
55 PendingMembers.clear();
59 /// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An
60 /// [N x Ty] type must still be contiguous in memory though.
61 static bool CC_AArch64_Custom_Stack_Block(
62 unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
63 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
64 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
66 // Add the argument to the list to be allocated once we know the size of the
68 PendingMembers.push_back(
69 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
71 if (!ArgFlags.isInConsecutiveRegsLast())
74 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, Align(8));
77 /// Given an [N x Ty] block, it should be passed in a consecutive sequence of
78 /// registers. If no such sequence is available, mark the rest of the registers
79 /// of that type as used and place the argument on the stack.
80 static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
81 CCValAssign::LocInfo &LocInfo,
82 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
83 const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
84 State.getMachineFunction().getSubtarget());
85 bool IsDarwinILP32 = Subtarget.isTargetILP32() && Subtarget.isTargetMachO();
87 // Try to allocate a contiguous block of registers, each of the correct
88 // size to hold one member.
89 ArrayRef<MCPhysReg> RegList;
90 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32))
92 else if (LocVT.SimpleTy == MVT::f16)
94 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
98 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
101 // Not an array we want to split up after all.
105 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
107 // Add the argument to the list to be allocated once we know the size of the
109 PendingMembers.push_back(
110 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
112 if (!ArgFlags.isInConsecutiveRegsLast())
115 // [N x i32] arguments get packed into x-registers on Darwin's arm64_32
116 // because that's how the armv7k Clang front-end emits small structs.
117 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1;
118 unsigned RegResult = State.AllocateRegBlock(
119 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg);
120 if (RegResult && EltsPerReg == 1) {
121 for (auto &It : PendingMembers) {
122 It.convertToReg(RegResult);
126 PendingMembers.clear();
128 } else if (RegResult) {
129 assert(EltsPerReg == 2 && "unexpected ABI");
130 bool UseHigh = false;
131 CCValAssign::LocInfo Info;
132 for (auto &It : PendingMembers) {
133 Info = UseHigh ? CCValAssign::AExtUpper : CCValAssign::ZExt;
134 State.addLoc(CCValAssign::getReg(It.getValNo(), MVT::i32, RegResult,
140 PendingMembers.clear();
144 // Mark all regs in the class as unavailable
145 for (auto Reg : RegList)
146 State.AllocateReg(Reg);
148 const Align SlotAlign = Subtarget.isTargetDarwin() ? Align(1) : Align(8);
150 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
153 // TableGen provides definitions of the calling convention analysis entry
155 #include "AArch64GenCallingConv.inc"