1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the AArch64 implementation of the TargetRegisterInfo
12 //===----------------------------------------------------------------------===//
14 #include "AArch64RegisterInfo.h"
15 #include "AArch64FrameLowering.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64StackOffset.h"
19 #include "AArch64Subtarget.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/CodeGen/TargetFrameLowering.h"
28 #include "llvm/IR/DiagnosticInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetOptions.h"
35 #define GET_REGINFO_TARGET_DESC
36 #include "AArch64GenRegisterInfo.inc"
38 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
39 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
40 AArch64_MC::initLLVMToCVRegMapping(this);
44 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
45 assert(MF && "Invalid MachineFunction pointer.");
46 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check)
47 return CSR_Win_AArch64_CFGuard_Check_SaveList;
48 if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows())
49 return CSR_Win_AArch64_AAPCS_SaveList;
50 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
51 // GHC set of callee saved regs is empty as all those regs are
52 // used for passing STG regs around
53 return CSR_AArch64_NoRegs_SaveList;
54 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
55 return CSR_AArch64_AllRegs_SaveList;
56 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
57 return CSR_AArch64_AAVPCS_SaveList;
58 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall)
59 return CSR_AArch64_SVE_AAPCS_SaveList;
60 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
61 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
62 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
63 CSR_AArch64_CXX_TLS_Darwin_SaveList;
64 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
65 ->supportSwiftError() &&
66 MF->getFunction().getAttributes().hasAttrSomewhere(
67 Attribute::SwiftError))
68 return CSR_AArch64_AAPCS_SwiftError_SaveList;
69 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
70 return CSR_AArch64_RT_MostRegs_SaveList;
71 if (MF->getSubtarget<AArch64Subtarget>().isTargetDarwin())
72 return CSR_Darwin_AArch64_AAPCS_SaveList;
73 return CSR_AArch64_AAPCS_SaveList;
76 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
77 const MachineFunction *MF) const {
78 assert(MF && "Invalid MachineFunction pointer.");
79 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
80 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
81 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
85 void AArch64RegisterInfo::UpdateCustomCalleeSavedRegs(
86 MachineFunction &MF) const {
87 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
88 SmallVector<MCPhysReg, 32> UpdatedCSRs;
89 for (const MCPhysReg *I = CSRs; *I; ++I)
90 UpdatedCSRs.push_back(*I);
92 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
93 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
94 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
97 // Register lists are zero-terminated.
98 UpdatedCSRs.push_back(0);
99 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
102 const TargetRegisterClass *
103 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
104 unsigned Idx) const {
105 // edge case for GPR/FPR register classes
106 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
107 return &AArch64::FPR32RegClass;
108 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
109 return &AArch64::FPR64RegClass;
111 // Forward to TableGen's default version.
112 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
116 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
117 CallingConv::ID CC) const {
118 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
119 if (CC == CallingConv::GHC)
120 // This is academic because all GHC calls are (supposed to be) tail calls
121 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
122 if (CC == CallingConv::AnyReg)
123 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
124 if (CC == CallingConv::CXX_FAST_TLS)
125 return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
126 : CSR_AArch64_CXX_TLS_Darwin_RegMask;
127 if (CC == CallingConv::AArch64_VectorCall)
128 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
129 if (CC == CallingConv::AArch64_SVE_VectorCall)
130 return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
131 : CSR_AArch64_SVE_AAPCS_RegMask;
132 if (CC == CallingConv::CFGuard_Check)
133 return CSR_Win_AArch64_CFGuard_Check_RegMask;
134 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
135 ->supportSwiftError() &&
136 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
137 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
138 : CSR_AArch64_AAPCS_SwiftError_RegMask;
139 if (CC == CallingConv::PreserveMost)
140 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
141 : CSR_AArch64_RT_MostRegs_RegMask;
143 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
146 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
148 return CSR_AArch64_TLS_Darwin_RegMask;
150 assert(TT.isOSBinFormatELF() && "Invalid target");
151 return CSR_AArch64_TLS_ELF_RegMask;
154 void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF,
155 const uint32_t **Mask) const {
156 uint32_t *UpdatedMask = MF.allocateRegMask();
157 unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
158 memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
160 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
161 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
162 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),
164 SubReg.isValid(); ++SubReg) {
165 // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
167 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
174 const uint32_t *AArch64RegisterInfo::getNoPreservedMask() const {
175 return CSR_AArch64_NoRegs_RegMask;
179 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
180 CallingConv::ID CC) const {
181 // This should return a register mask that is the same as that returned by
182 // getCallPreservedMask but that additionally preserves the register used for
183 // the first i64 argument (which must also be the register used to return a
184 // single i64 return value)
186 // In case that the calling convention does not use the same register for
187 // both, the function should return NULL (does not currently apply)
188 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
189 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
192 const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const {
193 return CSR_AArch64_StackProbe_Windows_RegMask;
197 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
198 const AArch64FrameLowering *TFI = getFrameLowering(MF);
200 // FIXME: avoid re-calculating this every time.
201 BitVector Reserved(getNumRegs());
202 markSuperRegs(Reserved, AArch64::WSP);
203 markSuperRegs(Reserved, AArch64::WZR);
205 if (TFI->hasFP(MF) || TT.isOSDarwin())
206 markSuperRegs(Reserved, AArch64::W29);
208 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
209 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))
210 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
213 if (hasBasePointer(MF))
214 markSuperRegs(Reserved, AArch64::W19);
216 // SLH uses register W16/X16 as the taint register.
217 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
218 markSuperRegs(Reserved, AArch64::W16);
220 assert(checkAllSuperRegsMarked(Reserved));
224 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
225 unsigned Reg) const {
226 return getReservedRegs(MF)[Reg];
229 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
230 return std::any_of(std::begin(*AArch64::GPR64argRegClass.MC),
231 std::end(*AArch64::GPR64argRegClass.MC),
232 [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});
235 void AArch64RegisterInfo::emitReservedArgRegCallError(
236 const MachineFunction &MF) const {
237 const Function &F = MF.getFunction();
238 F.getContext().diagnose(DiagnosticInfoUnsupported{F, "AArch64 doesn't support"
239 " function calls if any of the argument registers is reserved."});
242 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
243 unsigned PhysReg) const {
244 return !isReservedReg(MF, PhysReg);
247 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
248 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
251 const TargetRegisterClass *
252 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
253 unsigned Kind) const {
254 return &AArch64::GPR64spRegClass;
257 const TargetRegisterClass *
258 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
259 if (RC == &AArch64::CCRRegClass)
260 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
264 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
266 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
267 const MachineFrameInfo &MFI = MF.getFrameInfo();
269 // In the presence of variable sized objects or funclets, if the fixed stack
270 // size is large enough that referencing from the FP won't result in things
271 // being in range relatively often, we can use a base pointer to allow access
272 // from the other direction like the SP normally works.
274 // Furthermore, if both variable sized objects are present, and the
275 // stack needs to be dynamically re-aligned, the base pointer is the only
276 // reliable way to reference the locals.
277 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
278 if (needsStackRealignment(MF))
280 // Conservatively estimate whether the negative offset from the frame
281 // pointer will be sufficient to reach. If a function has a smallish
282 // frame, it's less likely to have lots of spills and callee saved
283 // space, so it's all more likely to be within range of the frame pointer.
284 // If it's wrong, we'll materialize the constant and still get to the
285 // object; it's just suboptimal. Negative offsets use the unscaled
286 // load/store instructions, which have a 9-bit signed immediate.
287 return MFI.getLocalFrameSize() >= 256;
294 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
295 const AArch64FrameLowering *TFI = getFrameLowering(MF);
296 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
299 bool AArch64RegisterInfo::requiresRegisterScavenging(
300 const MachineFunction &MF) const {
304 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
305 const MachineFunction &MF) const {
310 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
311 // This function indicates whether the emergency spillslot should be placed
312 // close to the beginning of the stackframe (closer to FP) or the end
315 // The beginning works most reliably if we have a frame pointer.
316 const AArch64FrameLowering &TFI = *getFrameLowering(MF);
317 return TFI.hasFP(MF);
320 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
321 const MachineFunction &MF) const {
326 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
327 const MachineFrameInfo &MFI = MF.getFrameInfo();
328 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
330 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
333 /// needsFrameBaseReg - Returns true if the instruction's frame index
334 /// reference would be better served by a base register other than FP
335 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
336 /// references it should create new base registers for.
337 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
338 int64_t Offset) const {
339 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
340 assert(i < MI->getNumOperands() &&
341 "Instr doesn't have FrameIndex operand!");
343 // It's the load/store FI references that cause issues, as it can be difficult
344 // to materialize the offset if it won't fit in the literal field. Estimate
345 // based on the size of the local frame and some conservative assumptions
346 // about the rest of the stack frame (note, this is pre-regalloc, so
347 // we don't know everything for certain yet) whether this offset is likely
348 // to be out of range of the immediate. Return true if so.
350 // We only generate virtual base registers for loads and stores, so
351 // return false for everything else.
352 if (!MI->mayLoad() && !MI->mayStore())
355 // Without a virtual base register, if the function has variable sized
356 // objects, all fixed-size local references will be via the frame pointer,
357 // Approximate the offset and see if it's legal for the instruction.
358 // Note that the incoming offset is based on the SP value at function entry,
359 // so it'll be negative.
360 MachineFunction &MF = *MI->getParent()->getParent();
361 const AArch64FrameLowering *TFI = getFrameLowering(MF);
362 MachineFrameInfo &MFI = MF.getFrameInfo();
364 // Estimate an offset from the frame pointer.
365 // Conservatively assume all GPR callee-saved registers get pushed.
366 // FP, LR, X19-X28, D8-D15. 64-bits each.
367 int64_t FPOffset = Offset - 16 * 20;
368 // Estimate an offset from the stack pointer.
369 // The incoming offset is relating to the SP at the start of the function,
370 // but when we access the local it'll be relative to the SP after local
371 // allocation, so adjust our SP-relative offset by that allocation size.
372 Offset += MFI.getLocalFrameSize();
373 // Assume that we'll have at least some spill slots allocated.
374 // FIXME: This is a total SWAG number. We should run some statistics
375 // and pick a real one.
376 Offset += 128; // 128 bytes of spill slots
378 // If there is a frame pointer, try using it.
379 // The FP is only available if there is no dynamic realignment. We
380 // don't know for sure yet whether we'll need that, so we guess based
381 // on whether there are any local variables that would trigger it.
382 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
385 // If we can reference via the stack pointer or base pointer, try that.
386 // FIXME: This (and the code that resolves the references) can be improved
387 // to only disallow SP relative references in the live range of
388 // the VLA(s). In practice, it's unclear how much difference that
389 // would make, but it may be worth doing.
390 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
393 // The offset likely isn't legal; we want to allocate a virtual base register.
397 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
399 int64_t Offset) const {
400 assert(MI && "Unable to get the legal offset for nil instruction.");
401 StackOffset SaveOffset(Offset, MVT::i8);
402 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
405 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
406 /// at the beginning of the basic block.
407 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
410 int64_t Offset) const {
411 MachineBasicBlock::iterator Ins = MBB->begin();
412 DebugLoc DL; // Defaults to "unknown"
413 if (Ins != MBB->end())
414 DL = Ins->getDebugLoc();
415 const MachineFunction &MF = *MBB->getParent();
416 const AArch64InstrInfo *TII =
417 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
418 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
419 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
420 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
421 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
423 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
424 .addFrameIndex(FrameIdx)
429 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
430 int64_t Offset) const {
431 // ARM doesn't need the general 64-bit offsets
432 StackOffset Off(Offset, MVT::i8);
436 while (!MI.getOperand(i).isFI()) {
438 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
440 const MachineFunction *MF = MI.getParent()->getParent();
441 const AArch64InstrInfo *TII =
442 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
443 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
444 assert(Done && "Unable to resolve frame index!");
448 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
449 int SPAdj, unsigned FIOperandNum,
450 RegScavenger *RS) const {
451 assert(SPAdj == 0 && "Unexpected");
453 MachineInstr &MI = *II;
454 MachineBasicBlock &MBB = *MI.getParent();
455 MachineFunction &MF = *MBB.getParent();
456 const MachineFrameInfo &MFI = MF.getFrameInfo();
457 const AArch64InstrInfo *TII =
458 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
459 const AArch64FrameLowering *TFI = getFrameLowering(MF);
461 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
463 MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
466 // Special handling of dbg_value, stackmap and patchpoint instructions.
467 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
468 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
470 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
473 Offset += StackOffset(MI.getOperand(FIOperandNum + 1).getImm(), MVT::i8);
474 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
475 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getBytes());
479 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
480 MachineOperand &FI = MI.getOperand(FIOperandNum);
481 int Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex);
482 FI.ChangeToImmediate(Offset);
487 if (MI.getOpcode() == AArch64::TAGPstack) {
488 // TAGPstack must use the virtual frame register in its 3rd operand.
489 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
490 FrameReg = MI.getOperand(3).getReg();
491 Offset = {MFI.getObjectOffset(FrameIndex) +
492 AFI->getTaggedBasePointerOffset(),
495 StackOffset SPOffset = {
496 MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize(), MVT::i8};
497 if (MFI.hasVarSizedObjects() ||
498 isAArch64FrameOffsetLegal(MI, SPOffset, nullptr, nullptr, nullptr) !=
499 (AArch64FrameOffsetCanUpdate | AArch64FrameOffsetIsLegal)) {
500 // Can't update to SP + offset in place. Precalculate the tagged pointer
501 // in a scratch register.
502 Offset = TFI->resolveFrameIndexReference(
503 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
504 Register ScratchReg =
505 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
506 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
508 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
512 MI.getOperand(FIOperandNum)
513 .ChangeToRegister(ScratchReg, false, false, true);
516 FrameReg = AArch64::SP;
517 Offset = {MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize(),
520 Offset = TFI->resolveFrameIndexReference(
521 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
524 // Modify MI as necessary to handle as much of 'Offset' as possible
525 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
528 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
529 "Emergency spill slot is out of reach");
531 // If we get here, the immediate doesn't fit into the instruction. We folded
532 // as much as possible above. Handle the rest, providing a register that is
534 Register ScratchReg =
535 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
536 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
537 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
540 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
541 MachineFunction &MF) const {
542 const AArch64FrameLowering *TFI = getFrameLowering(MF);
544 switch (RC->getID()) {
547 case AArch64::GPR32RegClassID:
548 case AArch64::GPR32spRegClassID:
549 case AArch64::GPR32allRegClassID:
550 case AArch64::GPR64spRegClassID:
551 case AArch64::GPR64allRegClassID:
552 case AArch64::GPR64RegClassID:
553 case AArch64::GPR32commonRegClassID:
554 case AArch64::GPR64commonRegClassID:
555 return 32 - 1 // XZR/SP
556 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
557 - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved()
558 - hasBasePointer(MF); // X19
559 case AArch64::FPR8RegClassID:
560 case AArch64::FPR16RegClassID:
561 case AArch64::FPR32RegClassID:
562 case AArch64::FPR64RegClassID:
563 case AArch64::FPR128RegClassID:
566 case AArch64::DDRegClassID:
567 case AArch64::DDDRegClassID:
568 case AArch64::DDDDRegClassID:
569 case AArch64::QQRegClassID:
570 case AArch64::QQQRegClassID:
571 case AArch64::QQQQRegClassID:
574 case AArch64::FPR128_loRegClassID:
579 unsigned AArch64RegisterInfo::getLocalAddressRegister(
580 const MachineFunction &MF) const {
581 const auto &MFI = MF.getFrameInfo();
582 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
584 else if (needsStackRealignment(MF))
585 return getBaseRegister();
586 return getFrameRegister(MF);