contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

   1 //=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M4 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide
  16 // in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM4Model : SchedMachineModel {
  20   let IssueWidth            =   6; // Up to 6 uops per cycle.
  21   let MicroOpBufferSize     = 228; // ROB size.
  22   let LoopMicroOpBufferSize =  48; // Based on the instruction queue size.
  23   let LoadLatency           =   4; // Optimistic load cases.
  24   let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
  25   let CompleteModel         =   1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
  28                                                     PAUnsupported.F);
  29 }
  30
  31 //===----------------------------------------------------------------------===//
  32 // Define each kind of processor resource and number available on the Exynos-M4.
  33
  34 let SchedModel = ExynosM4Model in {
  35
  36 def M4UnitA  : ProcResource<2>; // Simple integer
  37 def M4UnitC  : ProcResource<2>; // Simple and complex integer
  38 let Super =  M4UnitC, BufferSize = 1 in
  39 def M4UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  40 let Super =  M4UnitC in
  41 def M4UnitE  : ProcResource<1>; // CRC (inside C0)
  42 def M4UnitB  : ProcResource<2>; // Branch
  43 def M4UnitL0 : ProcResource<1>; // Load
  44 def M4UnitS0 : ProcResource<1>; // Store
  45 def M4PipeLS : ProcResource<1>; // Load/Store
  46 let Super = M4PipeLS in {
  47   def M4UnitL1 : ProcResource<1>;
  48   def M4UnitS1 : ProcResource<1>;
  49 }
  50 def M4PipeF0 : ProcResource<1>; // FP #0
  51 let Super = M4PipeF0 in {
  52   def M4UnitFMAC0 : ProcResource<1>; // FP multiplication
  53   def M4UnitFADD0 : ProcResource<1>; // Simple FP
  54   def M4UnitFCVT0 : ProcResource<1>; // FP conversion
  55   def M4UnitNALU0 : ProcResource<1>; // Simple vector
  56   def M4UnitNHAD  : ProcResource<1>; // Horizontal vector
  57   def M4UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  58   def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication
  59   def M4UnitNSHT0 : ProcResource<1>; // Vector shifting
  60   def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling
  61   def M4UnitNCRY0 : ProcResource<1>; // Cryptographic
  62 }
  63 def M4PipeF1 : ProcResource<1>; // FP #1
  64 let Super = M4PipeF1 in {
  65   def M4UnitFMAC1 : ProcResource<1>; // FP multiplication
  66   def M4UnitFADD1 : ProcResource<1>; // Simple FP
  67   def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  68   def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
  69   def M4UnitFST0  : ProcResource<1>; // FP store
  70   def M4UnitNALU1 : ProcResource<1>; // Simple vector
  71   def M4UnitNSHT1 : ProcResource<1>; // Vector shifting
  72   def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling
  73 }
  74 def M4PipeF2 : ProcResource<1>; // FP #2
  75 let Super = M4PipeF2 in {
  76   def M4UnitFMAC2 : ProcResource<1>; // FP multiplication
  77   def M4UnitFADD2 : ProcResource<1>; // Simple FP
  78   def M4UnitFCVT1 : ProcResource<1>; // FP conversion
  79   def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  80   def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
  81   def M4UnitFST1  : ProcResource<1>; // FP store
  82   def M4UnitNALU2 : ProcResource<1>; // Simple vector
  83   def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication
  84   def M4UnitNSHT2 : ProcResource<1>; // Vector shifting
  85   def M4UnitNCRY1 : ProcResource<1>; // Cryptographic
  86 }
  87
  88 def M4UnitALU   : ProcResGroup<[M4UnitA,
  89                                 M4UnitC]>;
  90 def M4UnitL     : ProcResGroup<[M4UnitL0,
  91                                 M4UnitL1]>;
  92 def M4UnitS     : ProcResGroup<[M4UnitS0,
  93                                 M4UnitS1]>;
  94 def M4UnitFMAC  : ProcResGroup<[M4UnitFMAC0,
  95                                 M4UnitFMAC1,
  96                                 M4UnitFMAC2]>;
  97 def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0,
  98                                 M4UnitFMAC1]>;
  99 def M4UnitFADD  : ProcResGroup<[M4UnitFADD0,
 100                                 M4UnitFADD1,
 101                                 M4UnitFADD2]>;
 102 def M4UnitFADDH : ProcResGroup<[M4UnitFADD0,
 103                                 M4UnitFADD1]>;
 104 def M4UnitFCVT  : ProcResGroup<[M4UnitFCVT0,
 105                                 M4UnitFCVT1]>;
 106 def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>;
 107 def M4UnitFDIV  : ProcResGroup<[M4UnitFDIV0,
 108                                 M4UnitFDIV1]>;
 109 def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>;
 110 def M4UnitFSQR  : ProcResGroup<[M4UnitFSQR0,
 111                                 M4UnitFSQR1]>;
 112 def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>;
 113 def M4UnitFST   : ProcResGroup<[M4UnitFST0,
 114                                 M4UnitFST1]>;
 115 def M4UnitNALU  : ProcResGroup<[M4UnitNALU0,
 116                                 M4UnitNALU1,
 117                                 M4UnitNALU2]>;
 118 def M4UnitNALUH : ProcResGroup<[M4UnitNALU0,
 119                                 M4UnitNALU1]>;
 120 def M4UnitNMUL  : ProcResGroup<[M4UnitNMUL0,
 121                                 M4UnitNMUL1]>;
 122 def M4UnitNSHT  : ProcResGroup<[M4UnitNSHT0,
 123                                 M4UnitNSHT1,
 124                                 M4UnitNSHT2]>;
 125 def M4UnitNSHF  : ProcResGroup<[M4UnitNSHF0,
 126                                 M4UnitNSHF1]>;
 127 def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>;
 128 def M4UnitNCRY  : ProcResGroup<[M4UnitNCRY0,
 129                                 M4UnitNCRY1]>;
 130
 131 //===----------------------------------------------------------------------===//
 132 // Resources details.
 133
 134 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
 135 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 136                                     let NumMicroOps = 0; }
 137 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
 138                                     let NumMicroOps = 0; }
 139
 140 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
 141 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
 142 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
 143                                              let ResourceCycles = [2]; }
 144 def M4WriteAB : SchedWriteRes<[M4UnitALU,
 145                                M4UnitC]>   { let Latency = 2;
 146                                              let NumMicroOps = 2; }
 147 def M4WriteAC : SchedWriteRes<[M4UnitALU,
 148                                M4UnitALU,
 149                                M4UnitC]>   { let Latency = 3;
 150                                              let NumMicroOps = 3; }
 151 def M4WriteAD : SchedWriteRes<[M4UnitALU,
 152                                M4UnitC]>   { let Latency = 2;
 153                                              let NumMicroOps = 2; }
 154 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
 155                                              let NumMicroOps = 2; }
 156 def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M4WriteZ0]>,
 157                                    SchedVar<ExynosArithPred,   [M4WriteA1]>,
 158                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 159                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 160 def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M4WriteZ0]>,
 161                                    SchedVar<ExynosArithPred,   [M4WriteA1]>,
 162                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 163                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 164 def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M4WriteA1]>,
 165                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 166                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 167 def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>,
 168                                    SchedVar<NoSchedPred,              [M4WriteAF]>]>;
 169
 170 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
 171 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
 172                                    SchedVar<NoSchedPred,            [M4WriteAB]>]>;
 173
 174 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
 175 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
 176 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
 177                                            let ResourceCycles = [2]; }
 178
 179 def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
 180                                             let ResourceCycles = [12]; }
 181 def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
 182                                             let ResourceCycles = [21]; }
 183
 184 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
 185
 186 def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; }
 187 def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; }
 188 def M4WriteLA : SchedWriteRes<[M4UnitL,
 189                                M4UnitL]> { let Latency = 5;
 190                                            let NumMicroOps = 1; }
 191 def M4WriteLB : SchedWriteRes<[M4UnitA,
 192                                M4UnitL]> { let Latency = 5;
 193                                            let NumMicroOps = 2; }
 194 def M4WriteLC : SchedWriteRes<[M4UnitA,
 195                                M4UnitL,
 196                                M4UnitL]> { let Latency = 5;
 197                                            let NumMicroOps = 2; }
 198 def M4WriteLD : SchedWriteRes<[M4UnitA,
 199                                M4UnitL]> { let Latency = 4;
 200                                            let NumMicroOps = 2; }
 201 def M4WriteLE : SchedWriteRes<[M4UnitA,
 202                                M4UnitL]> { let Latency = 6;
 203                                            let NumMicroOps = 2; }
 204 def M4WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 205                                            let NumMicroOps = 0; }
 206 def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>,
 207                                    SchedVar<NoSchedPred,         [M4WriteL4]>]>;
 208 def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>,
 209                                    SchedVar<NoSchedPred,         [M4WriteL5]>]>;
 210
 211 def M4WriteS1 : SchedWriteRes<[M4UnitS]>  { let Latency = 1; }
 212 def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; }
 213 def M4WriteSB : SchedWriteRes<[M4UnitA,
 214                                M4UnitS]>  { let Latency = 2;
 215                                             let NumMicroOps = 1; }
 216 def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>,
 217                                    SchedVar<NoSchedPred,         [M4WriteS1]>]>;
 218
 219 def M4ReadAdrBase : SchedReadVariant<[SchedVar<
 220                                         MCSchedPredicate<
 221                                           CheckAny<
 222                                             [ScaledIdxFn,
 223                                              ExynosScaledIdxFn]>>, [ReadDefault]>,
 224                                       SchedVar<NoSchedPred,        [ReadDefault]>]>;
 225
 226 def M4WriteNEONA   : SchedWriteRes<[M4UnitNSHF,
 227                                     M4UnitFADD]>  { let Latency = 3;
 228                                                     let NumMicroOps = 2; }
 229 def M4WriteNEONB   : SchedWriteRes<[M4UnitNALU,
 230                                     M4UnitS0]>    { let Latency = 5;
 231                                                     let NumMicroOps = 2; }
 232 def M4WriteNEOND   : SchedWriteRes<[M4UnitNSHF,
 233                                     M4UnitFST]>   { let Latency = 6;
 234                                                     let NumMicroOps = 2; }
 235 def M4WriteNEONH   : SchedWriteRes<[M4UnitNALU,
 236                                     M4UnitS0]>    { let Latency = 5;
 237                                                     let NumMicroOps = 2; }
 238 def M4WriteNEONI   : SchedWriteRes<[M4UnitNSHF,
 239                                     M4UnitS0]>    { let Latency = 2;
 240                                                     let NumMicroOps = 2; }
 241 def M4WriteNEONJ   : SchedWriteRes<[M4UnitNMSC,
 242                                     M4UnitS0]>    { let Latency = 4; }
 243 def M4WriteNEONK   : SchedWriteRes<[M4UnitNSHF,
 244                                     M4UnitNMSC,
 245                                     M4UnitS0]>    { let Latency = 5;
 246                                                     let NumMicroOps = 2; }
 247 def M4WriteNEONL   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 248 def M4WriteNEONN   : SchedWriteRes<[M4UnitNMSC,
 249                                     M4UnitNMSC]>  { let Latency = 5;
 250                                                     let NumMicroOps = 2; }
 251 def M4WriteNEONO   : SchedWriteRes<[M4UnitNMSC,
 252                                     M4UnitNMSC,
 253                                     M4UnitNMSC]>  { let Latency = 8;
 254                                                     let NumMicroOps = 3; }
 255 def M4WriteNEONP   : SchedWriteRes<[M4UnitNSHF,
 256                                     M4UnitNMSC]>  { let Latency = 4;
 257                                                     let NumMicroOps = 2; }
 258 def M4WriteNEONQ   : SchedWriteRes<[M4UnitNMSC,
 259                                     M4UnitC]>     { let Latency = 3;
 260                                                     let NumMicroOps = 1; }
 261 def M4WriteNEONR   : SchedWriteRes<[M4UnitFCVT0,
 262                                     M4UnitS0]>    { let Latency = 4;
 263                                                     let NumMicroOps = 1; }
 264 def M4WriteNEONV   : SchedWriteRes<[M4UnitFDIV,
 265                                     M4UnitFDIV]>  { let Latency = 7;
 266                                                     let ResourceCycles = [6, 6]; }
 267 def M4WriteNEONVH  : SchedWriteRes<[M4UnitFDIVH,
 268                                     M4UnitFDIVH]> { let Latency = 7;
 269                                                     let ResourceCycles = [6, 6]; }
 270 def M4WriteNEONW   : SchedWriteRes<[M4UnitFDIV,
 271                                     M4UnitFDIV]>  { let Latency = 12;
 272                                                     let ResourceCycles = [9, 9]; }
 273 def M4WriteNEONX   : SchedWriteRes<[M4UnitFSQR,
 274                                     M4UnitFSQR]>  { let Latency = 8;
 275                                                     let ResourceCycles = [7, 7]; }
 276 def M4WriteNEONXH  : SchedWriteRes<[M4UnitFSQRH,
 277                                     M4UnitFSQRH]> { let Latency = 7;
 278                                                     let ResourceCycles = [6, 6]; }
 279 def M4WriteNEONY   : SchedWriteRes<[M4UnitFSQR,
 280                                     M4UnitFSQR]>  { let Latency = 12;
 281                                                     let ResourceCycles = [9, 9]; }
 282 def M4WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
 283                                         SchedVar<NoSchedPred,     [M4WriteNEONN]>]>;
 284
 285 def M4WriteFADD2   : SchedWriteRes<[M4UnitFADD]>  { let Latency = 2; }
 286 def M4WriteFADD2H  : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; }
 287
 288 def M4WriteFCVT2   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 2; }
 289 def M4WriteFCVT2A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; }
 290 def M4WriteFCVT2H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; }
 291 def M4WriteFCVT3   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 3; }
 292 def M4WriteFCVT3A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; }
 293 def M4WriteFCVT3H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; }
 294 def M4WriteFCVT4   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 4; }
 295 def M4WriteFCVT4A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
 296 def M4WriteFCVT6A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
 297
 298 def M4WriteFDIV7   : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 7;
 299                                                     let ResourceCycles = [6]; }
 300 def M4WriteFDIV7H  : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
 301                                                     let ResourceCycles = [6]; }
 302 def M4WriteFDIV12  : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 12;
 303                                                     let ResourceCycles = [9]; }
 304
 305 def M4WriteFMAC2H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
 306 def M4WriteFMAC3H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
 307 def M4WriteFMAC3   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 3; }
 308 def M4WriteFMAC4   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 4; }
 309 def M4WriteFMAC4H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
 310 def M4WriteFMAC5   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 5; }
 311
 312 def M4WriteFSQR7H  : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
 313                                                     let ResourceCycles = [6]; }
 314 def M4WriteFSQR8   : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 8;
 315                                                     let ResourceCycles = [7]; }
 316 def M4WriteFSQR12  : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 12;
 317                                                     let ResourceCycles = [9]; }
 318
 319 def M4WriteNALU1   : SchedWriteRes<[M4UnitNALU]>  { let Latency = 1; }
 320 def M4WriteNALU1H  : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
 321
 322 def M4WriteNCRY1   : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 1; }
 323 def M4WriteNCRY1A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; }
 324 def M4WriteNCRY3A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; }
 325 def M4WriteNCRY5A  : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 5; }
 326
 327 def M4WriteNHAD1   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 1; }
 328 def M4WriteNHAD3   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 3; }
 329
 330 def M4WriteNMSC1   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 1; }
 331 def M4WriteNMSC2   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 2; }
 332 def M4WriteNMSC3   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 3; }
 333
 334 def M4WriteNMUL3   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 335
 336 def M4WriteNSHF1   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1; }
 337 def M4WriteNSHF1H  : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
 338 def M4WriteNSHF3   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3; }
 339 def M4WriteNSHFA   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1;
 340                                                     let ResourceCycles = [2]; }
 341 def M4WriteNSHFB   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 2;
 342                                                     let NumMicroOps = 2;
 343                                                     let ResourceCycles = [2]; }
 344 def M4WriteNSHFC   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3;
 345                                                     let NumMicroOps = 3;
 346                                                     let ResourceCycles = [4]; }
 347 def M4WriteNSHFD   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 4;
 348                                                     let NumMicroOps = 4;
 349                                                     let ResourceCycles = [4]; }
 350
 351 def M4WriteNSHT1   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 1; }
 352 def M4WriteNSHT2   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 2; }
 353 def M4WriteNSHT3   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 3; }
 354 def M4WriteNSHT4A  : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; }
 355
 356 def M4WriteVLDA    : SchedWriteRes<[M4UnitL,
 357                                     M4UnitL]>     { let Latency = 5;
 358                                                     let NumMicroOps = 2; }
 359 def M4WriteVLDB    : SchedWriteRes<[M4UnitL,
 360                                     M4UnitL,
 361                                     M4UnitL]>     { let Latency = 6;
 362                                                     let NumMicroOps = 3; }
 363 def M4WriteVLDC    : SchedWriteRes<[M4UnitL,
 364                                     M4UnitL,
 365                                     M4UnitL,
 366                                     M4UnitL]>     { let Latency = 6;
 367                                                     let NumMicroOps = 4; }
 368 def M4WriteVLDD    : SchedWriteRes<[M4UnitL,
 369                                     M4UnitNSHF]>  { let Latency = 6;
 370                                                     let NumMicroOps = 2;
 371                                                     let ResourceCycles = [2, 1]; }
 372 def M4WriteVLDF    : SchedWriteRes<[M4UnitL,
 373                                     M4UnitL]>     { let Latency = 10;
 374                                                     let NumMicroOps = 2;
 375                                                     let ResourceCycles = [3, 3]; }
 376 def M4WriteVLDG    : SchedWriteRes<[M4UnitL,
 377                                     M4UnitNSHF,
 378                                     M4UnitNSHF]>  { let Latency = 6;
 379                                                     let NumMicroOps = 3;
 380                                                     let ResourceCycles = [2, 1, 1]; }
 381 def M4WriteVLDI    : SchedWriteRes<[M4UnitL,
 382                                     M4UnitL,
 383                                     M4UnitL]>     { let Latency = 12;
 384                                                     let NumMicroOps = 3;
 385                                                     let ResourceCycles = [3, 3, 3]; }
 386 def M4WriteVLDJ    : SchedWriteRes<[M4UnitL,
 387                                     M4UnitNSHF,
 388                                     M4UnitNSHF,
 389                                     M4UnitNSHF]>  { let Latency = 7;
 390                                                     let NumMicroOps = 4;
 391                                                     let ResourceCycles = [3, 1, 1, 1]; }
 392 def M4WriteVLDK    : SchedWriteRes<[M4UnitL,
 393                                     M4UnitNSHF,
 394                                     M4UnitNSHF,
 395                                     M4UnitNSHF,
 396                                     M4UnitNSHF]>  { let Latency = 7;
 397                                                     let NumMicroOps = 5;
 398                                                     let ResourceCycles = [3, 1, 1, 1, 1]; }
 399 def M4WriteVLDL    : SchedWriteRes<[M4UnitL,
 400                                     M4UnitNSHF,
 401                                     M4UnitNSHF,
 402                                     M4UnitL,
 403                                     M4UnitNSHF]>  { let Latency = 7;
 404                                                     let NumMicroOps = 5;
 405                                                     let ResourceCycles = [3, 1, 1, 6, 1]; }
 406 def M4WriteVLDM    : SchedWriteRes<[M4UnitL,
 407                                     M4UnitNSHF,
 408                                     M4UnitNSHF,
 409                                     M4UnitL,
 410                                     M4UnitNSHF,
 411                                     M4UnitNSHF]>  { let Latency = 7;
 412                                                     let NumMicroOps = 6;
 413                                                     let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
 414 def M4WriteVLDN    : SchedWriteRes<[M4UnitL,
 415                                     M4UnitL,
 416                                     M4UnitL,
 417                                     M4UnitL]>     { let Latency = 14;
 418                                                     let NumMicroOps = 4;
 419                                                     let ResourceCycles = [3, 3, 3, 3]; }
 420
 421 def M4WriteVST1    : SchedWriteRes<[M4UnitS,
 422                                     M4UnitFST]>  { let Latency = 1;
 423                                                    let NumMicroOps = 1; }
 424 def M4WriteVSTA    : WriteSequence<[WriteVST], 2>;
 425 def M4WriteVSTB    : WriteSequence<[WriteVST], 3>;
 426 def M4WriteVSTC    : WriteSequence<[WriteVST], 4>;
 427 def M4WriteVSTD    : SchedWriteRes<[M4UnitS,
 428                                     M4UnitFST]>   { let Latency = 2; }
 429 def M4WriteVSTE    : SchedWriteRes<[M4UnitS,
 430                                     M4UnitFST,
 431                                     M4UnitS,
 432                                     M4UnitFST]>   { let Latency = 2;
 433                                                     let NumMicroOps = 2; }
 434 def M4WriteVSTF    : SchedWriteRes<[M4UnitNSHF,
 435                                     M4UnitS,
 436                                     M4UnitFST,
 437                                     M4UnitS,
 438                                     M4UnitFST]>   { let Latency = 4;
 439                                                     let NumMicroOps = 4;
 440                                                     let ResourceCycles = [1, 2, 1, 2, 1]; }
 441 def M4WriteVSTG    : SchedWriteRes<[M4UnitNSHF,
 442                                     M4UnitNSHF,
 443                                     M4UnitNSHF,
 444                                     M4UnitS,
 445                                     M4UnitFST,
 446                                     M4UnitS,
 447                                     M4UnitFST,
 448                                     M4UnitS,
 449                                     M4UnitFST]>   { let Latency = 5;
 450                                                     let NumMicroOps = 6;
 451                                                     let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
 452 def M4WriteVSTI    : SchedWriteRes<[M4UnitNSHF,
 453                                     M4UnitNSHF,
 454                                     M4UnitNSHF,
 455                                     M4UnitNSHF,
 456                                     M4UnitS,
 457                                     M4UnitFST,
 458                                     M4UnitS,
 459                                     M4UnitFST,
 460                                     M4UnitS,
 461                                     M4UnitFST,
 462                                     M4UnitS,
 463                                     M4UnitFST]>   { let Latency = 8;
 464                                                     let NumMicroOps = 5;
 465                                                     let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 466 def M4WriteVSTJ    : SchedWriteRes<[M4UnitA,
 467                                     M4UnitS,
 468                                     M4UnitFST,
 469                                     M4UnitS,
 470                                     M4UnitFST]>   { let Latency = 1;
 471                                                     let NumMicroOps = 2; }
 472 def M4WriteVSTK    : SchedWriteRes<[M4UnitA,
 473                                     M4UnitS,
 474                                     M4UnitFST]>   { let Latency = 3;
 475                                                     let NumMicroOps = 2; }
 476 def M4WriteVSTL    : SchedWriteRes<[M4UnitNSHF,
 477                                     M4UnitNSHF,
 478                                     M4UnitS,
 479                                     M4UnitFST,
 480                                     M4UnitS,
 481                                     M4UnitFST]>   { let Latency = 4;
 482                                                     let NumMicroOps = 4;
 483                                                     let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
 484 def M4WriteVSTY    : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>,
 485                                         SchedVar<NoSchedPred,         [WriteVST]>]>;
 486
 487 // Special cases.
 488 def M4WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
 489                                         SchedVar<NoSchedPred,  [M4WriteZ0]>]>;
 490 def M4WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>,
 491                                         SchedVar<NoSchedPred,       [M4WriteNALU1]>]>;
 492
 493 // Fast forwarding.
 494 def M4ReadAESM1    : SchedReadAdvance<+1, [M4WriteNCRY1]>;
 495 def M4ReadFMACM1   : SchedReadAdvance<+1, [M4WriteFMAC4,
 496                                            M4WriteFMAC4H,
 497                                            M4WriteFMAC5]>;
 498 def M4ReadNMULM1   : SchedReadAdvance<+1, [M4WriteNMUL3]>;
 499 def M4ReadNMULP2   : SchedReadAdvance<-2, [M4WriteNMUL3]>;
 500
 501
 502 //===----------------------------------------------------------------------===//
 503 // Coarse scheduling model.
 504
 505 // Branch instructions.
 506 def : SchedAlias<WriteBr,    M4WriteZ0>;
 507 def : SchedAlias<WriteBrReg, M4WriteC1>;
 508
 509 // Arithmetic and logical integer instructions.
 510 def : SchedAlias<WriteI,     M4WriteA1>;
 511 def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
 512 def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
 513 def : SchedAlias<WriteIS,    M4WriteA1>;
 514
 515 // Move instructions.
 516 def : SchedAlias<WriteImm, M4WriteA1>;
 517
 518 // Divide and multiply instructions.
 519 def : SchedAlias<WriteID32, M4WriteD12>;
 520 def : SchedAlias<WriteID64, M4WriteD21>;
 521 def : SchedAlias<WriteIM32, M4WriteC3>;
 522 def : SchedAlias<WriteIM64, M4WriteCA>;
 523
 524 // Miscellaneous instructions.
 525 def : SchedAlias<WriteExtr, M4WriteAY>;
 526
 527 // Addressing modes.
 528 def : SchedAlias<WriteAdr,    M4WriteZ1>;
 529 def : SchedAlias<ReadAdrBase, M4ReadAdrBase>;
 530
 531 // Load instructions.
 532 def : SchedAlias<WriteLD,    M4WriteL4>;
 533 def : SchedAlias<WriteLDHi,  M4WriteZ4>;
 534 def : SchedAlias<WriteLDIdx, M4WriteLX>;
 535
 536 // Store instructions.
 537 def : SchedAlias<WriteST,    M4WriteS1>;
 538 def : SchedAlias<WriteSTP,   M4WriteS1>;
 539 def : SchedAlias<WriteSTX,   M4WriteS1>;
 540 def : SchedAlias<WriteSTIdx, M4WriteSX>;
 541
 542 // FP data instructions.
 543 def : SchedAlias<WriteF,    M4WriteFADD2>;
 544 def : SchedAlias<WriteFCmp, M4WriteNMSC2>;
 545 def : SchedAlias<WriteFDiv, M4WriteFDIV12>;
 546 def : SchedAlias<WriteFMul, M4WriteFMAC3>;
 547
 548 // FP miscellaneous instructions.
 549 def : SchedAlias<WriteFCvt,  M4WriteFCVT2>;
 550 def : SchedAlias<WriteFImm,  M4WriteNALU1>;
 551 def : SchedAlias<WriteFCopy, M4WriteNALU1>;
 552
 553 // FP load instructions.
 554 def : SchedAlias<WriteVLD, M4WriteL5>;
 555
 556 // FP store instructions.
 557 def : SchedAlias<WriteVST, M4WriteVST1>;
 558
 559 // ASIMD FP instructions.
 560 def : SchedAlias<WriteV, M4WriteNALU1>;
 561
 562 // Other miscellaneous instructions.
 563 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 564 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 565 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 566 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 567
 568 //===----------------------------------------------------------------------===//
 569 // Generic fast forwarding.
 570
 571 // TODO: Add FP register forwarding rules.
 572
 573 def : ReadAdvance<ReadI,       0>;
 574 def : ReadAdvance<ReadISReg,   0>;
 575 def : ReadAdvance<ReadIEReg,   0>;
 576 def : ReadAdvance<ReadIM,      0>;
 577 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 578 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 579 def : ReadAdvance<ReadID,      0>;
 580 def : ReadAdvance<ReadExtrHi,  0>;
 581 def : ReadAdvance<ReadAdrBase, 0>;
 582 def : ReadAdvance<ReadVLD,     0>;
 583
 584 //===----------------------------------------------------------------------===//
 585 // Finer scheduling model.
 586
 587 // Branch instructions
 588 def : InstRW<[M4WriteB1], (instrs Bcc)>;
 589 def : InstRW<[M4WriteAF], (instrs BL)>;
 590 def : InstRW<[M4WriteBX], (instrs BLR)>;
 591 def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>;
 592 def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>;
 593
 594 // Arithmetic and logical integer instructions.
 595 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 596 def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>;
 597 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 598 def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
 599 def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>;
 600
 601 // Move instructions.
 602 def : InstRW<[M4WriteCOPY], (instrs COPY)>;
 603 def : InstRW<[M4WriteZ0],   (instrs ADR, ADRP)>;
 604 def : InstRW<[M4WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
 605
 606 // Divide and multiply instructions.
 607
 608 // Miscellaneous instructions.
 609
 610 // Load instructions.
 611 def : InstRW<[M4WriteLD,
 612               WriteLDHi,
 613               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 614 def : InstRW<[M4WriteL5,
 615               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 616 def : InstRW<[WriteLDIdx,
 617               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 618 def : InstRW<[M4WriteL5,
 619               ReadAdrBase], (instrs PRFMroW)>;
 620 def : InstRW<[WriteLDIdx,
 621               ReadAdrBase], (instrs PRFMroX)>;
 622
 623 // Store instructions.
 624 def : InstRW<[M4WriteSB,
 625               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 626 def : InstRW<[WriteST,
 627               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 628
 629 // FP data instructions.
 630 def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>;
 631 def : InstRW<[M4WriteNSHF1],  (instregex "^FABS[SD]r")>;
 632 def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>;
 633 def : InstRW<[M4WriteFADD2],  (instregex "^F(ADD|SUB)[SD]rr")>;
 634 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>;
 635 def : InstRW<[M4WriteFADD2],  (instregex "^FADDPv.i(32|64)")>;
 636 def : InstRW<[M4WriteNEONQ],  (instregex "^FCCMPE?[HSD]rr")>;
 637 def : InstRW<[M4WriteNMSC2],  (instregex "^FCMPE?[HSD]r[ir]")>;
 638 def : InstRW<[M4WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
 639 def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>;
 640 def : InstRW<[M4WriteFDIV7],  (instrs FDIVSrr)>;
 641 def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>;
 642 def : InstRW<[M4WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
 643 def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>;
 644 def : InstRW<[M4WriteFMAC3],  (instregex "^FN?MUL[SD]rr")>;
 645 def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>;
 646 def : InstRW<[M4WriteFMAC3],  (instregex "^FMULX(32|64)")>;
 647 def : InstRW<[M4WriteFMAC4H,
 648               M4ReadFMACM1],  (instregex "^FN?M(ADD|SUB)Hrrr")>;
 649 def : InstRW<[M4WriteFMAC4,
 650               M4ReadFMACM1],  (instregex "^FN?M(ADD|SUB)[SD]rrr")>;
 651 def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>;
 652 def : InstRW<[M4WriteNALU1],  (instregex "^FNEG[SD]r")>;
 653 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
 654 def : InstRW<[M4WriteNEONH],  (instregex "^FCSEL[HSD]rrr")>;
 655 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>;
 656 def : InstRW<[M4WriteFSQR8],  (instrs FSQRTSr)>;
 657 def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>;
 658
 659 // FP miscellaneous instructions.
 660 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>;
 661 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>;
 662 def : InstRW<[M4WriteFCVT2],  (instregex "^FCVT[SD][SD]r")>;
 663 def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
 664 def : InstRW<[M4WriteNEONR],  (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
 665 def : InstRW<[M4WriteNALU1],  (instregex "^FMOV[HSD][ir]")>;
 666 def : InstRW<[M4WriteSA],     (instregex "^FMOV[WX][HSD]r")>;
 667 def : InstRW<[M4WriteNEONJ],  (instregex "^FMOV[HSD][WX]r")>;
 668 def : InstRW<[M4WriteNEONI],  (instregex "^FMOVXDHighr")>;
 669 def : InstRW<[M4WriteNEONK],  (instregex "^FMOVDXHighr")>;
 670 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
 671 def : InstRW<[M4WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
 672 def : InstRW<[M4WriteNMSC1],  (instregex "^FRECPXv1")>;
 673 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>;
 674 def : InstRW<[M4WriteFMAC4],  (instregex "^F(RECP|RSQRT)S(32|64)")>;
 675
 676 // FP load instructions.
 677 def : InstRW<[WriteVLD],    (instregex "^LDR[SDQ]l")>;
 678 def : InstRW<[WriteVLD],    (instregex "^LDUR[BHSDQ]i")>;
 679 def : InstRW<[WriteVLD,
 680               WriteAdr],    (instregex "^LDR[BHSDQ](post|pre)")>;
 681 def : InstRW<[WriteVLD],    (instregex "^LDR[BHSDQ]ui")>;
 682 def : InstRW<[M4WriteLE,
 683               ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
 684 def : InstRW<[WriteVLD,
 685               ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
 686 def : InstRW<[M4WriteLY,
 687               ReadAdrBase], (instrs LDRQroX)>;
 688 def : InstRW<[WriteVLD,
 689               M4WriteLH],   (instregex "^LDN?P[SD]i")>;
 690 def : InstRW<[M4WriteLA,
 691               M4WriteLH],   (instregex "^LDN?PQi")>;
 692 def : InstRW<[M4WriteL5,
 693               M4WriteLH,
 694               WriteAdr],    (instregex "^LDP[SD]post")>;
 695 def : InstRW<[M4WriteLB,
 696               M4WriteLH,
 697               WriteAdr],    (instrs LDPQpost)>;
 698 def : InstRW<[M4WriteLB,
 699               M4WriteLH,
 700               WriteAdr],    (instregex "^LDP[SD]pre")>;
 701 def : InstRW<[M4WriteLC,
 702               M4WriteLH,
 703               WriteAdr],    (instrs LDPQpre)>;
 704
 705 // FP store instructions.
 706 def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
 707 def : InstRW<[WriteVST,
 708               WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
 709 def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
 710 def : InstRW<[M4WriteVSTK,
 711               ReadAdrBase], (instregex "^STR[BHSD]roW")>;
 712 def : InstRW<[M4WriteVSTK,
 713               ReadAdrBase], (instrs STRQroW)>;
 714 def : InstRW<[WriteVST,
 715               ReadAdrBase], (instregex "^STR[BHSD]roX")>;
 716 def : InstRW<[M4WriteVSTY,
 717               ReadAdrBase], (instrs STRQroX)>;
 718 def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
 719 def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>;
 720 def : InstRW<[WriteVST,
 721               WriteAdr],    (instregex "^STP[SD](post|pre)")>;
 722 def : InstRW<[M4WriteVSTJ,
 723               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 724
 725 // ASIMD instructions.
 726 def : InstRW<[M4WriteNHAD1],  (instregex "^[SU]ABDL?v")>;
 727 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]ABAL?v")>;
 728 def : InstRW<[M4WriteNMSC1],  (instregex "^ABSv")>;
 729 def : InstRW<[M4WriteNALU1],  (instregex "^(ADD|NEG|SUB)v")>;
 730 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]?ADDL?Pv")>;
 731 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]H(ADD|SUB)v")>;
 732 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU](ADD|SUB)[LW]v")>;
 733 def : InstRW<[M4WriteNHAD3],  (instregex "^R?(ADD|SUB)HN2?v")>;
 734 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]Q(ADD|SUB)v")>;
 735 def : InstRW<[M4WriteNHAD3],  (instregex "^(SU|US)QADDv")>;
 736 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]RHADDv")>;
 737 def : InstRW<[M4WriteNMSC1],  (instregex "^SQ(ABS|NEG)v")>;
 738 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]?ADDL?Vv")>;
 739 def : InstRW<[M4WriteNMSC1],  (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 740 def : InstRW<[M4WriteNALU1],  (instregex "^CMTSTv")>;
 741 def : InstRW<[M4WriteNALU1],  (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
 742 def : InstRW<[M4WriteNMSC1],  (instregex "^[SU](MIN|MAX)v")>;
 743 def : InstRW<[M4WriteNMSC2],  (instregex "^[SU](MIN|MAX)Pv")>;
 744 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU](MIN|MAX)Vv")>;
 745 def : InstRW<[M4WriteNMUL3,
 746               M4ReadNMULM1],  (instregex "^ML[AS]v")>;
 747 def : InstRW<[M4WriteNMUL3,
 748               M4ReadNMULM1],  (instregex "^(SQR?D)?MULH?v")>;
 749 def : InstRW<[M4WriteNMUL3,
 750               M4ReadNMULM1],  (instregex "^SQRDML[AS]H")>;
 751 def : InstRW<[M4WriteNMUL3,
 752               M4ReadNMULM1],  (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
 753 def : InstRW<[M4WriteNMUL3,
 754               M4ReadNMULP2],  (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
 755 def : InstRW<[M4WriteNMUL3,
 756               M4ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
 757 def : InstRW<[M4WriteNMUL3,
 758               M4ReadNMULP2],  (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
 759 def : InstRW<[M4WriteNMUL3],  (instregex "^[SU]DOT(lane)?v")>;
 760 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]ADALPv")>;
 761 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
 762 def : InstRW<[M4WriteNSHT1],  (instregex "^SHL[dv]")>;
 763 def : InstRW<[M4WriteNSHT1],  (instregex "^S[LR]I[dv]")>;
 764 def : InstRW<[M4WriteNSHT1],  (instregex "^[SU]SH[LR][dv]")>;
 765 def : InstRW<[M4WriteNSHT2],  (instregex "^[SU]?SHLLv")>;
 766 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
 767 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
 768 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
 769
 770 // ASIMD FP instructions.
 771 def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>;
 772 def : InstRW<[M4WriteNSHF1],  (instregex "^FABSv.f(32|64)")>;
 773 def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>;
 774 def : InstRW<[M4WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>;
 775 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>;
 776 def : InstRW<[M4WriteFADD2],  (instregex "^FADDPv.f(32|64)")>;
 777 def : InstRW<[M4WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 778 def : InstRW<[M4WriteFCVT2],  (instregex "^FCVT(L|N|XN)v")>;
 779 def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
 780 def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>;
 781 def : InstRW<[M4WriteFCVT2],  (instregex "^[SU]CVTFv.[fi](32|64)")>;
 782 def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>;
 783 def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>;
 784 def : InstRW<[M4WriteFDIV7],  (instrs FDIVv2f32)>;
 785 def : InstRW<[M4WriteNEONV],  (instrs FDIVv4f32)>;
 786 def : InstRW<[M4WriteNEONW],  (instrs FDIVv2f64)>;
 787 def : InstRW<[M4WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 788 def : InstRW<[M4WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 789 def : InstRW<[M4WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 790 def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>;
 791 def : InstRW<[M4WriteFMAC3],  (instregex "^FMULX?v.[fi](32|64)")>;
 792 def : InstRW<[M4WriteFMAC4H,
 793               M4ReadFMACM1],  (instregex "^FML[AS]v.[fi]16")>;
 794 def : InstRW<[M4WriteFMAC4,
 795               M4ReadFMACM1],  (instregex "^FML[AS]v.[fi](32|64)")>;
 796 def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>;
 797 def : InstRW<[M4WriteNALU1],  (instregex "^FNEGv.f(32|64)")>;
 798 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 799 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>;
 800 def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>;
 801 def : InstRW<[M4WriteFSQR8],  (instrs FSQRTv2f32)>;
 802 def : InstRW<[M4WriteNEONX],  (instrs FSQRTv4f32)>;
 803 def : InstRW<[M4WriteNEONY],  (instrs FSQRTv2f64)>;
 804
 805 // ASIMD miscellaneous instructions.
 806 def : InstRW<[M4WriteNALU1],  (instregex "^RBITv")>;
 807 def : InstRW<[M4WriteNALU1],  (instregex "^(BIF|BIT|BSL)v")>;
 808 def : InstRW<[M4WriteNALU1],  (instregex "^CL[STZ]v")>;
 809 def : InstRW<[M4WriteNEONB],  (instregex "^DUPv.+gpr")>;
 810 def : InstRW<[M4WriteNSHF1],  (instregex "^CPY")>;
 811 def : InstRW<[M4WriteNSHF1],  (instregex "^DUPv.+lane")>;
 812 def : InstRW<[M4WriteNSHF1],  (instregex "^EXTv")>;
 813 def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>;
 814 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
 815 def : InstRW<[M4WriteNEONB],  (instregex "^INSv.+gpr")>;
 816 def : InstRW<[M4WriteNSHF1],  (instregex "^INSv.+lane")>;
 817 def : InstRW<[M4WriteMOVI],   (instregex "^(MOV|MVN)I")>;
 818 def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>;
 819 def : InstRW<[M4WriteNALU1],  (instregex "^FMOVv.f(32|64)")>;
 820 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
 821 def : InstRW<[M4WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
 822 def : InstRW<[M4WriteFCVT3],  (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
 823 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>;
 824 def : InstRW<[M4WriteFMAC4],  (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
 825 def : InstRW<[M4WriteNSHF1],  (instregex "^REV(16|32|64)v")>;
 826 def : InstRW<[M4WriteNSHFA],  (instregex "^TB[LX]v(8|16)i8One")>;
 827 def : InstRW<[M4WriteNSHFB],  (instregex "^TB[LX]v(8|16)i8Two")>;
 828 def : InstRW<[M4WriteNSHFC],  (instregex "^TB[LX]v(8|16)i8Three")>;
 829 def : InstRW<[M4WriteNSHFD],  (instregex "^TB[LX]v(8|16)i8Four")>;
 830 def : InstRW<[M4WriteNEONP],  (instregex "^[SU]MOVv")>;
 831 def : InstRW<[M4WriteNSHF1],  (instregex "^(TRN|UZP|ZIP)[12]v")>;
 832
 833 // ASIMD load instructions.
 834 def : InstRW<[WriteVLD],    (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 835 def : InstRW<[WriteVLD,
 836               M4WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 837 def : InstRW<[WriteVLD],    (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 838 def : InstRW<[WriteVLD,
 839               M4WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 840
 841 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 842 def : InstRW<[M4WriteVLDA,
 843               M4WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 844 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 845 def : InstRW<[M4WriteVLDA,
 846               M4WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 847
 848 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 849 def : InstRW<[M4WriteVLDB,
 850               M4WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 851 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 852 def : InstRW<[M4WriteVLDB,
 853               M4WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 854
 855 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 856 def : InstRW<[M4WriteVLDC,
 857               M4WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 858 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 859 def : InstRW<[M4WriteVLDC,
 860               M4WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 861
 862 def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
 863 def : InstRW<[M4WriteVLDD,
 864               M4WriteA1],   (instregex "LD1i(8|16|32|64)_POST$")>;
 865
 866 def : InstRW<[WriteVLD],    (instregex "LD1Rv(8b|4h|2s|1d)$")>;
 867 def : InstRW<[WriteVLD,
 868               M4WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
 869 def : InstRW<[WriteVLD],    (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 870 def : InstRW<[WriteVLD,
 871               M4WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 872
 873 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
 874 def : InstRW<[M4WriteVLDF,
 875               M4WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 876 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 877 def : InstRW<[M4WriteVLDF,
 878               M4WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
 879
 880 def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
 881 def : InstRW<[M4WriteVLDG,
 882               M4WriteA1],   (instregex "LD2i(8|16|32|64)_POST$")>;
 883
 884 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
 885 def : InstRW<[M4WriteVLDA,
 886               M4WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
 887 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 888 def : InstRW<[M4WriteVLDA,
 889               M4WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 890
 891 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
 892 def : InstRW<[M4WriteVLDI,
 893               M4WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 894 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
 895 def : InstRW<[M4WriteVLDI,
 896               M4WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
 897
 898 def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 899 def : InstRW<[M4WriteVLDJ,
 900               M4WriteA1],   (instregex "LD3i(8|16|32)_POST$")>;
 901 def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>;
 902 def : InstRW<[M4WriteVLDL,
 903               M4WriteA1],   (instregex "LD3i64_POST$")>;
 904
 905 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
 906 def : InstRW<[M4WriteVLDB,
 907               M4WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
 908 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
 909 def : InstRW<[M4WriteVLDB,
 910               M4WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
 911
 912 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
 913 def : InstRW<[M4WriteVLDN,
 914               M4WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 915 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
 916 def : InstRW<[M4WriteVLDN,
 917               M4WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
 918
 919 def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 920 def : InstRW<[M4WriteVLDK,
 921               M4WriteA1],   (instregex "LD4i(8|16|32)_POST$")>;
 922 def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>;
 923 def : InstRW<[M4WriteVLDM,
 924               M4WriteA1],   (instregex "LD4i64_POST$")>;
 925
 926 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
 927 def : InstRW<[M4WriteVLDC,
 928               M4WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
 929 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
 930 def : InstRW<[M4WriteVLDC,
 931               M4WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
 932
 933 // ASIMD store instructions.
 934 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 935 def : InstRW<[WriteVST,
 936               M4WriteA1],   (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 937 def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 938 def : InstRW<[WriteVST,
 939               M4WriteA1],   (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 940
 941 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 942 def : InstRW<[M4WriteVSTA,
 943               M4WriteA1],   (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 944 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 945 def : InstRW<[M4WriteVSTA,
 946               M4WriteA1],   (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 947
 948 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 949 def : InstRW<[M4WriteVSTB,
 950               M4WriteA1],   (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 951 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 952 def : InstRW<[M4WriteVSTB,
 953               M4WriteA1],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 954
 955 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 956 def : InstRW<[M4WriteVSTC,
 957               M4WriteA1],   (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 958 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 959 def : InstRW<[M4WriteVSTC,
 960               M4WriteA1],   (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 961
 962 def : InstRW<[WriteVST],    (instregex "ST1i(8|16|32|64)$")>;
 963 def : InstRW<[WriteVST,
 964               M4WriteA1],   (instregex "ST1i(8|16|32|64)_POST$")>;
 965
 966 def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 967 def : InstRW<[M4WriteVSTD,
 968               M4WriteA1],   (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 969 def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 970 def : InstRW<[M4WriteVSTE,
 971               M4WriteA1],   (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
 972
 973 def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
 974 def : InstRW<[M4WriteVSTD,
 975               M4WriteA1],   (instregex "ST2i(8|16|32|64)_POST$")>;
 976
 977 def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 978 def : InstRW<[M4WriteVSTF,
 979               M4WriteA1],   (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 980 def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 981 def : InstRW<[M4WriteVSTG,
 982               M4WriteA1],   (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
 983
 984 def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>;
 985 def : InstRW<[M4WriteVSTE,
 986               M4WriteA1],   (instregex "ST3i(8|16|32|64)_POST$")>;
 987
 988 def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
 989 def : InstRW<[M4WriteVSTL,
 990               M4WriteA1],   (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 991 def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 992 def : InstRW<[M4WriteVSTI,
 993               M4WriteA1],   (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
 994
 995 def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>;
 996 def : InstRW<[M4WriteVSTE,
 997               M4WriteA1],   (instregex "ST4i(8|16|32|64)_POST$")>;
 998
 999 // Cryptography instructions.
1000 def : InstRW<[M4WriteNCRY1],  (instregex "^AES[DE]")>;
1001 def : InstRW<[M4WriteNCRY1,
1002               M4ReadAESM1],   (instregex "^AESI?MC")>;
1003 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>;
1004 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
1005 def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
1006 def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
1007 def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>;
1008 def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>;
1009 def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>;
1010
1011 // CRC instructions.
1012 def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>;
1013
1014 } // SchedModel = ExynosM4Model