1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //===----------------------------------------------------------------------===//
13 #include "AArch64Subtarget.h"
16 #include "AArch64CallLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64LegalizerInfo.h"
19 #include "AArch64PBQPRegAlloc.h"
20 #include "AArch64RegisterBankInfo.h"
21 #include "AArch64TargetMachine.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
30 #define DEBUG_TYPE "aarch64-subtarget"
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38 "converter pass"), cl::init(true), cl::Hidden);
40 // If OS supports TBI, use this flag to enable it.
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43 "an address is ignored"), cl::init(false), cl::Hidden);
46 UseNonLazyBind("aarch64-enable-nonlazybind",
47 cl::desc("Call nonlazybind functions via direct GOT load"),
48 cl::init(false), cl::Hidden);
51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
52 StringRef CPUString) {
53 // Determine default and user-specified characteristics
55 if (CPUString.empty())
56 CPUString = "generic";
58 ParseSubtargetFeatures(CPUString, FS);
59 initializeProperties();
64 void AArch64Subtarget::initializeProperties() {
65 // Initialize CPU specific properties. We should add a tablegen feature for
66 // this in the future so we can specify it together with the subtarget
68 switch (ARMProcFamily) {
74 PrefFunctionLogAlignment = 3;
79 MaxInterleaveFactor = 4;
80 PrefFunctionLogAlignment = 4;
83 PrefFunctionLogAlignment = 3;
89 PrefFunctionLogAlignment = 4;
97 PrefetchDistance = 280;
98 MinPrefetchStride = 2048;
99 MaxPrefetchIterationsAhead = 3;
102 MaxInterleaveFactor = 4;
103 MaxJumpTableSize = 20;
104 PrefFunctionLogAlignment = 5;
105 PrefLoopLogAlignment = 4;
108 MaxInterleaveFactor = 4;
109 // FIXME: remove this to enable 64-bit SLP if performance looks good.
110 MinVectorRegisterBitWidth = 128;
112 PrefetchDistance = 820;
113 MinPrefetchStride = 2048;
114 MaxPrefetchIterationsAhead = 8;
117 MaxInterleaveFactor = 4;
118 VectorInsertExtractBaseCost = 2;
120 PrefetchDistance = 740;
121 MinPrefetchStride = 1024;
122 MaxPrefetchIterationsAhead = 11;
123 // FIXME: remove this to enable 64-bit SLP if performance looks good.
124 MinVectorRegisterBitWidth = 128;
127 PrefFunctionLogAlignment = 3;
130 PrefFunctionLogAlignment = 4;
133 MaxInterleaveFactor = 4;
134 // FIXME: remove this to enable 64-bit SLP if performance looks good.
135 MinVectorRegisterBitWidth = 128;
139 PrefFunctionLogAlignment = 3;
140 PrefLoopLogAlignment = 2;
141 MaxInterleaveFactor = 4;
142 PrefetchDistance = 128;
143 MinPrefetchStride = 1024;
144 MaxPrefetchIterationsAhead = 4;
145 // FIXME: remove this to enable 64-bit SLP if performance looks good.
146 MinVectorRegisterBitWidth = 128;
153 PrefFunctionLogAlignment = 3;
154 PrefLoopLogAlignment = 2;
155 // FIXME: remove this to enable 64-bit SLP if performance looks good.
156 MinVectorRegisterBitWidth = 128;
160 PrefFunctionLogAlignment = 4;
161 PrefLoopLogAlignment = 2;
166 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
167 const std::string &FS,
168 const TargetMachine &TM, bool LittleEndian)
169 : AArch64GenSubtargetInfo(TT, CPU, FS),
170 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
171 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
172 IsLittle(LittleEndian),
173 TargetTriple(TT), FrameLowering(),
174 InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
176 if (AArch64::isX18ReservedByDefault(TT))
177 ReserveXRegister.set(18);
179 CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
180 Legalizer.reset(new AArch64LegalizerInfo(*this));
182 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
184 // FIXME: At this point, we can't rely on Subtarget having RBI.
185 // It's awkward to mix passing RBI and the Subtarget; should we pass
187 InstSelector.reset(createAArch64InstructionSelector(
188 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
190 RegBankInfo.reset(RBI);
193 const CallLowering *AArch64Subtarget::getCallLowering() const {
194 return CallLoweringInfo.get();
197 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
198 return InstSelector.get();
201 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
202 return Legalizer.get();
205 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
206 return RegBankInfo.get();
209 /// Find the target operand flags that describe how a global value should be
210 /// referenced for the current subtarget.
212 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
213 const TargetMachine &TM) const {
214 // MachO large model always goes via a GOT, simply to get a single 8-byte
215 // absolute relocation on all global addresses.
216 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
217 return AArch64II::MO_GOT;
219 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
220 if (GV->hasDLLImportStorageClass())
221 return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
222 if (getTargetTriple().isOSWindows())
223 return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
224 return AArch64II::MO_GOT;
227 // The small code model's direct accesses use ADRP, which cannot
228 // necessarily produce the value 0 (if the code is above 4GB).
229 // Same for the tiny code model, where we have a pc relative LDR.
230 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
231 GV->hasExternalWeakLinkage())
232 return AArch64II::MO_GOT;
234 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
235 // that their nominal addresses are tagged and outside of the code model. In
236 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
237 // tag if necessary based on MO_TAGGED.
238 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
239 return AArch64II::MO_NC | AArch64II::MO_TAGGED;
241 return AArch64II::MO_NO_FLAG;
244 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
245 const GlobalValue *GV, const TargetMachine &TM) const {
246 // MachO large model always goes via a GOT, because we don't have the
247 // relocations available to do anything else..
248 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
249 !GV->hasInternalLinkage())
250 return AArch64II::MO_GOT;
252 // NonLazyBind goes via GOT unless we know it's available locally.
253 auto *F = dyn_cast<Function>(GV);
254 if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
255 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
256 return AArch64II::MO_GOT;
258 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
259 if (getTargetTriple().isOSWindows())
260 return ClassifyGlobalReference(GV, TM);
262 return AArch64II::MO_NO_FLAG;
265 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
266 unsigned NumRegionInstrs) const {
267 // LNT run (at least on Cyclone) showed reasonably significant gains for
268 // bi-directional scheduling. 253.perlbmk.
269 Policy.OnlyTopDown = false;
270 Policy.OnlyBottomUp = false;
271 // Enabling or Disabling the latency heuristic is a close call: It seems to
272 // help nearly no benchmark on out-of-order architectures, on the other hand
273 // it regresses register pressure on a few benchmarking.
274 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
277 bool AArch64Subtarget::enableEarlyIfConversion() const {
278 return EnableEarlyIfConvert;
281 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
282 if (!UseAddressTopByteIgnored)
285 if (TargetTriple.isiOS()) {
286 unsigned Major, Minor, Micro;
287 TargetTriple.getiOSVersion(Major, Minor, Micro);
294 std::unique_ptr<PBQPRAConstraint>
295 AArch64Subtarget::getCustomPBQPConstraints() const {
296 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
299 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
300 // We usually compute max call frame size after ISel. Do the computation now
301 // if the .mir file didn't specify it. Note that this will probably give you
302 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
303 // instructions, specify explicitly if you need it to be correct.
304 MachineFrameInfo &MFI = MF.getFrameInfo();
305 if (!MFI.isMaxCallFrameSizeComputed())
306 MFI.computeMaxCallFrameSize(MF);