1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //===----------------------------------------------------------------------===//
13 #include "AArch64Subtarget.h"
16 #include "AArch64CallLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64LegalizerInfo.h"
19 #include "AArch64PBQPRegAlloc.h"
20 #include "AArch64RegisterBankInfo.h"
21 #include "AArch64TargetMachine.h"
22 #include "MCTargetDesc/AArch64AddressingModes.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/TargetParser.h"
30 #define DEBUG_TYPE "aarch64-subtarget"
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38 "converter pass"), cl::init(true), cl::Hidden);
40 // If OS supports TBI, use this flag to enable it.
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43 "an address is ignored"), cl::init(false), cl::Hidden);
46 UseNonLazyBind("aarch64-enable-nonlazybind",
47 cl::desc("Call nonlazybind functions via direct GOT load"),
48 cl::init(false), cl::Hidden);
51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
52 StringRef CPUString) {
53 // Determine default and user-specified characteristics
55 if (CPUString.empty())
56 CPUString = "generic";
58 ParseSubtargetFeatures(CPUString, FS);
59 initializeProperties();
64 void AArch64Subtarget::initializeProperties() {
65 // Initialize CPU specific properties. We should add a tablegen feature for
66 // this in the future so we can specify it together with the subtarget
68 switch (ARMProcFamily) {
74 PrefFunctionLogAlignment = 3;
79 MaxInterleaveFactor = 4;
80 PrefFunctionLogAlignment = 4;
83 PrefFunctionLogAlignment = 3;
89 PrefFunctionLogAlignment = 4;
97 PrefetchDistance = 280;
98 MinPrefetchStride = 2048;
99 MaxPrefetchIterationsAhead = 3;
102 MaxInterleaveFactor = 4;
103 MaxJumpTableSize = 20;
104 PrefFunctionLogAlignment = 5;
105 PrefLoopLogAlignment = 4;
108 MaxInterleaveFactor = 4;
109 // FIXME: remove this to enable 64-bit SLP if performance looks good.
110 MinVectorRegisterBitWidth = 128;
112 PrefetchDistance = 820;
113 MinPrefetchStride = 2048;
114 MaxPrefetchIterationsAhead = 8;
117 MaxInterleaveFactor = 4;
118 VectorInsertExtractBaseCost = 2;
120 PrefetchDistance = 740;
121 MinPrefetchStride = 1024;
122 MaxPrefetchIterationsAhead = 11;
123 // FIXME: remove this to enable 64-bit SLP if performance looks good.
124 MinVectorRegisterBitWidth = 128;
127 PrefFunctionLogAlignment = 3;
130 PrefFunctionLogAlignment = 4;
133 MaxInterleaveFactor = 4;
134 // FIXME: remove this to enable 64-bit SLP if performance looks good.
135 MinVectorRegisterBitWidth = 128;
139 PrefFunctionLogAlignment = 3;
140 PrefLoopLogAlignment = 2;
141 MaxInterleaveFactor = 4;
142 PrefetchDistance = 128;
143 MinPrefetchStride = 1024;
144 MaxPrefetchIterationsAhead = 4;
145 // FIXME: remove this to enable 64-bit SLP if performance looks good.
146 MinVectorRegisterBitWidth = 128;
153 PrefFunctionLogAlignment = 3;
154 PrefLoopLogAlignment = 2;
155 // FIXME: remove this to enable 64-bit SLP if performance looks good.
156 MinVectorRegisterBitWidth = 128;
160 PrefFunctionLogAlignment = 4;
161 PrefLoopLogAlignment = 2;
165 PrefFunctionLogAlignment = 4;
166 PrefLoopLogAlignment = 2;
167 MaxInterleaveFactor = 4;
168 PrefetchDistance = 128;
169 MinPrefetchStride = 1024;
170 MaxPrefetchIterationsAhead = 4;
171 // FIXME: remove this to enable 64-bit SLP if performance looks good.
172 MinVectorRegisterBitWidth = 128;
177 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
178 const std::string &FS,
179 const TargetMachine &TM, bool LittleEndian)
180 : AArch64GenSubtargetInfo(TT, CPU, FS),
181 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
182 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
183 IsLittle(LittleEndian),
184 TargetTriple(TT), FrameLowering(),
185 InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
187 if (AArch64::isX18ReservedByDefault(TT))
188 ReserveXRegister.set(18);
190 CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
191 Legalizer.reset(new AArch64LegalizerInfo(*this));
193 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
195 // FIXME: At this point, we can't rely on Subtarget having RBI.
196 // It's awkward to mix passing RBI and the Subtarget; should we pass
198 InstSelector.reset(createAArch64InstructionSelector(
199 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
201 RegBankInfo.reset(RBI);
204 const CallLowering *AArch64Subtarget::getCallLowering() const {
205 return CallLoweringInfo.get();
208 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
209 return InstSelector.get();
212 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
213 return Legalizer.get();
216 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
217 return RegBankInfo.get();
220 /// Find the target operand flags that describe how a global value should be
221 /// referenced for the current subtarget.
223 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
224 const TargetMachine &TM) const {
225 // MachO large model always goes via a GOT, simply to get a single 8-byte
226 // absolute relocation on all global addresses.
227 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
228 return AArch64II::MO_GOT;
230 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
231 if (GV->hasDLLImportStorageClass())
232 return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
233 if (getTargetTriple().isOSWindows())
234 return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
235 return AArch64II::MO_GOT;
238 // The small code model's direct accesses use ADRP, which cannot
239 // necessarily produce the value 0 (if the code is above 4GB).
240 // Same for the tiny code model, where we have a pc relative LDR.
241 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
242 GV->hasExternalWeakLinkage())
243 return AArch64II::MO_GOT;
245 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
246 // that their nominal addresses are tagged and outside of the code model. In
247 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
248 // tag if necessary based on MO_TAGGED.
249 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
250 return AArch64II::MO_NC | AArch64II::MO_TAGGED;
252 return AArch64II::MO_NO_FLAG;
255 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
256 const GlobalValue *GV, const TargetMachine &TM) const {
257 // MachO large model always goes via a GOT, because we don't have the
258 // relocations available to do anything else..
259 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
260 !GV->hasInternalLinkage())
261 return AArch64II::MO_GOT;
263 // NonLazyBind goes via GOT unless we know it's available locally.
264 auto *F = dyn_cast<Function>(GV);
265 if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
266 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
267 return AArch64II::MO_GOT;
269 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
270 if (getTargetTriple().isOSWindows())
271 return ClassifyGlobalReference(GV, TM);
273 return AArch64II::MO_NO_FLAG;
276 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
277 unsigned NumRegionInstrs) const {
278 // LNT run (at least on Cyclone) showed reasonably significant gains for
279 // bi-directional scheduling. 253.perlbmk.
280 Policy.OnlyTopDown = false;
281 Policy.OnlyBottomUp = false;
282 // Enabling or Disabling the latency heuristic is a close call: It seems to
283 // help nearly no benchmark on out-of-order architectures, on the other hand
284 // it regresses register pressure on a few benchmarking.
285 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
288 bool AArch64Subtarget::enableEarlyIfConversion() const {
289 return EnableEarlyIfConvert;
292 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
293 if (!UseAddressTopByteIgnored)
296 if (TargetTriple.isiOS()) {
297 unsigned Major, Minor, Micro;
298 TargetTriple.getiOSVersion(Major, Minor, Micro);
305 std::unique_ptr<PBQPRAConstraint>
306 AArch64Subtarget::getCustomPBQPConstraints() const {
307 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
310 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
311 // We usually compute max call frame size after ISel. Do the computation now
312 // if the .mir file didn't specify it. Note that this will probably give you
313 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
314 // instructions, specify explicitly if you need it to be correct.
315 MachineFrameInfo &MFI = MF.getFrameInfo();
316 if (!MFI.isMaxCallFrameSizeComputed())
317 MFI.computeMaxCallFrameSize(MF);