1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "AArch64TargetMachine.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "TargetInfo/AArch64TargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/CSEConfigBase.h"
25 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
28 #include "llvm/CodeGen/GlobalISel/Localizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
30 #include "llvm/CodeGen/MIRParser/MIParser.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCTargetOptions.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/CFGuard.h"
46 #include "llvm/Transforms/Scalar.h"
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53 cl::desc("Enable the CCMP formation pass"),
54 cl::init(true), cl::Hidden);
57 EnableCondBrTuning("aarch64-enable-cond-br-tune",
58 cl::desc("Enable the conditional branch tuning pass"),
59 cl::init(true), cl::Hidden);
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62 cl::desc("Enable the machine combiner pass"),
63 cl::init(true), cl::Hidden);
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66 cl::desc("Suppress STP for AArch64"),
67 cl::init(true), cl::Hidden);
69 static cl::opt<bool> EnableAdvSIMDScalar(
70 "aarch64-enable-simd-scalar",
71 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72 cl::init(false), cl::Hidden);
75 EnablePromoteConstant("aarch64-enable-promote-const",
76 cl::desc("Enable the promote constant pass"),
77 cl::init(true), cl::Hidden);
79 static cl::opt<bool> EnableCollectLOH(
80 "aarch64-enable-collect-loh",
81 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82 cl::init(true), cl::Hidden);
85 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86 cl::desc("Enable the pass that removes dead"
87 " definitons and replaces stores to"
88 " them with stores to the zero"
92 static cl::opt<bool> EnableRedundantCopyElimination(
93 "aarch64-enable-copyelim",
94 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98 cl::desc("Enable the load/store pair"
99 " optimization pass"),
100 cl::init(true), cl::Hidden);
102 static cl::opt<bool> EnableAtomicTidy(
103 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104 cl::desc("Run SimplifyCFG after expanding atomic operations"
105 " to make use of cmpxchg flow-based information"),
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110 cl::desc("Run early if-conversion"),
114 EnableCondOpt("aarch64-enable-condopt",
115 cl::desc("Enable the condition optimizer pass"),
116 cl::init(true), cl::Hidden);
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120 cl::desc("Work around Cortex-A53 erratum 835769"),
124 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125 cl::desc("Enable optimizations on complex GEPs"),
129 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130 cl::desc("Relax out of range conditional branches"));
132 static cl::opt<bool> EnableCompressJumpTables(
133 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134 cl::desc("Use smallest entry possible for jump tables"));
136 // FIXME: Unify control over GlobalMerge.
137 static cl::opt<cl::boolOrDefault>
138 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139 cl::desc("Enable the global merge pass"));
142 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143 cl::desc("Enable the loop data prefetch pass"),
146 static cl::opt<int> EnableGlobalISelAtO(
147 "aarch64-enable-global-isel-at-O", cl::Hidden,
148 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
151 static cl::opt<bool> EnableSVEIntrinsicOpts(
152 "aarch64-sve-intrinsic-opts", cl::Hidden,
153 cl::desc("Enable SVE intrinsic opts"),
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157 cl::init(true), cl::Hidden);
160 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161 cl::desc("Enable the AAcrh64 branch target pass"),
164 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
165 // Register the target.
166 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
167 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
168 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
169 RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
170 RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
171 auto PR = PassRegistry::getPassRegistry();
172 initializeGlobalISel(*PR);
173 initializeAArch64A53Fix835769Pass(*PR);
174 initializeAArch64A57FPLoadBalancingPass(*PR);
175 initializeAArch64AdvSIMDScalarPass(*PR);
176 initializeAArch64BranchTargetsPass(*PR);
177 initializeAArch64CollectLOHPass(*PR);
178 initializeAArch64CompressJumpTablesPass(*PR);
179 initializeAArch64ConditionalComparesPass(*PR);
180 initializeAArch64ConditionOptimizerPass(*PR);
181 initializeAArch64DeadRegisterDefinitionsPass(*PR);
182 initializeAArch64ExpandPseudoPass(*PR);
183 initializeAArch64LoadStoreOptPass(*PR);
184 initializeAArch64SIMDInstrOptPass(*PR);
185 initializeAArch64PreLegalizerCombinerPass(*PR);
186 initializeAArch64PostLegalizerCombinerPass(*PR);
187 initializeAArch64PromoteConstantPass(*PR);
188 initializeAArch64RedundantCopyEliminationPass(*PR);
189 initializeAArch64StorePairSuppressPass(*PR);
190 initializeFalkorHWPFFixPass(*PR);
191 initializeFalkorMarkStridedAccessesLegacyPass(*PR);
192 initializeLDTLSCleanupPass(*PR);
193 initializeSVEIntrinsicOptsPass(*PR);
194 initializeAArch64SpeculationHardeningPass(*PR);
195 initializeAArch64SLSHardeningPass(*PR);
196 initializeAArch64StackTaggingPass(*PR);
197 initializeAArch64StackTaggingPreRAPass(*PR);
200 //===----------------------------------------------------------------------===//
201 // AArch64 Lowering public interface.
202 //===----------------------------------------------------------------------===//
203 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
204 if (TT.isOSBinFormatMachO())
205 return std::make_unique<AArch64_MachoTargetObjectFile>();
206 if (TT.isOSBinFormatCOFF())
207 return std::make_unique<AArch64_COFFTargetObjectFile>();
209 return std::make_unique<AArch64_ELFTargetObjectFile>();
212 // Helper function to build a DataLayout string
213 static std::string computeDataLayout(const Triple &TT,
214 const MCTargetOptions &Options,
216 if (Options.getABIName() == "ilp32")
217 return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
218 if (TT.isOSBinFormatMachO()) {
219 if (TT.getArch() == Triple::aarch64_32)
220 return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
221 return "e-m:o-i64:64-i128:128-n32:64-S128";
223 if (TT.isOSBinFormatCOFF())
224 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
226 return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
227 return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
230 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
231 Optional<Reloc::Model> RM) {
232 // AArch64 Darwin and Windows are always PIC.
233 if (TT.isOSDarwin() || TT.isOSWindows())
235 // On ELF platforms the default static relocation model has a smart enough
236 // linker to cope with referencing external symbols defined in a shared
237 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
238 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
239 return Reloc::Static;
243 static CodeModel::Model
244 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
247 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
248 *CM != CodeModel::Large) {
250 "Only small, tiny and large code models are allowed on AArch64");
251 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
252 report_fatal_error("tiny code model is only supported on ELF");
255 // The default MCJIT memory managers make no guarantees about where they can
256 // find an executable page; JITed code needs to be able to refer to globals
257 // no matter how far away they are.
258 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
259 // since with large code model LLVM generating 4 MOV instructions, and
260 // Windows doesn't support relocating these long branch (4 MOVs).
261 if (JIT && !TT.isOSWindows())
262 return CodeModel::Large;
263 return CodeModel::Small;
266 /// Create an AArch64 architecture model.
268 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
269 StringRef CPU, StringRef FS,
270 const TargetOptions &Options,
271 Optional<Reloc::Model> RM,
272 Optional<CodeModel::Model> CM,
273 CodeGenOpt::Level OL, bool JIT,
275 : LLVMTargetMachine(T,
276 computeDataLayout(TT, Options.MCOptions, LittleEndian),
277 TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
278 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
279 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
282 if (TT.isOSBinFormatMachO()) {
283 this->Options.TrapUnreachable = true;
284 this->Options.NoTrapAfterNoreturn = true;
287 if (getMCAsmInfo()->usesWindowsCFI()) {
288 // Unwinding can get confused if the last instruction in an
289 // exception-handling region (function, funclet, try block, etc.)
292 // FIXME: We could elide the trap if the next instruction would be in
293 // the same region anyway.
294 this->Options.TrapUnreachable = true;
297 if (this->Options.TLSSize == 0) // default
298 this->Options.TLSSize = 24;
299 if ((getCodeModel() == CodeModel::Small ||
300 getCodeModel() == CodeModel::Kernel) &&
301 this->Options.TLSSize > 32)
302 // for the small (and kernel) code model, the maximum TLS size is 4GiB
303 this->Options.TLSSize = 32;
304 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
305 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
306 this->Options.TLSSize = 24;
308 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
309 // MachO/CodeModel::Large, which GlobalISel does not support.
310 if (getOptLevel() <= EnableGlobalISelAtO &&
311 TT.getArch() != Triple::aarch64_32 &&
312 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
314 setGlobalISelAbort(GlobalISelAbortMode::Disable);
317 // AArch64 supports the MachineOutliner.
318 setMachineOutliner(true);
320 // AArch64 supports default outlining behaviour.
321 setSupportsDefaultOutlining(true);
323 // AArch64 supports the debug entry values.
324 setSupportsDebugEntryValues(true);
327 AArch64TargetMachine::~AArch64TargetMachine() = default;
329 const AArch64Subtarget *
330 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
331 Attribute CPUAttr = F.getFnAttribute("target-cpu");
332 Attribute FSAttr = F.getFnAttribute("target-features");
334 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
335 ? CPUAttr.getValueAsString().str()
337 std::string FS = !FSAttr.hasAttribute(Attribute::None)
338 ? FSAttr.getValueAsString().str()
341 auto &I = SubtargetMap[CPU + FS];
343 // This needs to be done before we create a new subtarget since any
344 // creation will depend on the TM and the code generation flags on the
345 // function that reside in TargetOptions.
346 resetTargetOptions(F);
347 I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
353 void AArch64leTargetMachine::anchor() { }
355 AArch64leTargetMachine::AArch64leTargetMachine(
356 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
357 const TargetOptions &Options, Optional<Reloc::Model> RM,
358 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
359 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
361 void AArch64beTargetMachine::anchor() { }
363 AArch64beTargetMachine::AArch64beTargetMachine(
364 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
365 const TargetOptions &Options, Optional<Reloc::Model> RM,
366 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
367 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
371 /// AArch64 Code Generator Pass Configuration Options.
372 class AArch64PassConfig : public TargetPassConfig {
374 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
375 : TargetPassConfig(TM, PM) {
376 if (TM.getOptLevel() != CodeGenOpt::None)
377 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
380 AArch64TargetMachine &getAArch64TargetMachine() const {
381 return getTM<AArch64TargetMachine>();
385 createMachineScheduler(MachineSchedContext *C) const override {
386 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
387 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
388 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
389 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
391 DAG->addMutation(createAArch64MacroFusionDAGMutation());
396 createPostMachineScheduler(MachineSchedContext *C) const override {
397 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
398 if (ST.hasFusion()) {
399 // Run the Macro Fusion after RA again since literals are expanded from
400 // pseudos then (v. addPreSched2()).
401 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
402 DAG->addMutation(createAArch64MacroFusionDAGMutation());
409 void addIRPasses() override;
410 bool addPreISel() override;
411 bool addInstSelector() override;
412 bool addIRTranslator() override;
413 void addPreLegalizeMachineIR() override;
414 bool addLegalizeMachineIR() override;
415 void addPreRegBankSelect() override;
416 bool addRegBankSelect() override;
417 void addPreGlobalInstructionSelect() override;
418 bool addGlobalInstructionSelect() override;
419 bool addILPOpts() override;
420 void addPreRegAlloc() override;
421 void addPostRegAlloc() override;
422 void addPreSched2() override;
423 void addPreEmitPass() override;
425 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
428 } // end anonymous namespace
431 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
432 return TargetTransformInfo(AArch64TTIImpl(this, F));
435 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
436 return new AArch64PassConfig(*this, PM);
439 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
440 return getStandardCSEConfigForOpt(TM->getOptLevel());
443 void AArch64PassConfig::addIRPasses() {
444 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
446 addPass(createAtomicExpandPass());
448 // Expand any SVE vector library calls that we can't code generate directly.
449 if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
450 addPass(createSVEIntrinsicOptsPass());
452 // Cmpxchg instructions are often used with a subsequent comparison to
453 // determine whether it succeeded. We can exploit existing control-flow in
454 // ldrex/strex loops to simplify this, but it needs tidying up.
455 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
456 addPass(createCFGSimplificationPass(1, true, true, false, true));
458 // Run LoopDataPrefetch
460 // Run this before LSR to remove the multiplies involved in computing the
461 // pointer values N iterations ahead.
462 if (TM->getOptLevel() != CodeGenOpt::None) {
463 if (EnableLoopDataPrefetch)
464 addPass(createLoopDataPrefetchPass());
465 if (EnableFalkorHWPFFix)
466 addPass(createFalkorMarkStridedAccessesPass());
469 TargetPassConfig::addIRPasses();
471 addPass(createAArch64StackTaggingPass(
472 /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
474 // Match interleaved memory accesses to ldN/stN intrinsics.
475 if (TM->getOptLevel() != CodeGenOpt::None) {
476 addPass(createInterleavedLoadCombinePass());
477 addPass(createInterleavedAccessPass());
480 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
481 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
482 // and lower a GEP with multiple indices to either arithmetic operations or
483 // multiple GEPs with single index.
484 addPass(createSeparateConstOffsetFromGEPPass(true));
485 // Call EarlyCSE pass to find and remove subexpressions in the lowered
487 addPass(createEarlyCSEPass());
488 // Do loop invariant code motion in case part of the lowered result is
490 addPass(createLICMPass());
493 // Add Control Flow Guard checks.
494 if (TM->getTargetTriple().isOSWindows())
495 addPass(createCFGuardCheckPass());
498 // Pass Pipeline Configuration
499 bool AArch64PassConfig::addPreISel() {
500 // Run promote constant before global merge, so that the promoted constants
501 // get a chance to be merged
502 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
503 addPass(createAArch64PromoteConstantPass());
504 // FIXME: On AArch64, this depends on the type.
505 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
506 // and the offset has to be a multiple of the related size in bytes.
507 if ((TM->getOptLevel() != CodeGenOpt::None &&
508 EnableGlobalMerge == cl::BOU_UNSET) ||
509 EnableGlobalMerge == cl::BOU_TRUE) {
510 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
511 (EnableGlobalMerge == cl::BOU_UNSET);
513 // Merging of extern globals is enabled by default on non-Mach-O as we
514 // expect it to be generally either beneficial or harmless. On Mach-O it
515 // is disabled as we emit the .subsections_via_symbols directive which
516 // means that merging extern globals is not safe.
517 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
519 // FIXME: extern global merging is only enabled when we optimise for size
520 // because there are some regressions with it also enabled for performance.
521 if (!OnlyOptimizeForSize)
522 MergeExternalByDefault = false;
524 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
525 MergeExternalByDefault));
531 bool AArch64PassConfig::addInstSelector() {
532 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
534 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
535 // references to _TLS_MODULE_BASE_ as possible.
536 if (TM->getTargetTriple().isOSBinFormatELF() &&
537 getOptLevel() != CodeGenOpt::None)
538 addPass(createAArch64CleanupLocalDynamicTLSPass());
543 bool AArch64PassConfig::addIRTranslator() {
544 addPass(new IRTranslator());
548 void AArch64PassConfig::addPreLegalizeMachineIR() {
549 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
550 addPass(createAArch64PreLegalizeCombiner(IsOptNone));
553 bool AArch64PassConfig::addLegalizeMachineIR() {
554 addPass(new Legalizer());
558 void AArch64PassConfig::addPreRegBankSelect() {
559 // For now we don't add this to the pipeline for -O0. We could do in future
560 // if we split the combines into separate O0/opt groupings.
561 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
563 addPass(createAArch64PostLegalizeCombiner(IsOptNone));
566 bool AArch64PassConfig::addRegBankSelect() {
567 addPass(new RegBankSelect());
571 void AArch64PassConfig::addPreGlobalInstructionSelect() {
572 addPass(new Localizer());
575 bool AArch64PassConfig::addGlobalInstructionSelect() {
576 addPass(new InstructionSelect());
580 bool AArch64PassConfig::addILPOpts() {
582 addPass(createAArch64ConditionOptimizerPass());
584 addPass(createAArch64ConditionalCompares());
586 addPass(&MachineCombinerID);
587 if (EnableCondBrTuning)
588 addPass(createAArch64CondBrTuning());
589 if (EnableEarlyIfConversion)
590 addPass(&EarlyIfConverterID);
591 if (EnableStPairSuppress)
592 addPass(createAArch64StorePairSuppressPass());
593 addPass(createAArch64SIMDInstrOptPass());
594 if (TM->getOptLevel() != CodeGenOpt::None)
595 addPass(createAArch64StackTaggingPreRAPass());
599 void AArch64PassConfig::addPreRegAlloc() {
600 // Change dead register definitions to refer to the zero register.
601 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
602 addPass(createAArch64DeadRegisterDefinitions());
604 // Use AdvSIMD scalar instructions whenever profitable.
605 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
606 addPass(createAArch64AdvSIMDScalar());
607 // The AdvSIMD pass may produce copies that can be rewritten to
608 // be register coalescer friendly.
609 addPass(&PeepholeOptimizerID);
613 void AArch64PassConfig::addPostRegAlloc() {
614 // Remove redundant copy instructions.
615 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
616 addPass(createAArch64RedundantCopyEliminationPass());
618 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
619 // Improve performance for some FP/SIMD code for A57.
620 addPass(createAArch64A57FPLoadBalancing());
623 void AArch64PassConfig::addPreSched2() {
624 // Expand some pseudo instructions to allow proper scheduling.
625 addPass(createAArch64ExpandPseudoPass());
626 // Use load/store pair instructions when possible.
627 if (TM->getOptLevel() != CodeGenOpt::None) {
628 if (EnableLoadStoreOpt)
629 addPass(createAArch64LoadStoreOptimizationPass());
632 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
633 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
634 // Therefore, run the AArch64SpeculationHardeningPass before the
635 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
637 addPass(createAArch64SpeculationHardeningPass());
639 addPass(createAArch64IndirectThunks());
640 addPass(createAArch64SLSHardeningPass());
642 if (TM->getOptLevel() != CodeGenOpt::None) {
643 if (EnableFalkorHWPFFix)
644 addPass(createFalkorHWPFFixPass());
648 void AArch64PassConfig::addPreEmitPass() {
649 // Machine Block Placement might have created new opportunities when run
650 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
651 // Run the load/store optimizer once more.
652 if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
653 addPass(createAArch64LoadStoreOptimizationPass());
655 if (EnableA53Fix835769)
656 addPass(createAArch64A53Fix835769());
658 if (EnableBranchTargets)
659 addPass(createAArch64BranchTargetsPass());
661 // Relax conditional branch instructions if they're otherwise out of
662 // range of their destination.
663 if (BranchRelaxation)
664 addPass(&BranchRelaxationPassID);
666 // Identify valid longjmp targets for Windows Control Flow Guard.
667 if (TM->getTargetTriple().isOSWindows())
668 addPass(createCFGuardLongjmpPass());
670 if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
671 addPass(createAArch64CompressJumpTablesPass());
673 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
674 TM->getTargetTriple().isOSBinFormatMachO())
675 addPass(createAArch64CollectLOHPass());
677 // SVE bundles move prefixes with destructive operations.
678 addPass(createUnpackMachineBundles(nullptr));
681 yaml::MachineFunctionInfo *
682 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
683 return new yaml::AArch64FunctionInfo();
686 yaml::MachineFunctionInfo *
687 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
688 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
689 return new yaml::AArch64FunctionInfo(*MFI);
692 bool AArch64TargetMachine::parseMachineFunctionInfo(
693 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
694 SMDiagnostic &Error, SMRange &SourceRange) const {
695 const auto &YamlMFI =
696 reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
697 MachineFunction &MF = PFS.MF;
698 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);