1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "AArch64Disassembler.h"
13 #include "AArch64ExternalSymbolizer.h"
14 #include "MCTargetDesc/AArch64AddressingModes.h"
15 #include "MCTargetDesc/AArch64MCTargetDesc.h"
16 #include "TargetInfo/AArch64TargetInfo.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm-c/Disassembler.h"
19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
20 #include "llvm/MC/MCFixedLenDisassembler.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
33 #define DEBUG_TYPE "aarch64-disassembler"
35 // Pull DecodeStatus and its enum values into the global namespace.
36 using DecodeStatus = MCDisassembler::DecodeStatus;
38 // Forward declare these because the autogenerated code will reference them.
39 // Definitions are further down.
40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
41 unsigned RegNo, uint64_t Address,
43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
66 unsigned RegNo, uint64_t Address,
68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
72 unsigned RegNo, uint64_t Address,
74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
100 const void *Decoder);
101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
103 const void *Decoder);
104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
106 const void *Decoder);
107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
109 const void *Decoder);
110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
112 const void *Decoder);
113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
115 const void *Decoder);
117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
119 const void *Decoder);
120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
122 const void *Decoder);
123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
124 uint64_t Address, const void *Decoder);
125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
126 uint64_t Address, const void *Decoder);
127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
128 uint64_t Address, const void *Decoder);
129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
130 uint64_t Address, const void *Decoder);
131 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
133 const void *Decoder);
134 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
136 const void *Decoder);
137 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
139 const void *Decoder);
140 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
142 const void *Decoder);
143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
145 const void *Decoder);
146 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
148 const void *Decoder);
149 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
151 const void *Decoder);
152 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
154 const void *Decoder);
155 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
157 const void *Decoder);
158 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
160 const void *Decoder);
161 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
163 const void *Decoder);
164 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
170 const void *Decoder);
171 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
173 const void *Decoder);
174 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
175 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
179 const void *Decoder);
180 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
181 uint64_t Addr, const void *Decoder);
182 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
184 const void *Decoder);
185 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
186 uint64_t Addr, const void *Decoder);
187 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
189 const void *Decoder);
190 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
191 uint64_t Addr, const void *Decoder);
192 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
194 const void *Decoder);
195 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
196 uint64_t Addr, const void *Decoder);
197 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
198 uint64_t Addr, const void *Decoder);
199 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
200 uint64_t Addr, const void *Decoder);
201 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
202 uint64_t Addr, const void *Decoder);
203 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
204 uint64_t Addr, const void *Decoder);
205 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
212 const void *Decoder);
213 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
216 const void *Decoder);
218 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
219 uint64_t Address, const void *Decoder);
220 template <int ElementWidth>
221 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
222 uint64_t Addr, const void *Decoder);
223 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
224 uint64_t Addr, const void *Decoder);
226 static bool Check(DecodeStatus &Out, DecodeStatus In) {
228 case MCDisassembler::Success:
229 // Out stays the same.
231 case MCDisassembler::SoftFail:
234 case MCDisassembler::Fail:
238 llvm_unreachable("Invalid DecodeStatus!");
241 #include "AArch64GenDisassemblerTables.inc"
242 #include "AArch64GenInstrInfo.inc"
244 #define Success MCDisassembler::Success
245 #define Fail MCDisassembler::Fail
246 #define SoftFail MCDisassembler::SoftFail
248 static MCDisassembler *createAArch64Disassembler(const Target &T,
249 const MCSubtargetInfo &STI,
251 return new AArch64Disassembler(STI, Ctx);
254 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
255 ArrayRef<uint8_t> Bytes,
257 raw_ostream &CS) const {
261 // We want to read exactly 4 bytes of data.
262 if (Bytes.size() < 4)
266 // Encoded as a small-endian 32-bit word in the stream.
268 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
270 // Calling the auto-generated decoder function.
271 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
274 static MCSymbolizer *
275 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
276 LLVMSymbolLookupCallback SymbolLookUp,
277 void *DisInfo, MCContext *Ctx,
278 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
279 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
280 SymbolLookUp, DisInfo);
283 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
284 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
285 createAArch64Disassembler);
286 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
287 createAArch64Disassembler);
288 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
289 createAArch64ExternalSymbolizer);
290 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
291 createAArch64ExternalSymbolizer);
292 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
293 createAArch64Disassembler);
294 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
295 createAArch64ExternalSymbolizer);
297 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
298 createAArch64Disassembler);
299 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
300 createAArch64ExternalSymbolizer);
301 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
302 createAArch64Disassembler);
303 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
304 createAArch64ExternalSymbolizer);
307 static const unsigned FPR128DecoderTable[] = {
308 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
309 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
310 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
311 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
312 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
313 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
314 AArch64::Q30, AArch64::Q31
317 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
319 const void *Decoder) {
323 unsigned Register = FPR128DecoderTable[RegNo];
324 Inst.addOperand(MCOperand::createReg(Register));
328 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
330 const void *Decoder) {
333 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
336 static const unsigned FPR64DecoderTable[] = {
337 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
338 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
339 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
340 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
341 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
342 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
343 AArch64::D30, AArch64::D31
346 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
348 const void *Decoder) {
352 unsigned Register = FPR64DecoderTable[RegNo];
353 Inst.addOperand(MCOperand::createReg(Register));
357 static const unsigned FPR32DecoderTable[] = {
358 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
359 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
360 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
361 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
362 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
363 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
364 AArch64::S30, AArch64::S31
367 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
369 const void *Decoder) {
373 unsigned Register = FPR32DecoderTable[RegNo];
374 Inst.addOperand(MCOperand::createReg(Register));
378 static const unsigned FPR16DecoderTable[] = {
379 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
380 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
381 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
382 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
383 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
384 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
385 AArch64::H30, AArch64::H31
388 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
390 const void *Decoder) {
394 unsigned Register = FPR16DecoderTable[RegNo];
395 Inst.addOperand(MCOperand::createReg(Register));
399 static const unsigned FPR8DecoderTable[] = {
400 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
401 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
402 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
403 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
404 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
405 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
406 AArch64::B30, AArch64::B31
409 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
411 const void *Decoder) {
415 unsigned Register = FPR8DecoderTable[RegNo];
416 Inst.addOperand(MCOperand::createReg(Register));
420 static const unsigned GPR64DecoderTable[] = {
421 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
422 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
423 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
424 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
425 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
426 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
427 AArch64::LR, AArch64::XZR
430 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
432 const void *Decoder) {
436 unsigned Register = GPR64DecoderTable[RegNo];
437 Inst.addOperand(MCOperand::createReg(Register));
441 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
443 const void *Decoder) {
447 unsigned Register = GPR64DecoderTable[RegNo];
448 Inst.addOperand(MCOperand::createReg(Register));
452 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
454 const void *Decoder) {
457 unsigned Register = GPR64DecoderTable[RegNo];
458 if (Register == AArch64::XZR)
459 Register = AArch64::SP;
460 Inst.addOperand(MCOperand::createReg(Register));
464 static const unsigned GPR32DecoderTable[] = {
465 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
466 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
467 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
468 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
469 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
470 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
471 AArch64::W30, AArch64::WZR
474 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
476 const void *Decoder) {
480 unsigned Register = GPR32DecoderTable[RegNo];
481 Inst.addOperand(MCOperand::createReg(Register));
485 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
487 const void *Decoder) {
491 unsigned Register = GPR32DecoderTable[RegNo];
492 if (Register == AArch64::WZR)
493 Register = AArch64::WSP;
494 Inst.addOperand(MCOperand::createReg(Register));
497 static const unsigned ZPRDecoderTable[] = {
498 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
499 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
500 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
501 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
502 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
503 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
504 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
505 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
508 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
510 const void* Decoder) {
514 unsigned Register = ZPRDecoderTable[RegNo];
515 Inst.addOperand(MCOperand::createReg(Register));
519 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
521 const void *Decoder) {
524 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
527 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
529 const void *Decoder) {
532 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
535 static const unsigned ZZDecoderTable[] = {
536 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
537 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
538 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
539 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
540 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
541 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
542 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
543 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
546 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
548 const void* Decoder) {
551 unsigned Register = ZZDecoderTable[RegNo];
552 Inst.addOperand(MCOperand::createReg(Register));
556 static const unsigned ZZZDecoderTable[] = {
557 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
558 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
559 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
560 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
561 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
562 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
563 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
564 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
565 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
566 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
567 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
570 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
572 const void* Decoder) {
575 unsigned Register = ZZZDecoderTable[RegNo];
576 Inst.addOperand(MCOperand::createReg(Register));
580 static const unsigned ZZZZDecoderTable[] = {
581 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
582 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
583 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
584 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
585 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
586 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
587 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
588 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
589 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
590 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
591 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
594 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
596 const void* Decoder) {
599 unsigned Register = ZZZZDecoderTable[RegNo];
600 Inst.addOperand(MCOperand::createReg(Register));
604 static const unsigned PPRDecoderTable[] = {
605 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
606 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
607 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
608 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
611 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
612 uint64_t Addr, const void *Decoder) {
616 unsigned Register = PPRDecoderTable[RegNo];
617 Inst.addOperand(MCOperand::createReg(Register));
621 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
623 const void* Decoder) {
627 // Just reuse the PPR decode table
628 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
631 static const unsigned VectorDecoderTable[] = {
632 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
633 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
634 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
635 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
636 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
637 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
638 AArch64::Q30, AArch64::Q31
641 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
643 const void *Decoder) {
647 unsigned Register = VectorDecoderTable[RegNo];
648 Inst.addOperand(MCOperand::createReg(Register));
652 static const unsigned QQDecoderTable[] = {
653 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
654 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
655 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
656 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
657 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
658 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
659 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
660 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
663 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
664 uint64_t Addr, const void *Decoder) {
667 unsigned Register = QQDecoderTable[RegNo];
668 Inst.addOperand(MCOperand::createReg(Register));
672 static const unsigned QQQDecoderTable[] = {
673 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
674 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
675 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
676 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
677 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
678 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
679 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
680 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
681 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
682 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
683 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
686 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
687 uint64_t Addr, const void *Decoder) {
690 unsigned Register = QQQDecoderTable[RegNo];
691 Inst.addOperand(MCOperand::createReg(Register));
695 static const unsigned QQQQDecoderTable[] = {
696 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
697 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
698 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
699 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
700 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
701 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
702 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
703 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
704 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
705 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
706 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
709 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
711 const void *Decoder) {
714 unsigned Register = QQQQDecoderTable[RegNo];
715 Inst.addOperand(MCOperand::createReg(Register));
719 static const unsigned DDDecoderTable[] = {
720 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
721 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
722 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
723 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
724 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
725 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
726 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
727 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
730 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
731 uint64_t Addr, const void *Decoder) {
734 unsigned Register = DDDecoderTable[RegNo];
735 Inst.addOperand(MCOperand::createReg(Register));
739 static const unsigned DDDDecoderTable[] = {
740 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
741 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
742 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
743 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
744 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
745 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
746 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
747 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
748 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
749 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
750 AArch64::D30_D31_D0, AArch64::D31_D0_D1
753 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
754 uint64_t Addr, const void *Decoder) {
757 unsigned Register = DDDDecoderTable[RegNo];
758 Inst.addOperand(MCOperand::createReg(Register));
762 static const unsigned DDDDDecoderTable[] = {
763 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
764 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
765 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
766 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
767 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
768 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
769 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
770 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
771 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
772 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
773 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
776 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
778 const void *Decoder) {
781 unsigned Register = DDDDDecoderTable[RegNo];
782 Inst.addOperand(MCOperand::createReg(Register));
786 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
788 const void *Decoder) {
789 // scale{5} is asserted as 1 in tblgen.
791 Inst.addOperand(MCOperand::createImm(64 - Imm));
795 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
797 const void *Decoder) {
798 Inst.addOperand(MCOperand::createImm(64 - Imm));
802 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
803 uint64_t Addr, const void *Decoder) {
804 int64_t ImmVal = Imm;
805 const AArch64Disassembler *Dis =
806 static_cast<const AArch64Disassembler *>(Decoder);
808 // Sign-extend 19-bit immediate.
809 if (ImmVal & (1 << (19 - 1)))
810 ImmVal |= ~((1LL << 19) - 1);
812 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
813 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
814 Inst.addOperand(MCOperand::createImm(ImmVal));
818 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
819 uint64_t Address, const void *Decoder) {
820 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
821 Inst.addOperand(MCOperand::createImm(Imm & 1));
825 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
827 const void *Decoder) {
828 Inst.addOperand(MCOperand::createImm(Imm));
830 // Every system register in the encoding space is valid with the syntax
831 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
835 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
837 const void *Decoder) {
838 Inst.addOperand(MCOperand::createImm(Imm));
843 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
845 const void *Decoder) {
846 // This decoder exists to add the dummy Lane operand to the MCInst, which must
847 // be 1 in assembly but has no other real manifestation.
848 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
849 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
850 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
853 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
854 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
856 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
857 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
861 Inst.addOperand(MCOperand::createImm(1));
866 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
868 Inst.addOperand(MCOperand::createImm(Add - Imm));
872 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
874 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
878 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
879 uint64_t Addr, const void *Decoder) {
880 return DecodeVecShiftRImm(Inst, Imm, 64);
883 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
885 const void *Decoder) {
886 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
889 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
890 uint64_t Addr, const void *Decoder) {
891 return DecodeVecShiftRImm(Inst, Imm, 32);
894 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
896 const void *Decoder) {
897 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
900 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
901 uint64_t Addr, const void *Decoder) {
902 return DecodeVecShiftRImm(Inst, Imm, 16);
905 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
907 const void *Decoder) {
908 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
911 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
912 uint64_t Addr, const void *Decoder) {
913 return DecodeVecShiftRImm(Inst, Imm, 8);
916 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
917 uint64_t Addr, const void *Decoder) {
918 return DecodeVecShiftLImm(Inst, Imm, 64);
921 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
922 uint64_t Addr, const void *Decoder) {
923 return DecodeVecShiftLImm(Inst, Imm, 32);
926 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
927 uint64_t Addr, const void *Decoder) {
928 return DecodeVecShiftLImm(Inst, Imm, 16);
931 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
932 uint64_t Addr, const void *Decoder) {
933 return DecodeVecShiftLImm(Inst, Imm, 8);
936 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
938 const void *Decoder) {
939 unsigned Rd = fieldFromInstruction(insn, 0, 5);
940 unsigned Rn = fieldFromInstruction(insn, 5, 5);
941 unsigned Rm = fieldFromInstruction(insn, 16, 5);
942 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
943 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
944 unsigned shift = (shiftHi << 6) | shiftLo;
945 switch (Inst.getOpcode()) {
948 case AArch64::ADDWrs:
949 case AArch64::ADDSWrs:
950 case AArch64::SUBWrs:
951 case AArch64::SUBSWrs:
952 // if shift == '11' then ReservedValue()
956 case AArch64::ANDWrs:
957 case AArch64::ANDSWrs:
958 case AArch64::BICWrs:
959 case AArch64::BICSWrs:
960 case AArch64::ORRWrs:
961 case AArch64::ORNWrs:
962 case AArch64::EORWrs:
963 case AArch64::EONWrs: {
964 // if sf == '0' and imm6<5> == '1' then ReservedValue()
965 if (shiftLo >> 5 == 1)
967 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
968 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
969 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
972 case AArch64::ADDXrs:
973 case AArch64::ADDSXrs:
974 case AArch64::SUBXrs:
975 case AArch64::SUBSXrs:
976 // if shift == '11' then ReservedValue()
980 case AArch64::ANDXrs:
981 case AArch64::ANDSXrs:
982 case AArch64::BICXrs:
983 case AArch64::BICSXrs:
984 case AArch64::ORRXrs:
985 case AArch64::ORNXrs:
986 case AArch64::EORXrs:
987 case AArch64::EONXrs:
988 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
989 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
990 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
994 Inst.addOperand(MCOperand::createImm(shift));
998 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1000 const void *Decoder) {
1001 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1002 unsigned imm = fieldFromInstruction(insn, 5, 16);
1003 unsigned shift = fieldFromInstruction(insn, 21, 2);
1005 switch (Inst.getOpcode()) {
1008 case AArch64::MOVZWi:
1009 case AArch64::MOVNWi:
1010 case AArch64::MOVKWi:
1011 if (shift & (1U << 5))
1013 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1015 case AArch64::MOVZXi:
1016 case AArch64::MOVNXi:
1017 case AArch64::MOVKXi:
1018 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1022 if (Inst.getOpcode() == AArch64::MOVKWi ||
1023 Inst.getOpcode() == AArch64::MOVKXi)
1024 Inst.addOperand(Inst.getOperand(0));
1026 Inst.addOperand(MCOperand::createImm(imm));
1027 Inst.addOperand(MCOperand::createImm(shift));
1031 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1033 const void *Decoder) {
1034 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1035 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1036 unsigned offset = fieldFromInstruction(insn, 10, 12);
1037 const AArch64Disassembler *Dis =
1038 static_cast<const AArch64Disassembler *>(Decoder);
1040 switch (Inst.getOpcode()) {
1043 case AArch64::PRFMui:
1044 // Rt is an immediate in prefetch.
1045 Inst.addOperand(MCOperand::createImm(Rt));
1047 case AArch64::STRBBui:
1048 case AArch64::LDRBBui:
1049 case AArch64::LDRSBWui:
1050 case AArch64::STRHHui:
1051 case AArch64::LDRHHui:
1052 case AArch64::LDRSHWui:
1053 case AArch64::STRWui:
1054 case AArch64::LDRWui:
1055 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1057 case AArch64::LDRSBXui:
1058 case AArch64::LDRSHXui:
1059 case AArch64::LDRSWui:
1060 case AArch64::STRXui:
1061 case AArch64::LDRXui:
1062 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1064 case AArch64::LDRQui:
1065 case AArch64::STRQui:
1066 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1068 case AArch64::LDRDui:
1069 case AArch64::STRDui:
1070 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1072 case AArch64::LDRSui:
1073 case AArch64::STRSui:
1074 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1076 case AArch64::LDRHui:
1077 case AArch64::STRHui:
1078 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1080 case AArch64::LDRBui:
1081 case AArch64::STRBui:
1082 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1086 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1087 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1088 Inst.addOperand(MCOperand::createImm(offset));
1092 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1094 const void *Decoder) {
1095 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1096 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1097 int64_t offset = fieldFromInstruction(insn, 12, 9);
1099 // offset is a 9-bit signed immediate, so sign extend it to
1100 // fill the unsigned.
1101 if (offset & (1 << (9 - 1)))
1102 offset |= ~((1LL << 9) - 1);
1104 // First operand is always the writeback to the address register, if needed.
1105 switch (Inst.getOpcode()) {
1108 case AArch64::LDRSBWpre:
1109 case AArch64::LDRSHWpre:
1110 case AArch64::STRBBpre:
1111 case AArch64::LDRBBpre:
1112 case AArch64::STRHHpre:
1113 case AArch64::LDRHHpre:
1114 case AArch64::STRWpre:
1115 case AArch64::LDRWpre:
1116 case AArch64::LDRSBWpost:
1117 case AArch64::LDRSHWpost:
1118 case AArch64::STRBBpost:
1119 case AArch64::LDRBBpost:
1120 case AArch64::STRHHpost:
1121 case AArch64::LDRHHpost:
1122 case AArch64::STRWpost:
1123 case AArch64::LDRWpost:
1124 case AArch64::LDRSBXpre:
1125 case AArch64::LDRSHXpre:
1126 case AArch64::STRXpre:
1127 case AArch64::LDRSWpre:
1128 case AArch64::LDRXpre:
1129 case AArch64::LDRSBXpost:
1130 case AArch64::LDRSHXpost:
1131 case AArch64::STRXpost:
1132 case AArch64::LDRSWpost:
1133 case AArch64::LDRXpost:
1134 case AArch64::LDRQpre:
1135 case AArch64::STRQpre:
1136 case AArch64::LDRQpost:
1137 case AArch64::STRQpost:
1138 case AArch64::LDRDpre:
1139 case AArch64::STRDpre:
1140 case AArch64::LDRDpost:
1141 case AArch64::STRDpost:
1142 case AArch64::LDRSpre:
1143 case AArch64::STRSpre:
1144 case AArch64::LDRSpost:
1145 case AArch64::STRSpost:
1146 case AArch64::LDRHpre:
1147 case AArch64::STRHpre:
1148 case AArch64::LDRHpost:
1149 case AArch64::STRHpost:
1150 case AArch64::LDRBpre:
1151 case AArch64::STRBpre:
1152 case AArch64::LDRBpost:
1153 case AArch64::STRBpost:
1154 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1158 switch (Inst.getOpcode()) {
1161 case AArch64::PRFUMi:
1162 // Rt is an immediate in prefetch.
1163 Inst.addOperand(MCOperand::createImm(Rt));
1165 case AArch64::STURBBi:
1166 case AArch64::LDURBBi:
1167 case AArch64::LDURSBWi:
1168 case AArch64::STURHHi:
1169 case AArch64::LDURHHi:
1170 case AArch64::LDURSHWi:
1171 case AArch64::STURWi:
1172 case AArch64::LDURWi:
1173 case AArch64::LDTRSBWi:
1174 case AArch64::LDTRSHWi:
1175 case AArch64::STTRWi:
1176 case AArch64::LDTRWi:
1177 case AArch64::STTRHi:
1178 case AArch64::LDTRHi:
1179 case AArch64::LDTRBi:
1180 case AArch64::STTRBi:
1181 case AArch64::LDRSBWpre:
1182 case AArch64::LDRSHWpre:
1183 case AArch64::STRBBpre:
1184 case AArch64::LDRBBpre:
1185 case AArch64::STRHHpre:
1186 case AArch64::LDRHHpre:
1187 case AArch64::STRWpre:
1188 case AArch64::LDRWpre:
1189 case AArch64::LDRSBWpost:
1190 case AArch64::LDRSHWpost:
1191 case AArch64::STRBBpost:
1192 case AArch64::LDRBBpost:
1193 case AArch64::STRHHpost:
1194 case AArch64::LDRHHpost:
1195 case AArch64::STRWpost:
1196 case AArch64::LDRWpost:
1197 case AArch64::STLURBi:
1198 case AArch64::STLURHi:
1199 case AArch64::STLURWi:
1200 case AArch64::LDAPURBi:
1201 case AArch64::LDAPURSBWi:
1202 case AArch64::LDAPURHi:
1203 case AArch64::LDAPURSHWi:
1204 case AArch64::LDAPURi:
1205 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1207 case AArch64::LDURSBXi:
1208 case AArch64::LDURSHXi:
1209 case AArch64::LDURSWi:
1210 case AArch64::STURXi:
1211 case AArch64::LDURXi:
1212 case AArch64::LDTRSBXi:
1213 case AArch64::LDTRSHXi:
1214 case AArch64::LDTRSWi:
1215 case AArch64::STTRXi:
1216 case AArch64::LDTRXi:
1217 case AArch64::LDRSBXpre:
1218 case AArch64::LDRSHXpre:
1219 case AArch64::STRXpre:
1220 case AArch64::LDRSWpre:
1221 case AArch64::LDRXpre:
1222 case AArch64::LDRSBXpost:
1223 case AArch64::LDRSHXpost:
1224 case AArch64::STRXpost:
1225 case AArch64::LDRSWpost:
1226 case AArch64::LDRXpost:
1227 case AArch64::LDAPURSWi:
1228 case AArch64::LDAPURSHXi:
1229 case AArch64::LDAPURSBXi:
1230 case AArch64::STLURXi:
1231 case AArch64::LDAPURXi:
1232 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1234 case AArch64::LDURQi:
1235 case AArch64::STURQi:
1236 case AArch64::LDRQpre:
1237 case AArch64::STRQpre:
1238 case AArch64::LDRQpost:
1239 case AArch64::STRQpost:
1240 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1242 case AArch64::LDURDi:
1243 case AArch64::STURDi:
1244 case AArch64::LDRDpre:
1245 case AArch64::STRDpre:
1246 case AArch64::LDRDpost:
1247 case AArch64::STRDpost:
1248 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1250 case AArch64::LDURSi:
1251 case AArch64::STURSi:
1252 case AArch64::LDRSpre:
1253 case AArch64::STRSpre:
1254 case AArch64::LDRSpost:
1255 case AArch64::STRSpost:
1256 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1258 case AArch64::LDURHi:
1259 case AArch64::STURHi:
1260 case AArch64::LDRHpre:
1261 case AArch64::STRHpre:
1262 case AArch64::LDRHpost:
1263 case AArch64::STRHpost:
1264 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1266 case AArch64::LDURBi:
1267 case AArch64::STURBi:
1268 case AArch64::LDRBpre:
1269 case AArch64::STRBpre:
1270 case AArch64::LDRBpost:
1271 case AArch64::STRBpost:
1272 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1276 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1277 Inst.addOperand(MCOperand::createImm(offset));
1279 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1280 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1281 bool IsFP = fieldFromInstruction(insn, 26, 1);
1283 // Cannot write back to a transfer register (but xzr != sp).
1284 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1290 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1292 const void *Decoder) {
1293 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1294 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1295 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1296 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1298 unsigned Opcode = Inst.getOpcode();
1302 case AArch64::STLXRW:
1303 case AArch64::STLXRB:
1304 case AArch64::STLXRH:
1305 case AArch64::STXRW:
1306 case AArch64::STXRB:
1307 case AArch64::STXRH:
1308 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1310 case AArch64::LDARW:
1311 case AArch64::LDARB:
1312 case AArch64::LDARH:
1313 case AArch64::LDAXRW:
1314 case AArch64::LDAXRB:
1315 case AArch64::LDAXRH:
1316 case AArch64::LDXRW:
1317 case AArch64::LDXRB:
1318 case AArch64::LDXRH:
1319 case AArch64::STLRW:
1320 case AArch64::STLRB:
1321 case AArch64::STLRH:
1322 case AArch64::STLLRW:
1323 case AArch64::STLLRB:
1324 case AArch64::STLLRH:
1325 case AArch64::LDLARW:
1326 case AArch64::LDLARB:
1327 case AArch64::LDLARH:
1328 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1330 case AArch64::STLXRX:
1331 case AArch64::STXRX:
1332 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1334 case AArch64::LDARX:
1335 case AArch64::LDAXRX:
1336 case AArch64::LDXRX:
1337 case AArch64::STLRX:
1338 case AArch64::LDLARX:
1339 case AArch64::STLLRX:
1340 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1342 case AArch64::STLXPW:
1343 case AArch64::STXPW:
1344 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1346 case AArch64::LDAXPW:
1347 case AArch64::LDXPW:
1348 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1349 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1351 case AArch64::STLXPX:
1352 case AArch64::STXPX:
1353 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1355 case AArch64::LDAXPX:
1356 case AArch64::LDXPX:
1357 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1358 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1362 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1364 // You shouldn't load to the same register twice in an instruction...
1365 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1366 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1373 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1375 const void *Decoder) {
1376 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1377 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1378 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1379 int64_t offset = fieldFromInstruction(insn, 15, 7);
1380 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1382 // offset is a 7-bit signed immediate, so sign extend it to
1383 // fill the unsigned.
1384 if (offset & (1 << (7 - 1)))
1385 offset |= ~((1LL << 7) - 1);
1387 unsigned Opcode = Inst.getOpcode();
1388 bool NeedsDisjointWritebackTransfer = false;
1390 // First operand is always writeback of base register.
1394 case AArch64::LDPXpost:
1395 case AArch64::STPXpost:
1396 case AArch64::LDPSWpost:
1397 case AArch64::LDPXpre:
1398 case AArch64::STPXpre:
1399 case AArch64::LDPSWpre:
1400 case AArch64::LDPWpost:
1401 case AArch64::STPWpost:
1402 case AArch64::LDPWpre:
1403 case AArch64::STPWpre:
1404 case AArch64::LDPQpost:
1405 case AArch64::STPQpost:
1406 case AArch64::LDPQpre:
1407 case AArch64::STPQpre:
1408 case AArch64::LDPDpost:
1409 case AArch64::STPDpost:
1410 case AArch64::LDPDpre:
1411 case AArch64::STPDpre:
1412 case AArch64::LDPSpost:
1413 case AArch64::STPSpost:
1414 case AArch64::LDPSpre:
1415 case AArch64::STPSpre:
1416 case AArch64::STGPpre:
1417 case AArch64::STGPpost:
1418 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1425 case AArch64::LDPXpost:
1426 case AArch64::STPXpost:
1427 case AArch64::LDPSWpost:
1428 case AArch64::LDPXpre:
1429 case AArch64::STPXpre:
1430 case AArch64::LDPSWpre:
1431 case AArch64::STGPpre:
1432 case AArch64::STGPpost:
1433 NeedsDisjointWritebackTransfer = true;
1435 case AArch64::LDNPXi:
1436 case AArch64::STNPXi:
1437 case AArch64::LDPXi:
1438 case AArch64::STPXi:
1439 case AArch64::LDPSWi:
1440 case AArch64::STGPi:
1441 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1442 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1444 case AArch64::LDPWpost:
1445 case AArch64::STPWpost:
1446 case AArch64::LDPWpre:
1447 case AArch64::STPWpre:
1448 NeedsDisjointWritebackTransfer = true;
1450 case AArch64::LDNPWi:
1451 case AArch64::STNPWi:
1452 case AArch64::LDPWi:
1453 case AArch64::STPWi:
1454 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1455 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1457 case AArch64::LDNPQi:
1458 case AArch64::STNPQi:
1459 case AArch64::LDPQpost:
1460 case AArch64::STPQpost:
1461 case AArch64::LDPQi:
1462 case AArch64::STPQi:
1463 case AArch64::LDPQpre:
1464 case AArch64::STPQpre:
1465 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1466 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1468 case AArch64::LDNPDi:
1469 case AArch64::STNPDi:
1470 case AArch64::LDPDpost:
1471 case AArch64::STPDpost:
1472 case AArch64::LDPDi:
1473 case AArch64::STPDi:
1474 case AArch64::LDPDpre:
1475 case AArch64::STPDpre:
1476 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1477 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1479 case AArch64::LDNPSi:
1480 case AArch64::STNPSi:
1481 case AArch64::LDPSpost:
1482 case AArch64::STPSpost:
1483 case AArch64::LDPSi:
1484 case AArch64::STPSi:
1485 case AArch64::LDPSpre:
1486 case AArch64::STPSpre:
1487 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1488 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1492 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1493 Inst.addOperand(MCOperand::createImm(offset));
1495 // You shouldn't load to the same register twice in an instruction...
1496 if (IsLoad && Rt == Rt2)
1499 // ... or do any operation that writes-back to a transfer register. But note
1500 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1501 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1507 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1509 const void *Decoder) {
1510 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1511 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1512 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1513 fieldFromInstruction(insn, 12, 9);
1514 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1516 switch (Inst.getOpcode()) {
1519 case AArch64::LDRAAwriteback:
1520 case AArch64::LDRABwriteback:
1521 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1524 case AArch64::LDRAAindexed:
1525 case AArch64::LDRABindexed:
1529 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1530 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1531 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1533 if (writeback && Rt == Rn && Rn != 31) {
1540 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1542 const void *Decoder) {
1543 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1544 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1545 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1546 unsigned extend = fieldFromInstruction(insn, 10, 6);
1548 unsigned shift = extend & 0x7;
1552 switch (Inst.getOpcode()) {
1555 case AArch64::ADDWrx:
1556 case AArch64::SUBWrx:
1557 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1558 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1559 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1561 case AArch64::ADDSWrx:
1562 case AArch64::SUBSWrx:
1563 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1564 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1565 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1567 case AArch64::ADDXrx:
1568 case AArch64::SUBXrx:
1569 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1570 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1571 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1573 case AArch64::ADDSXrx:
1574 case AArch64::SUBSXrx:
1575 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1576 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1577 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1579 case AArch64::ADDXrx64:
1580 case AArch64::SUBXrx64:
1581 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1582 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1583 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1585 case AArch64::SUBSXrx64:
1586 case AArch64::ADDSXrx64:
1587 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1588 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1589 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1593 Inst.addOperand(MCOperand::createImm(extend));
1597 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1599 const void *Decoder) {
1600 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1601 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1602 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1606 if (Inst.getOpcode() == AArch64::ANDSXri)
1607 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1609 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1610 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1611 imm = fieldFromInstruction(insn, 10, 13);
1612 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1615 if (Inst.getOpcode() == AArch64::ANDSWri)
1616 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1618 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1619 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1620 imm = fieldFromInstruction(insn, 10, 12);
1621 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1624 Inst.addOperand(MCOperand::createImm(imm));
1628 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1630 const void *Decoder) {
1631 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1632 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1633 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1634 imm |= fieldFromInstruction(insn, 5, 5);
1636 if (Inst.getOpcode() == AArch64::MOVID)
1637 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1639 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1641 Inst.addOperand(MCOperand::createImm(imm));
1643 switch (Inst.getOpcode()) {
1646 case AArch64::MOVIv4i16:
1647 case AArch64::MOVIv8i16:
1648 case AArch64::MVNIv4i16:
1649 case AArch64::MVNIv8i16:
1650 case AArch64::MOVIv2i32:
1651 case AArch64::MOVIv4i32:
1652 case AArch64::MVNIv2i32:
1653 case AArch64::MVNIv4i32:
1654 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1656 case AArch64::MOVIv2s_msl:
1657 case AArch64::MOVIv4s_msl:
1658 case AArch64::MVNIv2s_msl:
1659 case AArch64::MVNIv4s_msl:
1660 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1667 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1669 const void *Decoder) {
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1671 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1672 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1673 imm |= fieldFromInstruction(insn, 5, 5);
1675 // Tied operands added twice.
1676 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1677 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1679 Inst.addOperand(MCOperand::createImm(imm));
1680 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1685 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1686 uint64_t Addr, const void *Decoder) {
1687 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1688 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1689 imm |= fieldFromInstruction(insn, 29, 2);
1690 const AArch64Disassembler *Dis =
1691 static_cast<const AArch64Disassembler *>(Decoder);
1693 // Sign-extend the 21-bit immediate.
1694 if (imm & (1 << (21 - 1)))
1695 imm |= ~((1LL << 21) - 1);
1697 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1698 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1699 Inst.addOperand(MCOperand::createImm(imm));
1704 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1705 uint64_t Addr, const void *Decoder) {
1706 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1707 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1708 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1709 unsigned S = fieldFromInstruction(insn, 29, 1);
1710 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1712 unsigned ShifterVal = (Imm >> 12) & 3;
1713 unsigned ImmVal = Imm & 0xFFF;
1714 const AArch64Disassembler *Dis =
1715 static_cast<const AArch64Disassembler *>(Decoder);
1717 if (ShifterVal != 0 && ShifterVal != 1)
1722 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1724 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1725 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1728 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1730 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1731 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1734 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1735 Inst.addOperand(MCOperand::createImm(ImmVal));
1736 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1740 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1742 const void *Decoder) {
1743 int64_t imm = fieldFromInstruction(insn, 0, 26);
1744 const AArch64Disassembler *Dis =
1745 static_cast<const AArch64Disassembler *>(Decoder);
1747 // Sign-extend the 26-bit immediate.
1748 if (imm & (1 << (26 - 1)))
1749 imm |= ~((1LL << 26) - 1);
1751 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1752 Inst.addOperand(MCOperand::createImm(imm));
1757 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1759 const void *Decoder) {
1760 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1761 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1762 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1763 uint64_t pstate_field = (op1 << 3) | op2;
1765 switch (pstate_field) {
1766 case 0x01: // XAFlag
1767 case 0x02: // AXFlag
1771 if ((pstate_field == AArch64PState::PAN ||
1772 pstate_field == AArch64PState::UAO ||
1773 pstate_field == AArch64PState::SSBS) && crm > 1)
1776 Inst.addOperand(MCOperand::createImm(pstate_field));
1777 Inst.addOperand(MCOperand::createImm(crm));
1779 const AArch64Disassembler *Dis =
1780 static_cast<const AArch64Disassembler *>(Decoder);
1781 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1782 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1787 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1788 uint64_t Addr, const void *Decoder) {
1789 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1790 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1791 bit |= fieldFromInstruction(insn, 19, 5);
1792 int64_t dst = fieldFromInstruction(insn, 5, 14);
1793 const AArch64Disassembler *Dis =
1794 static_cast<const AArch64Disassembler *>(Decoder);
1796 // Sign-extend 14-bit immediate.
1797 if (dst & (1 << (14 - 1)))
1798 dst |= ~((1LL << 14) - 1);
1800 if (fieldFromInstruction(insn, 31, 1) == 0)
1801 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1803 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1804 Inst.addOperand(MCOperand::createImm(bit));
1805 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1806 Inst.addOperand(MCOperand::createImm(dst));
1811 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1812 unsigned RegClassID,
1815 const void *Decoder) {
1816 // Register number must be even (see CASP instruction)
1820 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1821 Inst.addOperand(MCOperand::createReg(Reg));
1825 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1828 const void *Decoder) {
1829 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1830 AArch64::WSeqPairsClassRegClassID,
1831 RegNo, Addr, Decoder);
1834 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1837 const void *Decoder) {
1838 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1839 AArch64::XSeqPairsClassRegClassID,
1840 RegNo, Addr, Decoder);
1843 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1846 const void *Decoder) {
1847 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1848 unsigned imm = fieldFromInstruction(insn, 5, 13);
1849 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1852 // The same (tied) operand is added twice to the instruction.
1853 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1854 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1855 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1856 Inst.addOperand(MCOperand::createImm(imm));
1861 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1862 uint64_t Address, const void *Decoder) {
1863 if (Imm & ~((1LL << Bits) - 1))
1866 // Imm is a signed immediate, so sign extend it.
1867 if (Imm & (1 << (Bits - 1)))
1868 Imm |= ~((1LL << Bits) - 1);
1870 Inst.addOperand(MCOperand::createImm(Imm));
1874 // Decode 8-bit signed/unsigned immediate for a given element width.
1875 template <int ElementWidth>
1876 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1877 uint64_t Addr, const void *Decoder) {
1878 unsigned Val = (uint8_t)Imm;
1879 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1880 if (ElementWidth == 8 && Shift)
1882 Inst.addOperand(MCOperand::createImm(Val));
1883 Inst.addOperand(MCOperand::createImm(Shift));
1887 // Decode uimm4 ranged from 1-16.
1888 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1889 uint64_t Addr, const void *Decoder) {
1890 Inst.addOperand(MCOperand::createImm(Imm + 1));