contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "AArch64Disassembler.h"
  13 #include "AArch64ExternalSymbolizer.h"
  14 #include "MCTargetDesc/AArch64AddressingModes.h"
  15 #include "MCTargetDesc/AArch64MCTargetDesc.h"
  16 #include "TargetInfo/AArch64TargetInfo.h"
  17 #include "Utils/AArch64BaseInfo.h"
  18 #include "llvm-c/Disassembler.h"
  19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
  20 #include "llvm/MC/MCFixedLenDisassembler.h"
  21 #include "llvm/MC/MCInst.h"
  22 #include "llvm/MC/MCRegisterInfo.h"
  23 #include "llvm/MC/MCSubtargetInfo.h"
  24 #include "llvm/Support/Compiler.h"
  25 #include "llvm/Support/Debug.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28 #include <algorithm>
  29 #include <memory>
  30
  31 using namespace llvm;
  32
  33 #define DEBUG_TYPE "aarch64-disassembler"
  34
  35 // Pull DecodeStatus and its enum values into the global namespace.
  36 using DecodeStatus = MCDisassembler::DecodeStatus;
  37
  38 // Forward declare these because the autogenerated code will reference them.
  39 // Definitions are further down.
  40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
  41                                               unsigned RegNo, uint64_t Address,
  42                                               const void *Decoder);
  43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
  44                                                  unsigned RegNo,
  45                                                  uint64_t Address,
  46                                                  const void *Decoder);
  47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
  48                                              uint64_t Address,
  49                                              const void *Decoder);
  50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
  51                                              uint64_t Address,
  52                                              const void *Decoder);
  53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
  54                                              uint64_t Address,
  55                                              const void *Decoder);
  56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
  57                                             uint64_t Address,
  58                                             const void *Decoder);
  59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
  60                                              uint64_t Address,
  61                                              const void *Decoder);
  62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
  63                                              uint64_t Address,
  64                                              const void *Decoder);
  65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
  66                                                unsigned RegNo, uint64_t Address,
  67                                                const void *Decoder);
  68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
  72                                                unsigned RegNo, uint64_t Address,
  73                                                const void *Decoder);
  74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
  75                                           uint64_t Address,
  76                                           const void *Decoder);
  77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
  78                                            uint64_t Address,
  79                                            const void *Decoder);
  80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
  81                                             uint64_t Address,
  82                                             const void *Decoder);
  83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
  84                                           uint64_t Address,
  85                                           const void *Decoder);
  86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
  87                                            uint64_t Address,
  88                                            const void *Decoder);
  89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
  90                                             uint64_t Address,
  91                                             const void *Decoder);
  92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
  93                                            uint64_t Address,
  94                                            const void *Decoder);
  95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
  96                                               uint64_t Address,
  97                                               const void *Decoder);
  98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
  99                                               uint64_t Address,
 100                                               const void *Decoder);
 101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
 102                                             uint64_t Address,
 103                                             const void *Decoder);
 104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
 105                                             uint64_t Address,
 106                                             const void *Decoder);
 107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
 108                                             uint64_t Address,
 109                                             const void *Decoder);
 110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
 111                                            uint64_t Address,
 112                                            const void *Decoder);
 113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
 114                                               uint64_t Address,
 115                                               const void *Decoder);
 116
 117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
 118                                                uint64_t Address,
 119                                                const void *Decoder);
 120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
 121                                                uint64_t Address,
 122                                                const void *Decoder);
 123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
 124                                        uint64_t Address, const void *Decoder);
 125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
 126                                     uint64_t Address, const void *Decoder);
 127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
 128                                             uint64_t Address, const void *Decoder);
 129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
 130                                             uint64_t Address, const void *Decoder);
 131 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
 132                                                    uint64_t Address,
 133                                                    const void *Decoder);
 134 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
 135                                              uint64_t Address,
 136                                              const void *Decoder);
 137 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
 138                                                   uint64_t Address,
 139                                                   const void *Decoder);
 140 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
 141                                                 uint64_t Address,
 142                                                 const void *Decoder);
 143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
 144                                                    uint64_t Address,
 145                                                    const void *Decoder);
 146 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
 147                                               uint64_t Address,
 148                                               const void *Decoder);
 149 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
 150                                                 uint64_t Address,
 151                                                 const void *Decoder);
 152 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
 153                                                 uint64_t Address,
 154                                                 const void *Decoder);
 155 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
 156                                             uint64_t Address,
 157                                             const void *Decoder);
 158 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
 159                                                 uint64_t Address,
 160                                                 const void *Decoder);
 161 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
 162                                          uint64_t Address, const void *Decoder);
 163 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
 164                                          uint64_t Address, const void *Decoder);
 165 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
 166                                               uint64_t Address,
 167                                               const void *Decoder);
 168 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
 169                                                   uint64_t Address,
 170                                                   const void *Decoder);
 171 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
 172                                         uint64_t Address, const void *Decoder);
 173
 174 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
 175                                               uint64_t Address,
 176                                               const void *Decoder);
 177 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
 178                                          uint64_t Addr, const void *Decoder);
 179 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
 180                                                uint64_t Addr,
 181                                                const void *Decoder);
 182 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
 183                                          uint64_t Addr, const void *Decoder);
 184 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
 185                                                uint64_t Addr,
 186                                                const void *Decoder);
 187 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
 188                                          uint64_t Addr, const void *Decoder);
 189 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
 190                                                uint64_t Addr,
 191                                                const void *Decoder);
 192 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
 193                                         uint64_t Addr, const void *Decoder);
 194 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
 195                                          uint64_t Addr, const void *Decoder);
 196 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
 197                                          uint64_t Addr, const void *Decoder);
 198 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
 199                                          uint64_t Addr, const void *Decoder);
 200 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
 201                                         uint64_t Addr, const void *Decoder);
 202 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
 203                                                       unsigned RegNo,
 204                                                       uint64_t Addr,
 205                                                       const void *Decoder);
 206 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
 207                                                       unsigned RegNo,
 208                                                       uint64_t Addr,
 209                                                       const void *Decoder);
 210 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
 211                                                    uint32_t insn,
 212                                                    uint64_t Address,
 213                                                    const void *Decoder);
 214 template<int Bits>
 215 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
 216                                uint64_t Address, const void *Decoder);
 217 template <int ElementWidth>
 218 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
 219                                      uint64_t Addr, const void *Decoder);
 220 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
 221                                        uint64_t Addr, const void *Decoder);
 222
 223 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 224   switch (In) {
 225     case MCDisassembler::Success:
 226       // Out stays the same.
 227       return true;
 228     case MCDisassembler::SoftFail:
 229       Out = In;
 230       return true;
 231     case MCDisassembler::Fail:
 232       Out = In;
 233       return false;
 234   }
 235   llvm_unreachable("Invalid DecodeStatus!");
 236 }
 237
 238 #include "AArch64GenDisassemblerTables.inc"
 239 #include "AArch64GenInstrInfo.inc"
 240
 241 #define Success MCDisassembler::Success
 242 #define Fail MCDisassembler::Fail
 243 #define SoftFail MCDisassembler::SoftFail
 244
 245 static MCDisassembler *createAArch64Disassembler(const Target &T,
 246                                                const MCSubtargetInfo &STI,
 247                                                MCContext &Ctx) {
 248   return new AArch64Disassembler(STI, Ctx);
 249 }
 250
 251 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 252                                                  ArrayRef<uint8_t> Bytes,
 253                                                  uint64_t Address,
 254                                                  raw_ostream &CS) const {
 255   CommentStream = &CS;
 256
 257   Size = 0;
 258   // We want to read exactly 4 bytes of data.
 259   if (Bytes.size() < 4)
 260     return Fail;
 261   Size = 4;
 262
 263   // Encoded as a small-endian 32-bit word in the stream.
 264   uint32_t Insn =
 265       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
 266
 267   // Calling the auto-generated decoder function.
 268   return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
 269 }
 270
 271 static MCSymbolizer *
 272 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
 273                                 LLVMSymbolLookupCallback SymbolLookUp,
 274                                 void *DisInfo, MCContext *Ctx,
 275                                 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
 276   return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
 277                                        SymbolLookUp, DisInfo);
 278 }
 279
 280 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
 281   TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
 282                                          createAArch64Disassembler);
 283   TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
 284                                          createAArch64Disassembler);
 285   TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
 286                                        createAArch64ExternalSymbolizer);
 287   TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
 288                                        createAArch64ExternalSymbolizer);
 289   TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
 290                                          createAArch64Disassembler);
 291   TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
 292                                        createAArch64ExternalSymbolizer);
 293
 294   TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
 295                                          createAArch64Disassembler);
 296   TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
 297                                        createAArch64ExternalSymbolizer);
 298   TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
 299                                          createAArch64Disassembler);
 300   TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
 301                                        createAArch64ExternalSymbolizer);
 302 }
 303
 304 static const unsigned FPR128DecoderTable[] = {
 305     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
 306     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
 307     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
 308     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
 309     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
 310     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
 311     AArch64::Q30, AArch64::Q31
 312 };
 313
 314 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
 315                                               uint64_t Addr,
 316                                               const void *Decoder) {
 317   if (RegNo > 31)
 318     return Fail;
 319
 320   unsigned Register = FPR128DecoderTable[RegNo];
 321   Inst.addOperand(MCOperand::createReg(Register));
 322   return Success;
 323 }
 324
 325 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
 326                                                  uint64_t Addr,
 327                                                  const void *Decoder) {
 328   if (RegNo > 15)
 329     return Fail;
 330   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
 331 }
 332
 333 static const unsigned FPR64DecoderTable[] = {
 334     AArch64::D0,  AArch64::D1,  AArch64::D2,  AArch64::D3,  AArch64::D4,
 335     AArch64::D5,  AArch64::D6,  AArch64::D7,  AArch64::D8,  AArch64::D9,
 336     AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
 337     AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
 338     AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
 339     AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
 340     AArch64::D30, AArch64::D31
 341 };
 342
 343 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 344                                              uint64_t Addr,
 345                                              const void *Decoder) {
 346   if (RegNo > 31)
 347     return Fail;
 348
 349   unsigned Register = FPR64DecoderTable[RegNo];
 350   Inst.addOperand(MCOperand::createReg(Register));
 351   return Success;
 352 }
 353
 354 static const unsigned FPR32DecoderTable[] = {
 355     AArch64::S0,  AArch64::S1,  AArch64::S2,  AArch64::S3,  AArch64::S4,
 356     AArch64::S5,  AArch64::S6,  AArch64::S7,  AArch64::S8,  AArch64::S9,
 357     AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
 358     AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
 359     AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
 360     AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
 361     AArch64::S30, AArch64::S31
 362 };
 363
 364 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 365                                              uint64_t Addr,
 366                                              const void *Decoder) {
 367   if (RegNo > 31)
 368     return Fail;
 369
 370   unsigned Register = FPR32DecoderTable[RegNo];
 371   Inst.addOperand(MCOperand::createReg(Register));
 372   return Success;
 373 }
 374
 375 static const unsigned FPR16DecoderTable[] = {
 376     AArch64::H0,  AArch64::H1,  AArch64::H2,  AArch64::H3,  AArch64::H4,
 377     AArch64::H5,  AArch64::H6,  AArch64::H7,  AArch64::H8,  AArch64::H9,
 378     AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
 379     AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
 380     AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
 381     AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
 382     AArch64::H30, AArch64::H31
 383 };
 384
 385 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
 386                                              uint64_t Addr,
 387                                              const void *Decoder) {
 388   if (RegNo > 31)
 389     return Fail;
 390
 391   unsigned Register = FPR16DecoderTable[RegNo];
 392   Inst.addOperand(MCOperand::createReg(Register));
 393   return Success;
 394 }
 395
 396 static const unsigned FPR8DecoderTable[] = {
 397     AArch64::B0,  AArch64::B1,  AArch64::B2,  AArch64::B3,  AArch64::B4,
 398     AArch64::B5,  AArch64::B6,  AArch64::B7,  AArch64::B8,  AArch64::B9,
 399     AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
 400     AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
 401     AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
 402     AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
 403     AArch64::B30, AArch64::B31
 404 };
 405
 406 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
 407                                             uint64_t Addr,
 408                                             const void *Decoder) {
 409   if (RegNo > 31)
 410     return Fail;
 411
 412   unsigned Register = FPR8DecoderTable[RegNo];
 413   Inst.addOperand(MCOperand::createReg(Register));
 414   return Success;
 415 }
 416
 417 static const unsigned GPR64DecoderTable[] = {
 418     AArch64::X0,  AArch64::X1,  AArch64::X2,  AArch64::X3,  AArch64::X4,
 419     AArch64::X5,  AArch64::X6,  AArch64::X7,  AArch64::X8,  AArch64::X9,
 420     AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
 421     AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
 422     AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
 423     AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
 424     AArch64::LR,  AArch64::XZR
 425 };
 426
 427 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
 428                                                    uint64_t Addr,
 429                                                    const void *Decoder) {
 430   if (RegNo > 30)
 431     return Fail;
 432
 433   unsigned Register = GPR64DecoderTable[RegNo];
 434   Inst.addOperand(MCOperand::createReg(Register));
 435   return Success;
 436 }
 437
 438 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 439                                              uint64_t Addr,
 440                                              const void *Decoder) {
 441   if (RegNo > 31)
 442     return Fail;
 443
 444   unsigned Register = GPR64DecoderTable[RegNo];
 445   Inst.addOperand(MCOperand::createReg(Register));
 446   return Success;
 447 }
 448
 449 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
 450                                                uint64_t Addr,
 451                                                const void *Decoder) {
 452   if (RegNo > 31)
 453     return Fail;
 454   unsigned Register = GPR64DecoderTable[RegNo];
 455   if (Register == AArch64::XZR)
 456     Register = AArch64::SP;
 457   Inst.addOperand(MCOperand::createReg(Register));
 458   return Success;
 459 }
 460
 461 static const unsigned GPR32DecoderTable[] = {
 462     AArch64::W0,  AArch64::W1,  AArch64::W2,  AArch64::W3,  AArch64::W4,
 463     AArch64::W5,  AArch64::W6,  AArch64::W7,  AArch64::W8,  AArch64::W9,
 464     AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
 465     AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
 466     AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
 467     AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
 468     AArch64::W30, AArch64::WZR
 469 };
 470
 471 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 472                                              uint64_t Addr,
 473                                              const void *Decoder) {
 474   if (RegNo > 31)
 475     return Fail;
 476
 477   unsigned Register = GPR32DecoderTable[RegNo];
 478   Inst.addOperand(MCOperand::createReg(Register));
 479   return Success;
 480 }
 481
 482 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
 483                                                uint64_t Addr,
 484                                                const void *Decoder) {
 485   if (RegNo > 31)
 486     return Fail;
 487
 488   unsigned Register = GPR32DecoderTable[RegNo];
 489   if (Register == AArch64::WZR)
 490     Register = AArch64::WSP;
 491   Inst.addOperand(MCOperand::createReg(Register));
 492   return Success;
 493 }
 494 static const unsigned ZPRDecoderTable[] = {
 495     AArch64::Z0,  AArch64::Z1,  AArch64::Z2,  AArch64::Z3,
 496     AArch64::Z4,  AArch64::Z5,  AArch64::Z6,  AArch64::Z7,
 497     AArch64::Z8,  AArch64::Z9,  AArch64::Z10, AArch64::Z11,
 498     AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
 499     AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
 500     AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
 501     AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
 502     AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
 503 };
 504
 505 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
 506                                            uint64_t Address,
 507                                            const void* Decoder) {
 508   if (RegNo > 31)
 509     return Fail;
 510
 511   unsigned Register = ZPRDecoderTable[RegNo];
 512   Inst.addOperand(MCOperand::createReg(Register));
 513   return Success;
 514 }
 515
 516 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
 517                                               uint64_t Address,
 518                                               const void *Decoder) {
 519   if (RegNo > 15)
 520     return Fail;
 521   return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
 522 }
 523
 524 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
 525                                               uint64_t Address,
 526                                               const void *Decoder) {
 527   if (RegNo > 7)
 528     return Fail;
 529   return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
 530 }
 531
 532 static const unsigned ZZDecoderTable[] = {
 533   AArch64::Z0_Z1,   AArch64::Z1_Z2,   AArch64::Z2_Z3,   AArch64::Z3_Z4,
 534   AArch64::Z4_Z5,   AArch64::Z5_Z6,   AArch64::Z6_Z7,   AArch64::Z7_Z8,
 535   AArch64::Z8_Z9,   AArch64::Z9_Z10,  AArch64::Z10_Z11, AArch64::Z11_Z12,
 536   AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
 537   AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
 538   AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
 539   AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
 540   AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
 541 };
 542
 543 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
 544                                             uint64_t Address,
 545                                             const void* Decoder) {
 546   if (RegNo > 31)
 547     return Fail;
 548   unsigned Register = ZZDecoderTable[RegNo];
 549   Inst.addOperand(MCOperand::createReg(Register));
 550   return Success;
 551 }
 552
 553 static const unsigned ZZZDecoderTable[] = {
 554   AArch64::Z0_Z1_Z2,    AArch64::Z1_Z2_Z3,    AArch64::Z2_Z3_Z4,
 555   AArch64::Z3_Z4_Z5,    AArch64::Z4_Z5_Z6,    AArch64::Z5_Z6_Z7,
 556   AArch64::Z6_Z7_Z8,    AArch64::Z7_Z8_Z9,    AArch64::Z8_Z9_Z10,
 557   AArch64::Z9_Z10_Z11,  AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
 558   AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
 559   AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
 560   AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
 561   AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
 562   AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
 563   AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
 564   AArch64::Z30_Z31_Z0,  AArch64::Z31_Z0_Z1
 565 };
 566
 567 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
 568                                             uint64_t Address,
 569                                             const void* Decoder) {
 570   if (RegNo > 31)
 571     return Fail;
 572   unsigned Register = ZZZDecoderTable[RegNo];
 573   Inst.addOperand(MCOperand::createReg(Register));
 574   return Success;
 575 }
 576
 577 static const unsigned ZZZZDecoderTable[] = {
 578   AArch64::Z0_Z1_Z2_Z3,     AArch64::Z1_Z2_Z3_Z4,     AArch64::Z2_Z3_Z4_Z5,
 579   AArch64::Z3_Z4_Z5_Z6,     AArch64::Z4_Z5_Z6_Z7,     AArch64::Z5_Z6_Z7_Z8,
 580   AArch64::Z6_Z7_Z8_Z9,     AArch64::Z7_Z8_Z9_Z10,    AArch64::Z8_Z9_Z10_Z11,
 581   AArch64::Z9_Z10_Z11_Z12,  AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
 582   AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
 583   AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
 584   AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
 585   AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
 586   AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
 587   AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
 588   AArch64::Z30_Z31_Z0_Z1,   AArch64::Z31_Z0_Z1_Z2
 589 };
 590
 591 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
 592                                             uint64_t Address,
 593                                             const void* Decoder) {
 594   if (RegNo > 31)
 595     return Fail;
 596   unsigned Register = ZZZZDecoderTable[RegNo];
 597   Inst.addOperand(MCOperand::createReg(Register));
 598   return Success;
 599 }
 600
 601 static const unsigned PPRDecoderTable[] = {
 602   AArch64::P0,  AArch64::P1,  AArch64::P2,  AArch64::P3,
 603   AArch64::P4,  AArch64::P5,  AArch64::P6,  AArch64::P7,
 604   AArch64::P8,  AArch64::P9,  AArch64::P10, AArch64::P11,
 605   AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
 606 };
 607
 608 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
 609                                            uint64_t Addr, const void *Decoder) {
 610   if (RegNo > 15)
 611     return Fail;
 612
 613   unsigned Register = PPRDecoderTable[RegNo];
 614   Inst.addOperand(MCOperand::createReg(Register));
 615   return Success;
 616 }
 617
 618 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
 619                                               uint64_t Addr,
 620                                               const void* Decoder) {
 621   if (RegNo > 7)
 622     return Fail;
 623
 624   // Just reuse the PPR decode table
 625   return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
 626 }
 627
 628 static const unsigned VectorDecoderTable[] = {
 629     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
 630     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
 631     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
 632     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
 633     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
 634     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
 635     AArch64::Q30, AArch64::Q31
 636 };
 637
 638 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
 639                                               uint64_t Addr,
 640                                               const void *Decoder) {
 641   if (RegNo > 31)
 642     return Fail;
 643
 644   unsigned Register = VectorDecoderTable[RegNo];
 645   Inst.addOperand(MCOperand::createReg(Register));
 646   return Success;
 647 }
 648
 649 static const unsigned QQDecoderTable[] = {
 650   AArch64::Q0_Q1,   AArch64::Q1_Q2,   AArch64::Q2_Q3,   AArch64::Q3_Q4,
 651   AArch64::Q4_Q5,   AArch64::Q5_Q6,   AArch64::Q6_Q7,   AArch64::Q7_Q8,
 652   AArch64::Q8_Q9,   AArch64::Q9_Q10,  AArch64::Q10_Q11, AArch64::Q11_Q12,
 653   AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
 654   AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
 655   AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
 656   AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
 657   AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
 658 };
 659
 660 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
 661                                           uint64_t Addr, const void *Decoder) {
 662   if (RegNo > 31)
 663     return Fail;
 664   unsigned Register = QQDecoderTable[RegNo];
 665   Inst.addOperand(MCOperand::createReg(Register));
 666   return Success;
 667 }
 668
 669 static const unsigned QQQDecoderTable[] = {
 670   AArch64::Q0_Q1_Q2,    AArch64::Q1_Q2_Q3,    AArch64::Q2_Q3_Q4,
 671   AArch64::Q3_Q4_Q5,    AArch64::Q4_Q5_Q6,    AArch64::Q5_Q6_Q7,
 672   AArch64::Q6_Q7_Q8,    AArch64::Q7_Q8_Q9,    AArch64::Q8_Q9_Q10,
 673   AArch64::Q9_Q10_Q11,  AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
 674   AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
 675   AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
 676   AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
 677   AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
 678   AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
 679   AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
 680   AArch64::Q30_Q31_Q0,  AArch64::Q31_Q0_Q1
 681 };
 682
 683 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 684                                            uint64_t Addr, const void *Decoder) {
 685   if (RegNo > 31)
 686     return Fail;
 687   unsigned Register = QQQDecoderTable[RegNo];
 688   Inst.addOperand(MCOperand::createReg(Register));
 689   return Success;
 690 }
 691
 692 static const unsigned QQQQDecoderTable[] = {
 693   AArch64::Q0_Q1_Q2_Q3,     AArch64::Q1_Q2_Q3_Q4,     AArch64::Q2_Q3_Q4_Q5,
 694   AArch64::Q3_Q4_Q5_Q6,     AArch64::Q4_Q5_Q6_Q7,     AArch64::Q5_Q6_Q7_Q8,
 695   AArch64::Q6_Q7_Q8_Q9,     AArch64::Q7_Q8_Q9_Q10,    AArch64::Q8_Q9_Q10_Q11,
 696   AArch64::Q9_Q10_Q11_Q12,  AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
 697   AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
 698   AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
 699   AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
 700   AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
 701   AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
 702   AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
 703   AArch64::Q30_Q31_Q0_Q1,   AArch64::Q31_Q0_Q1_Q2
 704 };
 705
 706 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 707                                             uint64_t Addr,
 708                                             const void *Decoder) {
 709   if (RegNo > 31)
 710     return Fail;
 711   unsigned Register = QQQQDecoderTable[RegNo];
 712   Inst.addOperand(MCOperand::createReg(Register));
 713   return Success;
 714 }
 715
 716 static const unsigned DDDecoderTable[] = {
 717   AArch64::D0_D1,   AArch64::D1_D2,   AArch64::D2_D3,   AArch64::D3_D4,
 718   AArch64::D4_D5,   AArch64::D5_D6,   AArch64::D6_D7,   AArch64::D7_D8,
 719   AArch64::D8_D9,   AArch64::D9_D10,  AArch64::D10_D11, AArch64::D11_D12,
 720   AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
 721   AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
 722   AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
 723   AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
 724   AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
 725 };
 726
 727 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
 728                                           uint64_t Addr, const void *Decoder) {
 729   if (RegNo > 31)
 730     return Fail;
 731   unsigned Register = DDDecoderTable[RegNo];
 732   Inst.addOperand(MCOperand::createReg(Register));
 733   return Success;
 734 }
 735
 736 static const unsigned DDDDecoderTable[] = {
 737   AArch64::D0_D1_D2,    AArch64::D1_D2_D3,    AArch64::D2_D3_D4,
 738   AArch64::D3_D4_D5,    AArch64::D4_D5_D6,    AArch64::D5_D6_D7,
 739   AArch64::D6_D7_D8,    AArch64::D7_D8_D9,    AArch64::D8_D9_D10,
 740   AArch64::D9_D10_D11,  AArch64::D10_D11_D12, AArch64::D11_D12_D13,
 741   AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
 742   AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
 743   AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
 744   AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
 745   AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
 746   AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
 747   AArch64::D30_D31_D0,  AArch64::D31_D0_D1
 748 };
 749
 750 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 751                                            uint64_t Addr, const void *Decoder) {
 752   if (RegNo > 31)
 753     return Fail;
 754   unsigned Register = DDDDecoderTable[RegNo];
 755   Inst.addOperand(MCOperand::createReg(Register));
 756   return Success;
 757 }
 758
 759 static const unsigned DDDDDecoderTable[] = {
 760   AArch64::D0_D1_D2_D3,     AArch64::D1_D2_D3_D4,     AArch64::D2_D3_D4_D5,
 761   AArch64::D3_D4_D5_D6,     AArch64::D4_D5_D6_D7,     AArch64::D5_D6_D7_D8,
 762   AArch64::D6_D7_D8_D9,     AArch64::D7_D8_D9_D10,    AArch64::D8_D9_D10_D11,
 763   AArch64::D9_D10_D11_D12,  AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
 764   AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
 765   AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
 766   AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
 767   AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
 768   AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
 769   AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
 770   AArch64::D30_D31_D0_D1,   AArch64::D31_D0_D1_D2
 771 };
 772
 773 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 774                                             uint64_t Addr,
 775                                             const void *Decoder) {
 776   if (RegNo > 31)
 777     return Fail;
 778   unsigned Register = DDDDDecoderTable[RegNo];
 779   Inst.addOperand(MCOperand::createReg(Register));
 780   return Success;
 781 }
 782
 783 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
 784                                                uint64_t Addr,
 785                                                const void *Decoder) {
 786   // scale{5} is asserted as 1 in tblgen.
 787   Imm |= 0x20;
 788   Inst.addOperand(MCOperand::createImm(64 - Imm));
 789   return Success;
 790 }
 791
 792 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
 793                                                uint64_t Addr,
 794                                                const void *Decoder) {
 795   Inst.addOperand(MCOperand::createImm(64 - Imm));
 796   return Success;
 797 }
 798
 799 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
 800                                        uint64_t Addr, const void *Decoder) {
 801   int64_t ImmVal = Imm;
 802   const AArch64Disassembler *Dis =
 803       static_cast<const AArch64Disassembler *>(Decoder);
 804
 805   // Sign-extend 19-bit immediate.
 806   if (ImmVal & (1 << (19 - 1)))
 807     ImmVal |= ~((1LL << 19) - 1);
 808
 809   if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal *  4, Addr,
 810                                      Inst.getOpcode() != AArch64::LDRXl, 0, 4))
 811     Inst.addOperand(MCOperand::createImm(ImmVal));
 812   return Success;
 813 }
 814
 815 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
 816                                     uint64_t Address, const void *Decoder) {
 817   Inst.addOperand(MCOperand::createImm((Imm  >> 1) & 1));
 818   Inst.addOperand(MCOperand::createImm(Imm & 1));
 819   return Success;
 820 }
 821
 822 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
 823                                             uint64_t Address,
 824                                             const void *Decoder) {
 825   Inst.addOperand(MCOperand::createImm(Imm));
 826
 827   // Every system register in the encoding space is valid with the syntax
 828   // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
 829   return Success;
 830 }
 831
 832 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
 833                                             uint64_t Address,
 834                                             const void *Decoder) {
 835   Inst.addOperand(MCOperand::createImm(Imm));
 836
 837   return Success;
 838 }
 839
 840 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
 841                                               uint64_t Address,
 842                                               const void *Decoder) {
 843   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 844   // be 1 in assembly but has no other real manifestation.
 845   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 846   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 847   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 848
 849   if (IsToVec) {
 850     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 851     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 852   } else {
 853     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 854     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 855   }
 856
 857   // Add the lane
 858   Inst.addOperand(MCOperand::createImm(1));
 859
 860   return Success;
 861 }
 862
 863 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
 864                                        unsigned Add) {
 865   Inst.addOperand(MCOperand::createImm(Add - Imm));
 866   return Success;
 867 }
 868
 869 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
 870                                        unsigned Add) {
 871   Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
 872   return Success;
 873 }
 874
 875 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
 876                                          uint64_t Addr, const void *Decoder) {
 877   return DecodeVecShiftRImm(Inst, Imm, 64);
 878 }
 879
 880 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
 881                                                uint64_t Addr,
 882                                                const void *Decoder) {
 883   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
 884 }
 885
 886 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
 887                                          uint64_t Addr, const void *Decoder) {
 888   return DecodeVecShiftRImm(Inst, Imm, 32);
 889 }
 890
 891 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
 892                                                uint64_t Addr,
 893                                                const void *Decoder) {
 894   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
 895 }
 896
 897 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
 898                                          uint64_t Addr, const void *Decoder) {
 899   return DecodeVecShiftRImm(Inst, Imm, 16);
 900 }
 901
 902 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
 903                                                uint64_t Addr,
 904                                                const void *Decoder) {
 905   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
 906 }
 907
 908 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
 909                                         uint64_t Addr, const void *Decoder) {
 910   return DecodeVecShiftRImm(Inst, Imm, 8);
 911 }
 912
 913 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
 914                                          uint64_t Addr, const void *Decoder) {
 915   return DecodeVecShiftLImm(Inst, Imm, 64);
 916 }
 917
 918 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
 919                                          uint64_t Addr, const void *Decoder) {
 920   return DecodeVecShiftLImm(Inst, Imm, 32);
 921 }
 922
 923 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
 924                                          uint64_t Addr, const void *Decoder) {
 925   return DecodeVecShiftLImm(Inst, Imm, 16);
 926 }
 927
 928 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
 929                                         uint64_t Addr, const void *Decoder) {
 930   return DecodeVecShiftLImm(Inst, Imm, 8);
 931 }
 932
 933 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
 934                                                    uint64_t Addr,
 935                                                    const void *Decoder) {
 936   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 937   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 938   unsigned Rm = fieldFromInstruction(insn, 16, 5);
 939   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
 940   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
 941   unsigned shift = (shiftHi << 6) | shiftLo;
 942   switch (Inst.getOpcode()) {
 943   default:
 944     return Fail;
 945   case AArch64::ADDWrs:
 946   case AArch64::ADDSWrs:
 947   case AArch64::SUBWrs:
 948   case AArch64::SUBSWrs:
 949     // if shift == '11' then ReservedValue()
 950     if (shiftHi == 0x3)
 951       return Fail;
 952     LLVM_FALLTHROUGH;
 953   case AArch64::ANDWrs:
 954   case AArch64::ANDSWrs:
 955   case AArch64::BICWrs:
 956   case AArch64::BICSWrs:
 957   case AArch64::ORRWrs:
 958   case AArch64::ORNWrs:
 959   case AArch64::EORWrs:
 960   case AArch64::EONWrs: {
 961     // if sf == '0' and imm6<5> == '1' then ReservedValue()
 962     if (shiftLo >> 5 == 1)
 963       return Fail;
 964     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 965     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
 966     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 967     break;
 968   }
 969   case AArch64::ADDXrs:
 970   case AArch64::ADDSXrs:
 971   case AArch64::SUBXrs:
 972   case AArch64::SUBSXrs:
 973     // if shift == '11' then ReservedValue()
 974     if (shiftHi == 0x3)
 975       return Fail;
 976     LLVM_FALLTHROUGH;
 977   case AArch64::ANDXrs:
 978   case AArch64::ANDSXrs:
 979   case AArch64::BICXrs:
 980   case AArch64::BICSXrs:
 981   case AArch64::ORRXrs:
 982   case AArch64::ORNXrs:
 983   case AArch64::EORXrs:
 984   case AArch64::EONXrs:
 985     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 986     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
 987     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
 988     break;
 989   }
 990
 991   Inst.addOperand(MCOperand::createImm(shift));
 992   return Success;
 993 }
 994
 995 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
 996                                              uint64_t Addr,
 997                                              const void *Decoder) {
 998   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 999   unsigned imm = fieldFromInstruction(insn, 5, 16);
1000   unsigned shift = fieldFromInstruction(insn, 21, 2);
1001   shift <<= 4;
1002   switch (Inst.getOpcode()) {
1003   default:
1004     return Fail;
1005   case AArch64::MOVZWi:
1006   case AArch64::MOVNWi:
1007   case AArch64::MOVKWi:
1008     if (shift & (1U << 5))
1009       return Fail;
1010     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1011     break;
1012   case AArch64::MOVZXi:
1013   case AArch64::MOVNXi:
1014   case AArch64::MOVKXi:
1015     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1016     break;
1017   }
1018
1019   if (Inst.getOpcode() == AArch64::MOVKWi ||
1020       Inst.getOpcode() == AArch64::MOVKXi)
1021     Inst.addOperand(Inst.getOperand(0));
1022
1023   Inst.addOperand(MCOperand::createImm(imm));
1024   Inst.addOperand(MCOperand::createImm(shift));
1025   return Success;
1026 }
1027
1028 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1029                                                   uint64_t Addr,
1030                                                   const void *Decoder) {
1031   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1032   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1033   unsigned offset = fieldFromInstruction(insn, 10, 12);
1034   const AArch64Disassembler *Dis =
1035       static_cast<const AArch64Disassembler *>(Decoder);
1036
1037   switch (Inst.getOpcode()) {
1038   default:
1039     return Fail;
1040   case AArch64::PRFMui:
1041     // Rt is an immediate in prefetch.
1042     Inst.addOperand(MCOperand::createImm(Rt));
1043     break;
1044   case AArch64::STRBBui:
1045   case AArch64::LDRBBui:
1046   case AArch64::LDRSBWui:
1047   case AArch64::STRHHui:
1048   case AArch64::LDRHHui:
1049   case AArch64::LDRSHWui:
1050   case AArch64::STRWui:
1051   case AArch64::LDRWui:
1052     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1053     break;
1054   case AArch64::LDRSBXui:
1055   case AArch64::LDRSHXui:
1056   case AArch64::LDRSWui:
1057   case AArch64::STRXui:
1058   case AArch64::LDRXui:
1059     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1060     break;
1061   case AArch64::LDRQui:
1062   case AArch64::STRQui:
1063     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1064     break;
1065   case AArch64::LDRDui:
1066   case AArch64::STRDui:
1067     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1068     break;
1069   case AArch64::LDRSui:
1070   case AArch64::STRSui:
1071     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1072     break;
1073   case AArch64::LDRHui:
1074   case AArch64::STRHui:
1075     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1076     break;
1077   case AArch64::LDRBui:
1078   case AArch64::STRBui:
1079     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1080     break;
1081   }
1082
1083   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1084   if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1085     Inst.addOperand(MCOperand::createImm(offset));
1086   return Success;
1087 }
1088
1089 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1090                                                 uint64_t Addr,
1091                                                 const void *Decoder) {
1092   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1093   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1094   int64_t offset = fieldFromInstruction(insn, 12, 9);
1095
1096   // offset is a 9-bit signed immediate, so sign extend it to
1097   // fill the unsigned.
1098   if (offset & (1 << (9 - 1)))
1099     offset |= ~((1LL << 9) - 1);
1100
1101   // First operand is always the writeback to the address register, if needed.
1102   switch (Inst.getOpcode()) {
1103   default:
1104     break;
1105   case AArch64::LDRSBWpre:
1106   case AArch64::LDRSHWpre:
1107   case AArch64::STRBBpre:
1108   case AArch64::LDRBBpre:
1109   case AArch64::STRHHpre:
1110   case AArch64::LDRHHpre:
1111   case AArch64::STRWpre:
1112   case AArch64::LDRWpre:
1113   case AArch64::LDRSBWpost:
1114   case AArch64::LDRSHWpost:
1115   case AArch64::STRBBpost:
1116   case AArch64::LDRBBpost:
1117   case AArch64::STRHHpost:
1118   case AArch64::LDRHHpost:
1119   case AArch64::STRWpost:
1120   case AArch64::LDRWpost:
1121   case AArch64::LDRSBXpre:
1122   case AArch64::LDRSHXpre:
1123   case AArch64::STRXpre:
1124   case AArch64::LDRSWpre:
1125   case AArch64::LDRXpre:
1126   case AArch64::LDRSBXpost:
1127   case AArch64::LDRSHXpost:
1128   case AArch64::STRXpost:
1129   case AArch64::LDRSWpost:
1130   case AArch64::LDRXpost:
1131   case AArch64::LDRQpre:
1132   case AArch64::STRQpre:
1133   case AArch64::LDRQpost:
1134   case AArch64::STRQpost:
1135   case AArch64::LDRDpre:
1136   case AArch64::STRDpre:
1137   case AArch64::LDRDpost:
1138   case AArch64::STRDpost:
1139   case AArch64::LDRSpre:
1140   case AArch64::STRSpre:
1141   case AArch64::LDRSpost:
1142   case AArch64::STRSpost:
1143   case AArch64::LDRHpre:
1144   case AArch64::STRHpre:
1145   case AArch64::LDRHpost:
1146   case AArch64::STRHpost:
1147   case AArch64::LDRBpre:
1148   case AArch64::STRBpre:
1149   case AArch64::LDRBpost:
1150   case AArch64::STRBpost:
1151     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1152     break;
1153   }
1154
1155   switch (Inst.getOpcode()) {
1156   default:
1157     return Fail;
1158   case AArch64::PRFUMi:
1159     // Rt is an immediate in prefetch.
1160     Inst.addOperand(MCOperand::createImm(Rt));
1161     break;
1162   case AArch64::STURBBi:
1163   case AArch64::LDURBBi:
1164   case AArch64::LDURSBWi:
1165   case AArch64::STURHHi:
1166   case AArch64::LDURHHi:
1167   case AArch64::LDURSHWi:
1168   case AArch64::STURWi:
1169   case AArch64::LDURWi:
1170   case AArch64::LDTRSBWi:
1171   case AArch64::LDTRSHWi:
1172   case AArch64::STTRWi:
1173   case AArch64::LDTRWi:
1174   case AArch64::STTRHi:
1175   case AArch64::LDTRHi:
1176   case AArch64::LDTRBi:
1177   case AArch64::STTRBi:
1178   case AArch64::LDRSBWpre:
1179   case AArch64::LDRSHWpre:
1180   case AArch64::STRBBpre:
1181   case AArch64::LDRBBpre:
1182   case AArch64::STRHHpre:
1183   case AArch64::LDRHHpre:
1184   case AArch64::STRWpre:
1185   case AArch64::LDRWpre:
1186   case AArch64::LDRSBWpost:
1187   case AArch64::LDRSHWpost:
1188   case AArch64::STRBBpost:
1189   case AArch64::LDRBBpost:
1190   case AArch64::STRHHpost:
1191   case AArch64::LDRHHpost:
1192   case AArch64::STRWpost:
1193   case AArch64::LDRWpost:
1194   case AArch64::STLURBi:
1195   case AArch64::STLURHi:
1196   case AArch64::STLURWi:
1197   case AArch64::LDAPURBi:
1198   case AArch64::LDAPURSBWi:
1199   case AArch64::LDAPURHi:
1200   case AArch64::LDAPURSHWi:
1201   case AArch64::LDAPURi:
1202     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1203     break;
1204   case AArch64::LDURSBXi:
1205   case AArch64::LDURSHXi:
1206   case AArch64::LDURSWi:
1207   case AArch64::STURXi:
1208   case AArch64::LDURXi:
1209   case AArch64::LDTRSBXi:
1210   case AArch64::LDTRSHXi:
1211   case AArch64::LDTRSWi:
1212   case AArch64::STTRXi:
1213   case AArch64::LDTRXi:
1214   case AArch64::LDRSBXpre:
1215   case AArch64::LDRSHXpre:
1216   case AArch64::STRXpre:
1217   case AArch64::LDRSWpre:
1218   case AArch64::LDRXpre:
1219   case AArch64::LDRSBXpost:
1220   case AArch64::LDRSHXpost:
1221   case AArch64::STRXpost:
1222   case AArch64::LDRSWpost:
1223   case AArch64::LDRXpost:
1224   case AArch64::LDAPURSWi:
1225   case AArch64::LDAPURSHXi:
1226   case AArch64::LDAPURSBXi:
1227   case AArch64::STLURXi:
1228   case AArch64::LDAPURXi:
1229     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1230     break;
1231   case AArch64::LDURQi:
1232   case AArch64::STURQi:
1233   case AArch64::LDRQpre:
1234   case AArch64::STRQpre:
1235   case AArch64::LDRQpost:
1236   case AArch64::STRQpost:
1237     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1238     break;
1239   case AArch64::LDURDi:
1240   case AArch64::STURDi:
1241   case AArch64::LDRDpre:
1242   case AArch64::STRDpre:
1243   case AArch64::LDRDpost:
1244   case AArch64::STRDpost:
1245     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1246     break;
1247   case AArch64::LDURSi:
1248   case AArch64::STURSi:
1249   case AArch64::LDRSpre:
1250   case AArch64::STRSpre:
1251   case AArch64::LDRSpost:
1252   case AArch64::STRSpost:
1253     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1254     break;
1255   case AArch64::LDURHi:
1256   case AArch64::STURHi:
1257   case AArch64::LDRHpre:
1258   case AArch64::STRHpre:
1259   case AArch64::LDRHpost:
1260   case AArch64::STRHpost:
1261     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1262     break;
1263   case AArch64::LDURBi:
1264   case AArch64::STURBi:
1265   case AArch64::LDRBpre:
1266   case AArch64::STRBpre:
1267   case AArch64::LDRBpost:
1268   case AArch64::STRBpost:
1269     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1270     break;
1271   }
1272
1273   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1274   Inst.addOperand(MCOperand::createImm(offset));
1275
1276   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1277   bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1278   bool IsFP = fieldFromInstruction(insn, 26, 1);
1279
1280   // Cannot write back to a transfer register (but xzr != sp).
1281   if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1282     return SoftFail;
1283
1284   return Success;
1285 }
1286
1287 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1288                                                    uint64_t Addr,
1289                                                    const void *Decoder) {
1290   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1291   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1292   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1293   unsigned Rs = fieldFromInstruction(insn, 16, 5);
1294
1295   unsigned Opcode = Inst.getOpcode();
1296   switch (Opcode) {
1297   default:
1298     return Fail;
1299   case AArch64::STLXRW:
1300   case AArch64::STLXRB:
1301   case AArch64::STLXRH:
1302   case AArch64::STXRW:
1303   case AArch64::STXRB:
1304   case AArch64::STXRH:
1305     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1306     LLVM_FALLTHROUGH;
1307   case AArch64::LDARW:
1308   case AArch64::LDARB:
1309   case AArch64::LDARH:
1310   case AArch64::LDAXRW:
1311   case AArch64::LDAXRB:
1312   case AArch64::LDAXRH:
1313   case AArch64::LDXRW:
1314   case AArch64::LDXRB:
1315   case AArch64::LDXRH:
1316   case AArch64::STLRW:
1317   case AArch64::STLRB:
1318   case AArch64::STLRH:
1319   case AArch64::STLLRW:
1320   case AArch64::STLLRB:
1321   case AArch64::STLLRH:
1322   case AArch64::LDLARW:
1323   case AArch64::LDLARB:
1324   case AArch64::LDLARH:
1325     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1326     break;
1327   case AArch64::STLXRX:
1328   case AArch64::STXRX:
1329     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1330     LLVM_FALLTHROUGH;
1331   case AArch64::LDARX:
1332   case AArch64::LDAXRX:
1333   case AArch64::LDXRX:
1334   case AArch64::STLRX:
1335   case AArch64::LDLARX:
1336   case AArch64::STLLRX:
1337     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1338     break;
1339   case AArch64::STLXPW:
1340   case AArch64::STXPW:
1341     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1342     LLVM_FALLTHROUGH;
1343   case AArch64::LDAXPW:
1344   case AArch64::LDXPW:
1345     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1346     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1347     break;
1348   case AArch64::STLXPX:
1349   case AArch64::STXPX:
1350     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1351     LLVM_FALLTHROUGH;
1352   case AArch64::LDAXPX:
1353   case AArch64::LDXPX:
1354     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1355     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1356     break;
1357   }
1358
1359   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1360
1361   // You shouldn't load to the same register twice in an instruction...
1362   if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1363        Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1364       Rt == Rt2)
1365     return SoftFail;
1366
1367   return Success;
1368 }
1369
1370 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1371                                               uint64_t Addr,
1372                                               const void *Decoder) {
1373   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1374   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1375   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1376   int64_t offset = fieldFromInstruction(insn, 15, 7);
1377   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1378
1379   // offset is a 7-bit signed immediate, so sign extend it to
1380   // fill the unsigned.
1381   if (offset & (1 << (7 - 1)))
1382     offset |= ~((1LL << 7) - 1);
1383
1384   unsigned Opcode = Inst.getOpcode();
1385   bool NeedsDisjointWritebackTransfer = false;
1386
1387   // First operand is always writeback of base register.
1388   switch (Opcode) {
1389   default:
1390     break;
1391   case AArch64::LDPXpost:
1392   case AArch64::STPXpost:
1393   case AArch64::LDPSWpost:
1394   case AArch64::LDPXpre:
1395   case AArch64::STPXpre:
1396   case AArch64::LDPSWpre:
1397   case AArch64::LDPWpost:
1398   case AArch64::STPWpost:
1399   case AArch64::LDPWpre:
1400   case AArch64::STPWpre:
1401   case AArch64::LDPQpost:
1402   case AArch64::STPQpost:
1403   case AArch64::LDPQpre:
1404   case AArch64::STPQpre:
1405   case AArch64::LDPDpost:
1406   case AArch64::STPDpost:
1407   case AArch64::LDPDpre:
1408   case AArch64::STPDpre:
1409   case AArch64::LDPSpost:
1410   case AArch64::STPSpost:
1411   case AArch64::LDPSpre:
1412   case AArch64::STPSpre:
1413   case AArch64::STGPpre:
1414   case AArch64::STGPpost:
1415     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1416     break;
1417   }
1418
1419   switch (Opcode) {
1420   default:
1421     return Fail;
1422   case AArch64::LDPXpost:
1423   case AArch64::STPXpost:
1424   case AArch64::LDPSWpost:
1425   case AArch64::LDPXpre:
1426   case AArch64::STPXpre:
1427   case AArch64::LDPSWpre:
1428   case AArch64::STGPpre:
1429   case AArch64::STGPpost:
1430     NeedsDisjointWritebackTransfer = true;
1431     LLVM_FALLTHROUGH;
1432   case AArch64::LDNPXi:
1433   case AArch64::STNPXi:
1434   case AArch64::LDPXi:
1435   case AArch64::STPXi:
1436   case AArch64::LDPSWi:
1437   case AArch64::STGPi:
1438     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1439     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1440     break;
1441   case AArch64::LDPWpost:
1442   case AArch64::STPWpost:
1443   case AArch64::LDPWpre:
1444   case AArch64::STPWpre:
1445     NeedsDisjointWritebackTransfer = true;
1446     LLVM_FALLTHROUGH;
1447   case AArch64::LDNPWi:
1448   case AArch64::STNPWi:
1449   case AArch64::LDPWi:
1450   case AArch64::STPWi:
1451     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1452     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1453     break;
1454   case AArch64::LDNPQi:
1455   case AArch64::STNPQi:
1456   case AArch64::LDPQpost:
1457   case AArch64::STPQpost:
1458   case AArch64::LDPQi:
1459   case AArch64::STPQi:
1460   case AArch64::LDPQpre:
1461   case AArch64::STPQpre:
1462     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1463     DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1464     break;
1465   case AArch64::LDNPDi:
1466   case AArch64::STNPDi:
1467   case AArch64::LDPDpost:
1468   case AArch64::STPDpost:
1469   case AArch64::LDPDi:
1470   case AArch64::STPDi:
1471   case AArch64::LDPDpre:
1472   case AArch64::STPDpre:
1473     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1474     DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1475     break;
1476   case AArch64::LDNPSi:
1477   case AArch64::STNPSi:
1478   case AArch64::LDPSpost:
1479   case AArch64::STPSpost:
1480   case AArch64::LDPSi:
1481   case AArch64::STPSi:
1482   case AArch64::LDPSpre:
1483   case AArch64::STPSpre:
1484     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1485     DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1486     break;
1487   }
1488
1489   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1490   Inst.addOperand(MCOperand::createImm(offset));
1491
1492   // You shouldn't load to the same register twice in an instruction...
1493   if (IsLoad && Rt == Rt2)
1494     return SoftFail;
1495
1496   // ... or do any operation that writes-back to a transfer register. But note
1497   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1498   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1499     return SoftFail;
1500
1501   return Success;
1502 }
1503
1504 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1505                                                 uint64_t Addr,
1506                                                 const void *Decoder) {
1507   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1508   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1509   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1510   unsigned extend = fieldFromInstruction(insn, 10, 6);
1511
1512   unsigned shift = extend & 0x7;
1513   if (shift > 4)
1514     return Fail;
1515
1516   switch (Inst.getOpcode()) {
1517   default:
1518     return Fail;
1519   case AArch64::ADDWrx:
1520   case AArch64::SUBWrx:
1521     DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1522     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1523     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1524     break;
1525   case AArch64::ADDSWrx:
1526   case AArch64::SUBSWrx:
1527     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1528     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1529     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1530     break;
1531   case AArch64::ADDXrx:
1532   case AArch64::SUBXrx:
1533     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1534     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1535     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1536     break;
1537   case AArch64::ADDSXrx:
1538   case AArch64::SUBSXrx:
1539     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1540     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1541     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1542     break;
1543   case AArch64::ADDXrx64:
1544   case AArch64::SUBXrx64:
1545     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1546     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1547     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1548     break;
1549   case AArch64::SUBSXrx64:
1550   case AArch64::ADDSXrx64:
1551     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1552     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1553     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1554     break;
1555   }
1556
1557   Inst.addOperand(MCOperand::createImm(extend));
1558   return Success;
1559 }
1560
1561 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1562                                                 uint64_t Addr,
1563                                                 const void *Decoder) {
1564   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1565   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1566   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1567   unsigned imm;
1568
1569   if (Datasize) {
1570     if (Inst.getOpcode() == AArch64::ANDSXri)
1571       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1572     else
1573       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1574     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1575     imm = fieldFromInstruction(insn, 10, 13);
1576     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1577       return Fail;
1578   } else {
1579     if (Inst.getOpcode() == AArch64::ANDSWri)
1580       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1581     else
1582       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1583     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1584     imm = fieldFromInstruction(insn, 10, 12);
1585     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1586       return Fail;
1587   }
1588   Inst.addOperand(MCOperand::createImm(imm));
1589   return Success;
1590 }
1591
1592 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1593                                             uint64_t Addr,
1594                                             const void *Decoder) {
1595   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1596   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1597   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1598   imm |= fieldFromInstruction(insn, 5, 5);
1599
1600   if (Inst.getOpcode() == AArch64::MOVID)
1601     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1602   else
1603     DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1604
1605   Inst.addOperand(MCOperand::createImm(imm));
1606
1607   switch (Inst.getOpcode()) {
1608   default:
1609     break;
1610   case AArch64::MOVIv4i16:
1611   case AArch64::MOVIv8i16:
1612   case AArch64::MVNIv4i16:
1613   case AArch64::MVNIv8i16:
1614   case AArch64::MOVIv2i32:
1615   case AArch64::MOVIv4i32:
1616   case AArch64::MVNIv2i32:
1617   case AArch64::MVNIv4i32:
1618     Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1619     break;
1620   case AArch64::MOVIv2s_msl:
1621   case AArch64::MOVIv4s_msl:
1622   case AArch64::MVNIv2s_msl:
1623   case AArch64::MVNIv4s_msl:
1624     Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1625     break;
1626   }
1627
1628   return Success;
1629 }
1630
1631 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1632                                                 uint64_t Addr,
1633                                                 const void *Decoder) {
1634   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1635   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1636   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1637   imm |= fieldFromInstruction(insn, 5, 5);
1638
1639   // Tied operands added twice.
1640   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1641   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1642
1643   Inst.addOperand(MCOperand::createImm(imm));
1644   Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1645
1646   return Success;
1647 }
1648
1649 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1650                                          uint64_t Addr, const void *Decoder) {
1651   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1652   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1653   imm |= fieldFromInstruction(insn, 29, 2);
1654   const AArch64Disassembler *Dis =
1655       static_cast<const AArch64Disassembler *>(Decoder);
1656
1657   // Sign-extend the 21-bit immediate.
1658   if (imm & (1 << (21 - 1)))
1659     imm |= ~((1LL << 21) - 1);
1660
1661   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1662   if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1663     Inst.addOperand(MCOperand::createImm(imm));
1664
1665   return Success;
1666 }
1667
1668 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1669                                          uint64_t Addr, const void *Decoder) {
1670   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1671   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1672   unsigned Imm = fieldFromInstruction(insn, 10, 14);
1673   unsigned S = fieldFromInstruction(insn, 29, 1);
1674   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1675
1676   unsigned ShifterVal = (Imm >> 12) & 3;
1677   unsigned ImmVal = Imm & 0xFFF;
1678   const AArch64Disassembler *Dis =
1679       static_cast<const AArch64Disassembler *>(Decoder);
1680
1681   if (ShifterVal != 0 && ShifterVal != 1)
1682     return Fail;
1683
1684   if (Datasize) {
1685     if (Rd == 31 && !S)
1686       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1687     else
1688       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1689     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1690   } else {
1691     if (Rd == 31 && !S)
1692       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1693     else
1694       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1695     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1696   }
1697
1698   if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1699     Inst.addOperand(MCOperand::createImm(ImmVal));
1700   Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1701   return Success;
1702 }
1703
1704 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1705                                               uint64_t Addr,
1706                                               const void *Decoder) {
1707   int64_t imm = fieldFromInstruction(insn, 0, 26);
1708   const AArch64Disassembler *Dis =
1709       static_cast<const AArch64Disassembler *>(Decoder);
1710
1711   // Sign-extend the 26-bit immediate.
1712   if (imm & (1 << (26 - 1)))
1713     imm |= ~((1LL << 26) - 1);
1714
1715   if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1716     Inst.addOperand(MCOperand::createImm(imm));
1717
1718   return Success;
1719 }
1720
1721 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1722                                                   uint64_t Addr,
1723                                                   const void *Decoder) {
1724   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1725   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1726   uint64_t crm = fieldFromInstruction(insn, 8, 4);
1727   uint64_t pstate_field = (op1 << 3) | op2;
1728
1729   switch (pstate_field) {
1730   case 0x01: // XAFlag
1731   case 0x02: // AXFlag
1732     return Fail;
1733   }
1734
1735   if ((pstate_field == AArch64PState::PAN  ||
1736        pstate_field == AArch64PState::UAO  ||
1737        pstate_field == AArch64PState::SSBS) && crm > 1)
1738     return Fail;
1739
1740   Inst.addOperand(MCOperand::createImm(pstate_field));
1741   Inst.addOperand(MCOperand::createImm(crm));
1742
1743   const AArch64Disassembler *Dis =
1744       static_cast<const AArch64Disassembler *>(Decoder);
1745   auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1746   if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1747     return Success;
1748   return Fail;
1749 }
1750
1751 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1752                                         uint64_t Addr, const void *Decoder) {
1753   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1754   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1755   bit |= fieldFromInstruction(insn, 19, 5);
1756   int64_t dst = fieldFromInstruction(insn, 5, 14);
1757   const AArch64Disassembler *Dis =
1758       static_cast<const AArch64Disassembler *>(Decoder);
1759
1760   // Sign-extend 14-bit immediate.
1761   if (dst & (1 << (14 - 1)))
1762     dst |= ~((1LL << 14) - 1);
1763
1764   if (fieldFromInstruction(insn, 31, 1) == 0)
1765     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1766   else
1767     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1768   Inst.addOperand(MCOperand::createImm(bit));
1769   if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1770     Inst.addOperand(MCOperand::createImm(dst));
1771
1772   return Success;
1773 }
1774
1775 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1776                                                         unsigned RegClassID,
1777                                                         unsigned RegNo,
1778                                                         uint64_t Addr,
1779                                                         const void *Decoder) {
1780   // Register number must be even (see CASP instruction)
1781   if (RegNo & 0x1)
1782     return Fail;
1783
1784   unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1785   Inst.addOperand(MCOperand::createReg(Reg));
1786   return Success;
1787 }
1788
1789 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1790                                                       unsigned RegNo,
1791                                                       uint64_t Addr,
1792                                                       const void *Decoder) {
1793   return DecodeGPRSeqPairsClassRegisterClass(Inst,
1794                                              AArch64::WSeqPairsClassRegClassID,
1795                                              RegNo, Addr, Decoder);
1796 }
1797
1798 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1799                                                       unsigned RegNo,
1800                                                       uint64_t Addr,
1801                                                       const void *Decoder) {
1802   return DecodeGPRSeqPairsClassRegisterClass(Inst,
1803                                              AArch64::XSeqPairsClassRegClassID,
1804                                              RegNo, Addr, Decoder);
1805 }
1806
1807 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1808                                                    uint32_t insn,
1809                                                    uint64_t Addr,
1810                                                    const void *Decoder) {
1811   unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1812   unsigned imm = fieldFromInstruction(insn, 5, 13);
1813   if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1814     return Fail;
1815
1816   // The same (tied) operand is added twice to the instruction.
1817   DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1818   if (Inst.getOpcode() != AArch64::DUPM_ZI)
1819     DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1820   Inst.addOperand(MCOperand::createImm(imm));
1821   return Success;
1822 }
1823
1824 template<int Bits>
1825 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1826                                uint64_t Address, const void *Decoder) {
1827   if (Imm & ~((1LL << Bits) - 1))
1828       return Fail;
1829
1830   // Imm is a signed immediate, so sign extend it.
1831   if (Imm & (1 << (Bits - 1)))
1832     Imm |= ~((1LL << Bits) - 1);
1833
1834   Inst.addOperand(MCOperand::createImm(Imm));
1835   return Success;
1836 }
1837
1838 // Decode 8-bit signed/unsigned immediate for a given element width.
1839 template <int ElementWidth>
1840 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1841                                       uint64_t Addr, const void *Decoder) {
1842   unsigned Val = (uint8_t)Imm;
1843   unsigned Shift = (Imm & 0x100) ? 8 : 0;
1844   if (ElementWidth == 8 && Shift)
1845     return Fail;
1846   Inst.addOperand(MCOperand::createImm(Val));
1847   Inst.addOperand(MCOperand::createImm(Shift));
1848   return Success;
1849 }
1850
1851 // Decode uimm4 ranged from 1-16.
1852 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1853                                        uint64_t Addr, const void *Decoder) {
1854   Inst.addOperand(MCOperand::createImm(Imm + 1));
1855   return Success;
1856 }