1 //=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
11 //===----------------------------------------------------------------------===//
13 def SVEPatternOperand : AsmOperandClass {
14 let Name = "SVEPattern";
15 let ParserMethod = "tryParseSVEPattern";
16 let PredicateMethod = "isSVEPattern";
17 let RenderMethod = "addImmOperands";
18 let DiagnosticType = "InvalidSVEPattern";
21 def sve_pred_enum : Operand<i32>, TImmLeaf<i32, [{
22 return (((uint32_t)Imm) < 32);
25 let PrintMethod = "printSVEPattern";
26 let ParserMatchClass = SVEPatternOperand;
29 def SVEPrefetchOperand : AsmOperandClass {
30 let Name = "SVEPrefetch";
31 let ParserMethod = "tryParsePrefetch<true>";
32 let PredicateMethod = "isPrefetch";
33 let RenderMethod = "addPrefetchOperands";
36 def sve_prfop : Operand<i32>, ImmLeaf<i32, [{
37 return (((uint32_t)Imm) <= 15);
39 let PrintMethod = "printPrefetchOp<true>";
40 let ParserMatchClass = SVEPrefetchOperand;
43 class SVELogicalImmOperand<int Width> : AsmOperandClass {
44 let Name = "SVELogicalImm" # Width;
45 let DiagnosticType = "LogicalSecondSource";
46 let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
47 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
50 def sve_logical_imm8 : Operand<i64> {
51 let ParserMatchClass = SVELogicalImmOperand<8>;
52 let PrintMethod = "printLogicalImm<int8_t>";
54 let MCOperandPredicate = [{
57 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
58 return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
62 def sve_logical_imm16 : Operand<i64> {
63 let ParserMatchClass = SVELogicalImmOperand<16>;
64 let PrintMethod = "printLogicalImm<int16_t>";
66 let MCOperandPredicate = [{
69 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
70 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
74 def sve_logical_imm32 : Operand<i64> {
75 let ParserMatchClass = SVELogicalImmOperand<32>;
76 let PrintMethod = "printLogicalImm<int32_t>";
78 let MCOperandPredicate = [{
81 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
82 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
86 class SVEPreferredLogicalImmOperand<int Width> : AsmOperandClass {
87 let Name = "SVEPreferredLogicalImm" # Width;
88 let PredicateMethod = "isSVEPreferredLogicalImm<int" # Width # "_t>";
89 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
92 def sve_preferred_logical_imm16 : Operand<i64> {
93 let ParserMatchClass = SVEPreferredLogicalImmOperand<16>;
94 let PrintMethod = "printSVELogicalImm<int16_t>";
96 let MCOperandPredicate = [{
99 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
100 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
101 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
105 def sve_preferred_logical_imm32 : Operand<i64> {
106 let ParserMatchClass = SVEPreferredLogicalImmOperand<32>;
107 let PrintMethod = "printSVELogicalImm<int32_t>";
109 let MCOperandPredicate = [{
112 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
113 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) &&
114 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
118 def sve_preferred_logical_imm64 : Operand<i64> {
119 let ParserMatchClass = SVEPreferredLogicalImmOperand<64>;
120 let PrintMethod = "printSVELogicalImm<int64_t>";
122 let MCOperandPredicate = [{
125 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
126 return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) &&
127 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
131 class SVELogicalImmNotOperand<int Width> : AsmOperandClass {
132 let Name = "SVELogicalImm" # Width # "Not";
133 let DiagnosticType = "LogicalSecondSource";
134 let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
135 let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>";
138 def sve_logical_imm8_not : Operand<i64> {
139 let ParserMatchClass = SVELogicalImmNotOperand<8>;
142 def sve_logical_imm16_not : Operand<i64> {
143 let ParserMatchClass = SVELogicalImmNotOperand<16>;
146 def sve_logical_imm32_not : Operand<i64> {
147 let ParserMatchClass = SVELogicalImmNotOperand<32>;
150 class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate>
152 let Name = "SVE" # Infix # "Imm" # ElementWidth;
153 let DiagnosticType = "Invalid" # Name;
154 let RenderMethod = "addImmWithOptionalShiftOperands<8>";
155 let ParserMethod = "tryParseImmWithOptionalShift";
156 let PredicateMethod = Predicate;
159 def SVECpyImmOperand8 : SVEShiftedImmOperand<8, "Cpy", "isSVECpyImm<int8_t>">;
160 def SVECpyImmOperand16 : SVEShiftedImmOperand<16, "Cpy", "isSVECpyImm<int16_t>">;
161 def SVECpyImmOperand32 : SVEShiftedImmOperand<32, "Cpy", "isSVECpyImm<int32_t>">;
162 def SVECpyImmOperand64 : SVEShiftedImmOperand<64, "Cpy", "isSVECpyImm<int64_t>">;
164 def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">;
165 def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">;
166 def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">;
167 def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">;
169 class imm8_opt_lsl<int ElementWidth, string printType,
170 AsmOperandClass OpndClass, code Predicate>
171 : Operand<i32>, ImmLeaf<i32, Predicate> {
172 let EncoderMethod = "getImm8OptLsl";
173 let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">";
174 let PrintMethod = "printImm8OptLsl<" # printType # ">";
175 let ParserMatchClass = OpndClass;
176 let MIOperandInfo = (ops i32imm, i32imm);
179 def cpy_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "int8_t", SVECpyImmOperand8, [{
180 return AArch64_AM::isSVECpyImm<int8_t>(Imm);
182 def cpy_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "int16_t", SVECpyImmOperand16, [{
183 return AArch64_AM::isSVECpyImm<int16_t>(Imm);
185 def cpy_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "int32_t", SVECpyImmOperand32, [{
186 return AArch64_AM::isSVECpyImm<int32_t>(Imm);
188 def cpy_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "int64_t", SVECpyImmOperand64, [{
189 return AArch64_AM::isSVECpyImm<int64_t>(Imm);
192 def addsub_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "uint8_t", SVEAddSubImmOperand8, [{
193 return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
195 def addsub_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "uint16_t", SVEAddSubImmOperand16, [{
196 return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
198 def addsub_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "uint32_t", SVEAddSubImmOperand32, [{
199 return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
201 def addsub_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "uint64_t", SVEAddSubImmOperand64, [{
202 return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
205 def SVEAddSubImm8Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i8>", []>;
206 def SVEAddSubImm16Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i16>", []>;
207 def SVEAddSubImm32Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i32>", []>;
208 def SVEAddSubImm64Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i64>", []>;
210 def SVELogicalImm8Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i8>", []>;
211 def SVELogicalImm16Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i16>", []>;
212 def SVELogicalImm32Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i32>", []>;
213 def SVELogicalImm64Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i64>", []>;
215 def SVEArithUImmPat : ComplexPattern<i32, 1, "SelectSVEArithImm", []>;
216 def SVEArithSImmPat : ComplexPattern<i32, 1, "SelectSVESignedArithImm", []>;
218 class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass {
219 let Name = "SVEExactFPImmOperand" # Suffix;
220 let DiagnosticType = "Invalid" # Name;
221 let ParserMethod = "tryParseFPImm<false>";
222 let PredicateMethod = "isExactFPImm<" # ValA # ", " # ValB # ">";
223 let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">";
226 class SVEExactFPImmOperand<string Suffix, string ValA, string ValB> : Operand<i32> {
227 let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">";
228 let ParserMatchClass = SVEExactFPImm<Suffix, ValA, ValB>;
231 def sve_fpimm_half_one
232 : SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half",
233 "AArch64ExactFPImm::one">;
234 def sve_fpimm_half_two
235 : SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half",
236 "AArch64ExactFPImm::two">;
237 def sve_fpimm_zero_one
238 : SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero",
239 "AArch64ExactFPImm::one">;
241 def sve_incdec_imm : Operand<i32>, TImmLeaf<i32, [{
242 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
244 let ParserMatchClass = Imm1_16Operand;
245 let EncoderMethod = "getSVEIncDecImm";
246 let DecoderMethod = "DecodeSVEIncDecImm";
249 // This allows i32 immediate extraction from i64 based arithmetic.
250 def sve_cnt_mul_imm : ComplexPattern<i32, 1, "SelectCntImm<1, 16, 1, false>">;
251 def sve_cnt_shl_imm : ComplexPattern<i32, 1, "SelectCntImm<1, 16, 1, true>">;
253 //===----------------------------------------------------------------------===//
254 // SVE PTrue - These are used extensively throughout the pattern matching so
255 // it's important we define them first.
256 //===----------------------------------------------------------------------===//
258 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
259 ValueType vt, SDPatternOperator op>
260 : I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern),
261 asm, "\t$Pd, $pattern",
263 [(set (vt pprty:$Pd), (op sve_pred_enum:$pattern))]>, Sched<[]> {
266 let Inst{31-24} = 0b00100101;
267 let Inst{23-22} = sz8_64;
268 let Inst{21-19} = 0b011;
269 let Inst{18-17} = opc{2-1};
270 let Inst{16} = opc{0};
271 let Inst{15-10} = 0b111000;
272 let Inst{9-5} = pattern;
276 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
279 multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
280 def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
281 def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
282 def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
283 def _D : sve_int_ptrue<0b11, opc, asm, PPR64, nxv2i1, op>;
285 def : InstAlias<asm # "\t$Pd",
286 (!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>;
287 def : InstAlias<asm # "\t$Pd",
288 (!cast<Instruction>(NAME # _H) PPR16:$Pd, 0b11111), 1>;
289 def : InstAlias<asm # "\t$Pd",
290 (!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>;
291 def : InstAlias<asm # "\t$Pd",
292 (!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>;
295 def SDT_AArch64PTrue : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
296 def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>;
298 let Predicates = [HasSVE] in {
299 defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
300 defm PTRUES : sve_int_ptrue<0b001, "ptrues", null_frag>;
303 //===----------------------------------------------------------------------===//
304 // SVE pattern match helpers.
305 //===----------------------------------------------------------------------===//
307 class SVE_1_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
309 : Pat<(vtd (op vt1:$Op1)),
312 class SVE_1_Op_Imm_OptLsl_Reverse_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty,
313 ValueType it, ComplexPattern cpx, Instruction inst>
314 : Pat<(vt (op (vt (AArch64dup (it (cpx i32:$imm, i32:$shift)))), (vt zprty:$Op1))),
315 (inst $Op1, i32:$imm, i32:$shift)>;
317 class SVE_1_Op_Imm_OptLsl_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty,
318 ValueType it, ComplexPattern cpx, Instruction inst>
319 : Pat<(vt (op (vt zprty:$Op1), (vt (AArch64dup (it (cpx i32:$imm, i32:$shift)))))),
320 (inst $Op1, i32:$imm, i32:$shift)>;
322 class SVE_1_Op_Imm_Arith_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty,
323 ValueType it, ComplexPattern cpx, Instruction inst>
324 : Pat<(vt (op (vt zprty:$Op1), (vt (AArch64dup (it (cpx i32:$imm)))))),
325 (inst $Op1, i32:$imm)>;
327 class SVE_1_Op_Imm_Log_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty,
328 ValueType it, ComplexPattern cpx, Instruction inst>
329 : Pat<(vt (op (vt zprty:$Op1), (vt (AArch64dup (it (cpx i64:$imm)))))),
330 (inst $Op1, i64:$imm)>;
332 class SVE_2_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
333 ValueType vt2, Instruction inst>
334 : Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
337 class SVE_2_Op_Pat_Reduce_To_Neon<ValueType vtd, SDPatternOperator op, ValueType vt1,
338 ValueType vt2, Instruction inst, SubRegIndex sub>
339 : Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
340 (INSERT_SUBREG (vtd (IMPLICIT_DEF)), (inst $Op1, $Op2), sub)>;
342 class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
343 ValueType vt2, ValueType vt3, Instruction inst>
344 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
345 (inst $Op1, $Op2, $Op3)>;
347 class SVE_4_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
348 ValueType vt2, ValueType vt3, ValueType vt4,
350 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
351 (inst $Op1, $Op2, $Op3, $Op4)>;
353 class SVE_2_Op_Imm_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
354 ValueType vt2, Operand ImmTy, Instruction inst>
355 : Pat<(vtd (op vt1:$Op1, (vt2 ImmTy:$Op2))),
356 (inst $Op1, ImmTy:$Op2)>;
358 class SVE_3_Op_Imm_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
359 ValueType vt2, ValueType vt3, Operand ImmTy,
361 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, (vt3 ImmTy:$Op3))),
362 (inst $Op1, $Op2, ImmTy:$Op3)>;
364 class SVE_4_Op_Imm_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
365 ValueType vt2, ValueType vt3, ValueType vt4,
366 Operand ImmTy, Instruction inst>
367 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
368 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
370 def SVEDup0Undef : ComplexPattern<i64, 0, "SelectDupZeroOrUndef", []>;
373 // Common but less generic patterns.
376 class SVE_1_Op_AllActive_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
377 Instruction inst, Instruction ptrue>
378 : Pat<(vtd (op vt1:$Op1)),
379 (inst (IMPLICIT_DEF), (ptrue 31), $Op1)>;
381 //===----------------------------------------------------------------------===//
382 // SVE Predicate Misc Group
383 //===----------------------------------------------------------------------===//
385 class sve_int_pfalse<bits<6> opc, string asm>
386 : I<(outs PPR8:$Pd), (ins),
391 let Inst{31-24} = 0b00100101;
392 let Inst{23-22} = opc{5-4};
393 let Inst{21-19} = 0b011;
394 let Inst{18-16} = opc{3-1};
395 let Inst{15-10} = 0b111001;
396 let Inst{9} = opc{0};
397 let Inst{8-4} = 0b00000;
401 class sve_int_ptest<bits<6> opc, string asm>
402 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
408 let Inst{31-24} = 0b00100101;
409 let Inst{23-22} = opc{5-4};
410 let Inst{21-19} = 0b010;
411 let Inst{18-16} = opc{3-1};
412 let Inst{15-14} = 0b11;
413 let Inst{13-10} = Pg;
414 let Inst{9} = opc{0};
416 let Inst{4-0} = 0b00000;
421 class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm,
423 : I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn),
424 asm, "\t$Pdn, $Pg, $_Pdn",
429 let Inst{31-24} = 0b00100101;
430 let Inst{23-22} = sz8_64;
431 let Inst{21-19} = 0b011;
432 let Inst{18-16} = opc{4-2};
433 let Inst{15-11} = 0b11000;
434 let Inst{10-9} = opc{1-0};
439 let Constraints = "$Pdn = $_Pdn";
443 multiclass sve_int_pfirst<bits<5> opc, string asm, SDPatternOperator op> {
444 def _B : sve_int_pfirst_next<0b01, opc, asm, PPR8>;
446 def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
449 multiclass sve_int_pnext<bits<5> opc, string asm, SDPatternOperator op> {
450 def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>;
451 def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>;
452 def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>;
453 def _D : sve_int_pfirst_next<0b11, opc, asm, PPR64>;
455 def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
456 def : SVE_2_Op_Pat<nxv8i1, op, nxv8i1, nxv8i1, !cast<Instruction>(NAME # _H)>;
457 def : SVE_2_Op_Pat<nxv4i1, op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>;
458 def : SVE_2_Op_Pat<nxv2i1, op, nxv2i1, nxv2i1, !cast<Instruction>(NAME # _D)>;
461 //===----------------------------------------------------------------------===//
462 // SVE Predicate Count Group
463 //===----------------------------------------------------------------------===//
465 class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm,
466 RegisterOperand dty, PPRRegOp pprty, RegisterOperand sty>
467 : I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn),
473 let Inst{31-24} = 0b00100101;
474 let Inst{23-22} = sz8_64;
475 let Inst{21-19} = 0b101;
476 let Inst{18-16} = opc{4-2};
477 let Inst{15-11} = 0b10001;
478 let Inst{10-9} = opc{1-0};
482 // Signed 32bit forms require their GPR operand printed.
483 let AsmString = !if(!eq(opc{4,2-0}, 0b0000),
484 !strconcat(asm, "\t$Rdn, $Pg, $_Rdn"),
485 !strconcat(asm, "\t$Rdn, $Pg"));
486 let Constraints = "$Rdn = $_Rdn";
489 multiclass sve_int_count_r_s32<bits<5> opc, string asm,
490 SDPatternOperator op> {
491 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>;
492 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>;
493 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>;
494 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64as32>;
496 def : Pat<(i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))),
497 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
498 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))))),
499 (!cast<Instruction>(NAME # _B) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32))>;
501 def : Pat<(i32 (op GPR32:$Rn, (nxv8i1 PPRAny:$Pg))),
502 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
503 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (nxv8i1 PPRAny:$Pg))))),
504 (!cast<Instruction>(NAME # _H) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32))>;
506 def : Pat<(i32 (op GPR32:$Rn, (nxv4i1 PPRAny:$Pg))),
507 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
508 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (nxv4i1 PPRAny:$Pg))))),
509 (!cast<Instruction>(NAME # _S) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32))>;
511 def : Pat<(i32 (op GPR32:$Rn, (nxv2i1 PPRAny:$Pg))),
512 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
513 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (nxv2i1 PPRAny:$Pg))))),
514 (!cast<Instruction>(NAME # _D) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32))>;
517 multiclass sve_int_count_r_u32<bits<5> opc, string asm,
518 SDPatternOperator op> {
519 def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>;
520 def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>;
521 def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>;
522 def _D : sve_int_count_r<0b11, opc, asm, GPR32z, PPR64, GPR32z>;
524 def : Pat<(i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))),
525 (!cast<Instruction>(NAME # _B) PPRAny:$Pg, $Rn)>;
526 def : Pat<(i32 (op GPR32:$Rn, (nxv8i1 PPRAny:$Pg))),
527 (!cast<Instruction>(NAME # _H) PPRAny:$Pg, $Rn)>;
528 def : Pat<(i32 (op GPR32:$Rn, (nxv4i1 PPRAny:$Pg))),
529 (!cast<Instruction>(NAME # _S) PPRAny:$Pg, $Rn)>;
530 def : Pat<(i32 (op GPR32:$Rn, (nxv2i1 PPRAny:$Pg))),
531 (!cast<Instruction>(NAME # _D) PPRAny:$Pg, $Rn)>;
534 multiclass sve_int_count_r_x64<bits<5> opc, string asm,
535 SDPatternOperator op = null_frag> {
536 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>;
537 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>;
538 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>;
539 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>;
541 def : Pat<(i64 (op GPR64:$Rn, (nxv16i1 PPRAny:$Pg))),
542 (!cast<Instruction>(NAME # _B) PPRAny:$Pg, $Rn)>;
543 def : Pat<(i64 (op GPR64:$Rn, (nxv8i1 PPRAny:$Pg))),
544 (!cast<Instruction>(NAME # _H) PPRAny:$Pg, $Rn)>;
545 def : Pat<(i64 (op GPR64:$Rn, (nxv4i1 PPRAny:$Pg))),
546 (!cast<Instruction>(NAME # _S) PPRAny:$Pg, $Rn)>;
547 def : Pat<(i64 (op GPR64:$Rn, (nxv2i1 PPRAny:$Pg))),
548 (!cast<Instruction>(NAME # _D) PPRAny:$Pg, $Rn)>;
551 class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
552 ZPRRegOp zprty, PPRRegOp pprty>
553 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
559 let Inst{31-24} = 0b00100101;
560 let Inst{23-22} = sz8_64;
561 let Inst{21-19} = 0b101;
562 let Inst{18-16} = opc{4-2};
563 let Inst{15-11} = 0b10000;
564 let Inst{10-9} = opc{1-0};
568 let Constraints = "$Zdn = $_Zdn";
569 let DestructiveInstType = Destructive;
570 let ElementSize = ElementSizeNone;
573 multiclass sve_int_count_v<bits<5> opc, string asm,
574 SDPatternOperator op = null_frag> {
575 def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
576 def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
577 def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
579 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, !cast<Instruction>(NAME # _H)>;
580 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, !cast<Instruction>(NAME # _S)>;
581 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, !cast<Instruction>(NAME # _D)>;
583 def : InstAlias<asm # "\t$Zdn, $Pm",
584 (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
585 def : InstAlias<asm # "\t$Zdn, $Pm",
586 (!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
587 def : InstAlias<asm # "\t$Zdn, $Pm",
588 (!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
591 class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,
593 : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
594 asm, "\t$Rd, $Pg, $Pn",
600 let Inst{31-24} = 0b00100101;
601 let Inst{23-22} = sz8_64;
602 let Inst{21-19} = 0b100;
603 let Inst{18-16} = opc{3-1};
604 let Inst{15-14} = 0b10;
605 let Inst{13-10} = Pg;
606 let Inst{9} = opc{0};
611 multiclass sve_int_pcount_pred<bits<4> opc, string asm,
612 SDPatternOperator int_op> {
613 def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>;
614 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
615 def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>;
616 def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>;
618 def : SVE_2_Op_Pat<i64, int_op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
619 def : SVE_2_Op_Pat<i64, int_op, nxv8i1, nxv8i1, !cast<Instruction>(NAME # _H)>;
620 def : SVE_2_Op_Pat<i64, int_op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>;
621 def : SVE_2_Op_Pat<i64, int_op, nxv2i1, nxv2i1, !cast<Instruction>(NAME # _D)>;
624 //===----------------------------------------------------------------------===//
625 // SVE Element Count Group
626 //===----------------------------------------------------------------------===//
628 class sve_int_count<bits<3> opc, string asm>
629 : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
630 asm, "\t$Rd, $pattern, mul $imm4",
636 let Inst{31-24} = 0b00000100;
637 let Inst{23-22} = opc{2-1};
638 let Inst{21-20} = 0b10;
639 let Inst{19-16} = imm4;
640 let Inst{15-11} = 0b11100;
641 let Inst{10} = opc{0};
642 let Inst{9-5} = pattern;
646 multiclass sve_int_count<bits<3> opc, string asm, SDPatternOperator op> {
647 def NAME : sve_int_count<opc, asm>;
649 def : InstAlias<asm # "\t$Rd, $pattern",
650 (!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>;
651 def : InstAlias<asm # "\t$Rd",
652 (!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>;
654 def : Pat<(i64 (mul (op sve_pred_enum:$pattern), (sve_cnt_mul_imm i32:$imm))),
655 (!cast<Instruction>(NAME) sve_pred_enum:$pattern, sve_incdec_imm:$imm)>;
657 def : Pat<(i64 (shl (op sve_pred_enum:$pattern), (i64 (sve_cnt_shl_imm i32:$imm)))),
658 (!cast<Instruction>(NAME) sve_pred_enum:$pattern, sve_incdec_imm:$imm)>;
660 def : Pat<(i64 (op sve_pred_enum:$pattern)),
661 (!cast<Instruction>(NAME) sve_pred_enum:$pattern, 1)>;
664 class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
665 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
666 asm, "\t$Zdn, $pattern, mul $imm4",
672 let Inst{31-24} = 0b00000100;
673 let Inst{23-22} = opc{4-3};
675 let Inst{20} = opc{2};
676 let Inst{19-16} = imm4;
677 let Inst{15-12} = 0b1100;
678 let Inst{11-10} = opc{1-0};
679 let Inst{9-5} = pattern;
682 let Constraints = "$Zdn = $_Zdn";
683 let DestructiveInstType = Destructive;
684 let ElementSize = ElementSizeNone;
687 multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty,
688 SDPatternOperator op = null_frag,
689 ValueType vt = OtherVT> {
690 def NAME : sve_int_countvlv<opc, asm, zprty>;
692 def : InstAlias<asm # "\t$Zdn, $pattern",
693 (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
694 def : InstAlias<asm # "\t$Zdn",
695 (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>;
697 def : Pat<(vt (op (vt zprty:$Zn), (sve_pred_enum:$pattern), (sve_incdec_imm:$imm4))),
698 (!cast<Instruction>(NAME) $Zn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4)>;
701 class sve_int_pred_pattern_a<bits<3> opc, string asm>
702 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
703 asm, "\t$Rdn, $pattern, mul $imm4",
709 let Inst{31-24} = 0b00000100;
710 let Inst{23-22} = opc{2-1};
711 let Inst{21-20} = 0b11;
712 let Inst{19-16} = imm4;
713 let Inst{15-11} = 0b11100;
714 let Inst{10} = opc{0};
715 let Inst{9-5} = pattern;
718 let Constraints = "$Rdn = $_Rdn";
721 multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> {
722 def NAME : sve_int_pred_pattern_a<opc, asm>;
724 def : InstAlias<asm # "\t$Rdn, $pattern",
725 (!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>;
726 def : InstAlias<asm # "\t$Rdn",
727 (!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
730 class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
732 : I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
733 asm, "\t$Rdn, $pattern, mul $imm4",
739 let Inst{31-24} = 0b00000100;
740 let Inst{23-22} = opc{4-3};
742 let Inst{20} = opc{2};
743 let Inst{19-16} = imm4;
744 let Inst{15-12} = 0b1111;
745 let Inst{11-10} = opc{1-0};
746 let Inst{9-5} = pattern;
749 // Signed 32bit forms require their GPR operand printed.
750 let AsmString = !if(!eq(opc{2,0}, 0b00),
751 !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"),
752 !strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));
754 let Constraints = "$Rdn = $_Rdn";
757 multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm,
758 SDPatternOperator op> {
759 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;
761 def : InstAlias<asm # "\t$Rd, $Rn, $pattern",
762 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>;
763 def : InstAlias<asm # "\t$Rd, $Rn",
764 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>;
766 // NOTE: Register allocation doesn't like tied operands of differing register
767 // class, hence the extra INSERT_SUBREG complication.
769 def : Pat<(i32 (op GPR32:$Rn, (sve_pred_enum:$pattern), (sve_incdec_imm:$imm4))),
770 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32), sve_pred_enum:$pattern, sve_incdec_imm:$imm4), sub_32)>;
771 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (sve_pred_enum:$pattern), (sve_incdec_imm:$imm4))))),
772 (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32), sve_pred_enum:$pattern, sve_incdec_imm:$imm4)>;
775 multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm,
776 SDPatternOperator op> {
777 def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;
779 def : InstAlias<asm # "\t$Rdn, $pattern",
780 (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
781 def : InstAlias<asm # "\t$Rdn",
782 (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;
784 def : Pat<(i32 (op GPR32:$Rn, (sve_pred_enum:$pattern), (sve_incdec_imm:$imm4))),
785 (!cast<Instruction>(NAME) $Rn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4)>;
788 multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm,
789 SDPatternOperator op> {
790 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
792 def : InstAlias<asm # "\t$Rdn, $pattern",
793 (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
794 def : InstAlias<asm # "\t$Rdn",
795 (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
797 def : Pat<(i64 (op GPR64:$Rn, (sve_pred_enum:$pattern), (sve_incdec_imm:$imm4))),
798 (!cast<Instruction>(NAME) $Rn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4)>;
802 //===----------------------------------------------------------------------===//
803 // SVE Permute - Cross Lane Group
804 //===----------------------------------------------------------------------===//
806 class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
807 ValueType vt, RegisterClass srcRegType,
808 SDPatternOperator op>
809 : I<(outs zprty:$Zd), (ins srcRegType:$Rn),
812 [(set (vt zprty:$Zd), (op srcRegType:$Rn))]>, Sched<[]> {
815 let Inst{31-24} = 0b00000101;
816 let Inst{23-22} = sz8_64;
817 let Inst{21-10} = 0b100000001110;
822 multiclass sve_int_perm_dup_r<string asm, SDPatternOperator op> {
823 def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, nxv16i8, GPR32sp, op>;
824 def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, nxv8i16, GPR32sp, op>;
825 def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, nxv4i32, GPR32sp, op>;
826 def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, nxv2i64, GPR64sp, op>;
828 def : InstAlias<"mov $Zd, $Rn",
829 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>;
830 def : InstAlias<"mov $Zd, $Rn",
831 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>;
832 def : InstAlias<"mov $Zd, $Rn",
833 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>;
834 def : InstAlias<"mov $Zd, $Rn",
835 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>;
838 class sve_int_perm_dup_i<bits<5> tsz, Operand immtype, string asm,
840 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$idx),
841 asm, "\t$Zd, $Zn$idx",
847 let Inst{31-24} = 0b00000101;
848 let Inst{23-22} = {?,?}; // imm3h
850 let Inst{20-16} = tsz;
851 let Inst{15-10} = 0b001000;
856 multiclass sve_int_perm_dup_i<string asm> {
857 def _B : sve_int_perm_dup_i<{?,?,?,?,1}, sve_elm_idx_extdup_b, asm, ZPR8> {
858 let Inst{23-22} = idx{5-4};
859 let Inst{20-17} = idx{3-0};
861 def _H : sve_int_perm_dup_i<{?,?,?,1,0}, sve_elm_idx_extdup_h, asm, ZPR16> {
862 let Inst{23-22} = idx{4-3};
863 let Inst{20-18} = idx{2-0};
865 def _S : sve_int_perm_dup_i<{?,?,1,0,0}, sve_elm_idx_extdup_s, asm, ZPR32> {
866 let Inst{23-22} = idx{3-2};
867 let Inst{20-19} = idx{1-0};
869 def _D : sve_int_perm_dup_i<{?,1,0,0,0}, sve_elm_idx_extdup_d, asm, ZPR64> {
870 let Inst{23-22} = idx{2-1};
871 let Inst{20} = idx{0};
873 def _Q : sve_int_perm_dup_i<{1,0,0,0,0}, sve_elm_idx_extdup_q, asm, ZPR128> {
874 let Inst{23-22} = idx{1-0};
877 def : InstAlias<"mov $Zd, $Zn$idx",
878 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx), 1>;
879 def : InstAlias<"mov $Zd, $Zn$idx",
880 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>;
881 def : InstAlias<"mov $Zd, $Zn$idx",
882 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>;
883 def : InstAlias<"mov $Zd, $Zn$idx",
884 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>;
885 def : InstAlias<"mov $Zd, $Zn$idx",
886 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>;
887 def : InstAlias<"mov $Zd, $Bn",
888 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>;
889 def : InstAlias<"mov $Zd, $Hn",
890 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>;
891 def : InstAlias<"mov $Zd, $Sn",
892 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>;
893 def : InstAlias<"mov $Zd, $Dn",
894 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>;
895 def : InstAlias<"mov $Zd, $Qn",
896 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
899 class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm,
900 ZPRRegOp zprty, RegisterOperand VecList>
901 : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
902 asm, "\t$Zd, $Zn, $Zm",
908 let Inst{31-24} = 0b00000101;
909 let Inst{23-22} = sz8_64;
911 let Inst{20-16} = Zm;
912 let Inst{15-13} = 0b001;
913 let Inst{12-11} = opc;
919 multiclass sve_int_perm_tbl<string asm, SDPatternOperator op> {
920 def _B : sve_int_perm_tbl<0b00, 0b10, asm, ZPR8, Z_b>;
921 def _H : sve_int_perm_tbl<0b01, 0b10, asm, ZPR16, Z_h>;
922 def _S : sve_int_perm_tbl<0b10, 0b10, asm, ZPR32, Z_s>;
923 def _D : sve_int_perm_tbl<0b11, 0b10, asm, ZPR64, Z_d>;
925 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
926 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
927 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
928 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>;
929 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
930 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>;
931 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
932 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
934 def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
935 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
936 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
937 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
939 def : SVE_2_Op_Pat<nxv8f16, op, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>;
940 def : SVE_2_Op_Pat<nxv4f32, op, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>;
941 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
944 multiclass sve2_int_perm_tbl<string asm> {
945 def _B : sve_int_perm_tbl<0b00, 0b01, asm, ZPR8, ZZ_b>;
946 def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>;
947 def _S : sve_int_perm_tbl<0b10, 0b01, asm, ZPR32, ZZ_s>;
948 def _D : sve_int_perm_tbl<0b11, 0b01, asm, ZPR64, ZZ_d>;
951 class sve2_int_perm_tbx<bits<2> sz8_64, string asm, ZPRRegOp zprty>
952 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, zprty:$Zm),
953 asm, "\t$Zd, $Zn, $Zm",
959 let Inst{31-24} = 0b00000101;
960 let Inst{23-22} = sz8_64;
962 let Inst{20-16} = Zm;
963 let Inst{15-10} = 0b001011;
967 let Constraints = "$Zd = $_Zd";
970 multiclass sve2_int_perm_tbx<string asm> {
971 def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>;
972 def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>;
973 def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>;
974 def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>;
977 class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty>
978 : I<(outs zprty:$Zd), (ins zprty:$Zn),
984 let Inst{31-24} = 0b00000101;
985 let Inst{23-22} = sz8_64;
986 let Inst{21-10} = 0b111000001110;
991 multiclass sve_int_perm_reverse_z<string asm, SDPatternOperator op> {
992 def _B : sve_int_perm_reverse_z<0b00, asm, ZPR8>;
993 def _H : sve_int_perm_reverse_z<0b01, asm, ZPR16>;
994 def _S : sve_int_perm_reverse_z<0b10, asm, ZPR32>;
995 def _D : sve_int_perm_reverse_z<0b11, asm, ZPR64>;
997 def : SVE_1_Op_Pat<nxv16i8, op, nxv16i8, !cast<Instruction>(NAME # _B)>;
998 def : SVE_1_Op_Pat<nxv8i16, op, nxv8i16, !cast<Instruction>(NAME # _H)>;
999 def : SVE_1_Op_Pat<nxv4i32, op, nxv4i32, !cast<Instruction>(NAME # _S)>;
1000 def : SVE_1_Op_Pat<nxv2i64, op, nxv2i64, !cast<Instruction>(NAME # _D)>;
1002 def : SVE_1_Op_Pat<nxv8f16, op, nxv8f16, !cast<Instruction>(NAME # _H)>;
1003 def : SVE_1_Op_Pat<nxv4f32, op, nxv4f32, !cast<Instruction>(NAME # _S)>;
1004 def : SVE_1_Op_Pat<nxv2f64, op, nxv2f64, !cast<Instruction>(NAME # _D)>;
1007 class sve_int_perm_reverse_p<bits<2> sz8_64, string asm, PPRRegOp pprty>
1008 : I<(outs pprty:$Pd), (ins pprty:$Pn),
1014 let Inst{31-24} = 0b00000101;
1015 let Inst{23-22} = sz8_64;
1016 let Inst{21-9} = 0b1101000100000;
1022 multiclass sve_int_perm_reverse_p<string asm, SDPatternOperator op> {
1023 def _B : sve_int_perm_reverse_p<0b00, asm, PPR8>;
1024 def _H : sve_int_perm_reverse_p<0b01, asm, PPR16>;
1025 def _S : sve_int_perm_reverse_p<0b10, asm, PPR32>;
1026 def _D : sve_int_perm_reverse_p<0b11, asm, PPR64>;
1028 def : SVE_1_Op_Pat<nxv16i1, op, nxv16i1, !cast<Instruction>(NAME # _B)>;
1029 def : SVE_1_Op_Pat<nxv8i1, op, nxv8i1, !cast<Instruction>(NAME # _H)>;
1030 def : SVE_1_Op_Pat<nxv4i1, op, nxv4i1, !cast<Instruction>(NAME # _S)>;
1031 def : SVE_1_Op_Pat<nxv2i1, op, nxv2i1, !cast<Instruction>(NAME # _D)>;
1034 class sve_int_perm_unpk<bits<2> sz16_64, bits<2> opc, string asm,
1035 ZPRRegOp zprty1, ZPRRegOp zprty2>
1036 : I<(outs zprty1:$Zd), (ins zprty2:$Zn),
1038 "", []>, Sched<[]> {
1041 let Inst{31-24} = 0b00000101;
1042 let Inst{23-22} = sz16_64;
1043 let Inst{21-18} = 0b1100;
1044 let Inst{17-16} = opc;
1045 let Inst{15-10} = 0b001110;
1050 multiclass sve_int_perm_unpk<bits<2> opc, string asm, SDPatternOperator op> {
1051 def _H : sve_int_perm_unpk<0b01, opc, asm, ZPR16, ZPR8>;
1052 def _S : sve_int_perm_unpk<0b10, opc, asm, ZPR32, ZPR16>;
1053 def _D : sve_int_perm_unpk<0b11, opc, asm, ZPR64, ZPR32>;
1055 def : SVE_1_Op_Pat<nxv8i16, op, nxv16i8, !cast<Instruction>(NAME # _H)>;
1056 def : SVE_1_Op_Pat<nxv4i32, op, nxv8i16, !cast<Instruction>(NAME # _S)>;
1057 def : SVE_1_Op_Pat<nxv2i64, op, nxv4i32, !cast<Instruction>(NAME # _D)>;
1060 class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty,
1061 RegisterClass srcRegType>
1062 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
1068 let Inst{31-24} = 0b00000101;
1069 let Inst{23-22} = sz8_64;
1070 let Inst{21-10} = 0b100100001110;
1072 let Inst{4-0} = Zdn;
1074 let Constraints = "$Zdn = $_Zdn";
1075 let DestructiveInstType = Destructive;
1078 multiclass sve_int_perm_insrs<string asm, SDPatternOperator op> {
1079 def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
1080 def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
1081 def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
1082 def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
1084 def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, i32, !cast<Instruction>(NAME # _B)>;
1085 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, i32, !cast<Instruction>(NAME # _H)>;
1086 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, i32, !cast<Instruction>(NAME # _S)>;
1087 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, i64, !cast<Instruction>(NAME # _D)>;
1090 class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
1091 RegisterClass srcRegType>
1092 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
1098 let Inst{31-24} = 0b00000101;
1099 let Inst{23-22} = sz8_64;
1100 let Inst{21-10} = 0b110100001110;
1102 let Inst{4-0} = Zdn;
1104 let Constraints = "$Zdn = $_Zdn";
1105 let DestructiveInstType = Destructive;
1108 multiclass sve_int_perm_insrv<string asm, SDPatternOperator op> {
1109 def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
1110 def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
1111 def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
1112 def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
1114 def : SVE_2_Op_Pat<nxv8f16, op, nxv8f16, f16, !cast<Instruction>(NAME # _H)>;
1115 def : SVE_2_Op_Pat<nxv4f32, op, nxv4f32, f32, !cast<Instruction>(NAME # _S)>;
1116 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, f64, !cast<Instruction>(NAME # _D)>;
1119 //===----------------------------------------------------------------------===//
1120 // SVE Permute - Extract Group
1121 //===----------------------------------------------------------------------===//
1123 class sve_int_perm_extract_i<string asm>
1124 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
1125 asm, "\t$Zdn, $_Zdn, $Zm, $imm8",
1126 "", []>, Sched<[]> {
1130 let Inst{31-21} = 0b00000101001;
1131 let Inst{20-16} = imm8{7-3};
1132 let Inst{15-13} = 0b000;
1133 let Inst{12-10} = imm8{2-0};
1135 let Inst{4-0} = Zdn;
1137 let Constraints = "$Zdn = $_Zdn";
1138 let DestructiveInstType = Destructive;
1139 let ElementSize = ElementSizeNone;
1142 multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op> {
1143 def NAME : sve_int_perm_extract_i<asm>;
1145 def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv16i8, i32, imm0_255,
1146 !cast<Instruction>(NAME)>;
1149 class sve2_int_perm_extract_i_cons<string asm>
1150 : I<(outs ZPR8:$Zd), (ins ZZ_b:$Zn, imm0_255:$imm8),
1151 asm, "\t$Zd, $Zn, $imm8",
1152 "", []>, Sched<[]> {
1156 let Inst{31-21} = 0b00000101011;
1157 let Inst{20-16} = imm8{7-3};
1158 let Inst{15-13} = 0b000;
1159 let Inst{12-10} = imm8{2-0};
1164 //===----------------------------------------------------------------------===//
1165 // SVE Vector Select Group
1166 //===----------------------------------------------------------------------===//
1168 class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty>
1169 : I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
1170 asm, "\t$Zd, $Pg, $Zn, $Zm",
1177 let Inst{31-24} = 0b00000101;
1178 let Inst{23-22} = sz8_64;
1180 let Inst{20-16} = Zm;
1181 let Inst{15-14} = 0b11;
1182 let Inst{13-10} = Pg;
1187 multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
1188 def _B : sve_int_sel_vvv<0b00, asm, ZPR8>;
1189 def _H : sve_int_sel_vvv<0b01, asm, ZPR16>;
1190 def _S : sve_int_sel_vvv<0b10, asm, ZPR32>;
1191 def _D : sve_int_sel_vvv<0b11, asm, ZPR64>;
1193 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
1194 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
1195 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
1196 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
1198 def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1199 def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1200 def : SVE_3_Op_Pat<nxv2f32, op, nxv2i1, nxv2f32, nxv2f32, !cast<Instruction>(NAME # _D)>;
1201 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
1203 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
1204 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;
1205 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
1206 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>;
1207 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
1208 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>;
1209 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
1210 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>;
1214 //===----------------------------------------------------------------------===//
1215 // SVE Predicate Logical Operations Group
1216 //===----------------------------------------------------------------------===//
1218 class sve_int_pred_log<bits<4> opc, string asm>
1219 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
1220 asm, "\t$Pd, $Pg/z, $Pn, $Pm",
1227 let Inst{31-24} = 0b00100101;
1228 let Inst{23-22} = opc{3-2};
1229 let Inst{21-20} = 0b00;
1230 let Inst{19-16} = Pm;
1231 let Inst{15-14} = 0b01;
1232 let Inst{13-10} = Pg;
1233 let Inst{9} = opc{1};
1235 let Inst{4} = opc{0};
1238 // SEL has no predication qualifier.
1239 let AsmString = !if(!eq(opc, 0b0011),
1240 !strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"),
1241 !strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm"));
1243 let Defs = !if(!eq (opc{2}, 1), [NZCV], []);
1247 multiclass sve_int_pred_log<bits<4> opc, string asm, SDPatternOperator op> {
1248 def NAME : sve_int_pred_log<opc, asm>;
1250 def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
1251 def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i1, nxv8i1, !cast<Instruction>(NAME)>;
1252 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i1, nxv4i1, !cast<Instruction>(NAME)>;
1253 def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2i1, nxv2i1, !cast<Instruction>(NAME)>;
1257 //===----------------------------------------------------------------------===//
1258 // SVE Logical Mask Immediate Group
1259 //===----------------------------------------------------------------------===//
1261 class sve_int_log_imm<bits<2> opc, string asm>
1262 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),
1263 asm, "\t$Zdn, $_Zdn, $imms13",
1264 "", []>, Sched<[]> {
1267 let Inst{31-24} = 0b00000101;
1268 let Inst{23-22} = opc;
1269 let Inst{21-18} = 0b0000;
1270 let Inst{17-5} = imms13;
1271 let Inst{4-0} = Zdn;
1273 let Constraints = "$Zdn = $_Zdn";
1274 let DecoderMethod = "DecodeSVELogicalImmInstruction";
1275 let DestructiveInstType = Destructive;
1276 let ElementSize = ElementSizeNone;
1279 multiclass sve_int_log_imm<bits<2> opc, string asm, string alias, SDPatternOperator op> {
1280 def NAME : sve_int_log_imm<opc, asm>;
1282 def : SVE_1_Op_Imm_Log_Pat<nxv16i8, op, ZPR8, i32, SVELogicalImm8Pat, !cast<Instruction>(NAME)>;
1283 def : SVE_1_Op_Imm_Log_Pat<nxv8i16, op, ZPR16, i32, SVELogicalImm16Pat, !cast<Instruction>(NAME)>;
1284 def : SVE_1_Op_Imm_Log_Pat<nxv4i32, op, ZPR32, i32, SVELogicalImm32Pat, !cast<Instruction>(NAME)>;
1285 def : SVE_1_Op_Imm_Log_Pat<nxv2i64, op, ZPR64, i64, SVELogicalImm64Pat, !cast<Instruction>(NAME)>;
1287 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1288 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
1289 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1290 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>;
1291 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1292 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>;
1294 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1295 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>;
1296 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1297 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>;
1298 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1299 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>;
1300 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1301 (!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>;
1304 class sve_int_dup_mask_imm<string asm>
1305 : I<(outs ZPR64:$Zd), (ins logical_imm64:$imms),
1306 asm, "\t$Zd, $imms",
1311 let Inst{31-18} = 0b00000101110000;
1312 let Inst{17-5} = imms;
1315 let isReMaterializable = 1;
1316 let DecoderMethod = "DecodeSVELogicalImmInstruction";
1319 multiclass sve_int_dup_mask_imm<string asm> {
1320 def NAME : sve_int_dup_mask_imm<asm>;
1322 def : InstAlias<"dupm $Zd, $imm",
1323 (!cast<Instruction>(NAME) ZPR8:$Zd, sve_logical_imm8:$imm), 4>;
1324 def : InstAlias<"dupm $Zd, $imm",
1325 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_logical_imm16:$imm), 3>;
1326 def : InstAlias<"dupm $Zd, $imm",
1327 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_logical_imm32:$imm), 2>;
1329 // All Zd.b forms have a CPY/DUP equivalent, hence no byte alias here.
1330 def : InstAlias<"mov $Zd, $imm",
1331 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_preferred_logical_imm16:$imm), 7>;
1332 def : InstAlias<"mov $Zd, $imm",
1333 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_preferred_logical_imm32:$imm), 6>;
1334 def : InstAlias<"mov $Zd, $imm",
1335 (!cast<Instruction>(NAME) ZPR64:$Zd, sve_preferred_logical_imm64:$imm), 5>;
1338 //===----------------------------------------------------------------------===//
1339 // SVE Integer Arithmetic - Unpredicated Group.
1340 //===----------------------------------------------------------------------===//
1342 class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
1344 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
1345 asm, "\t$Zd, $Zn, $Zm",
1346 "", []>, Sched<[]> {
1350 let Inst{31-24} = 0b00000100;
1351 let Inst{23-22} = sz8_64;
1353 let Inst{20-16} = Zm;
1354 let Inst{15-13} = 0b000;
1355 let Inst{12-10} = opc;
1360 multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm, SDPatternOperator op> {
1361 def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
1362 def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
1363 def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
1364 def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
1366 def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
1367 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
1368 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
1369 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
1372 //===----------------------------------------------------------------------===//
1373 // SVE Floating Point Arithmetic - Predicated Group
1374 //===----------------------------------------------------------------------===//
1376 class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm,
1379 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
1380 asm, "\t$Zdn, $Pg/m, $_Zdn, $i1",
1386 let Inst{31-24} = 0b01100101;
1387 let Inst{23-22} = sz;
1388 let Inst{21-19} = 0b011;
1389 let Inst{18-16} = opc;
1390 let Inst{15-13} = 0b100;
1391 let Inst{12-10} = Pg;
1392 let Inst{9-6} = 0b0000;
1394 let Inst{4-0} = Zdn;
1396 let Constraints = "$Zdn = $_Zdn";
1397 let DestructiveInstType = Destructive;
1398 let ElementSize = zprty.ElementSize;
1401 multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
1402 def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
1403 def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
1404 def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
1407 class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
1409 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
1410 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
1416 let Inst{31-24} = 0b01100101;
1417 let Inst{23-22} = sz;
1418 let Inst{21-20} = 0b00;
1419 let Inst{19-16} = opc;
1420 let Inst{15-13} = 0b100;
1421 let Inst{12-10} = Pg;
1423 let Inst{4-0} = Zdn;
1425 let Constraints = "$Zdn = $_Zdn";
1426 let DestructiveInstType = Destructive;
1427 let ElementSize = zprty.ElementSize;
1430 multiclass sve_fp_2op_p_zds<bits<4> opc, string asm,
1431 SDPatternOperator op> {
1432 def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
1433 def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
1434 def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
1436 def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1437 def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1438 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
1441 multiclass sve_fp_2op_p_zds_fscale<bits<4> opc, string asm,
1442 SDPatternOperator op> {
1443 def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
1444 def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
1445 def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
1447 def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>;
1448 def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>;
1449 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
1452 class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty>
1453 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm32_0_7:$imm3),
1454 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
1460 let Inst{31-24} = 0b01100101;
1461 let Inst{23-22} = sz;
1462 let Inst{21-19} = 0b010;
1463 let Inst{18-16} = imm3;
1464 let Inst{15-10} = 0b100000;
1466 let Inst{4-0} = Zdn;
1468 let Constraints = "$Zdn = $_Zdn";
1469 let DestructiveInstType = Destructive;
1470 let ElementSize = ElementSizeNone;
1473 multiclass sve_fp_ftmad<string asm, SDPatternOperator op> {
1474 def _H : sve_fp_ftmad<0b01, asm, ZPR16>;
1475 def _S : sve_fp_ftmad<0b10, asm, ZPR32>;
1476 def _D : sve_fp_ftmad<0b11, asm, ZPR64>;
1478 def : Pat<(nxv8f16 (op (nxv8f16 ZPR16:$Zn), (nxv8f16 ZPR16:$Zm), (i32 imm32_0_7:$imm))),
1479 (!cast<Instruction>(NAME # _H) ZPR16:$Zn, ZPR16:$Zm, imm32_0_7:$imm)>;
1480 def : Pat<(nxv4f32 (op (nxv4f32 ZPR32:$Zn), (nxv4f32 ZPR32:$Zm), (i32 imm32_0_7:$imm))),
1481 (!cast<Instruction>(NAME # _S) ZPR32:$Zn, ZPR32:$Zm, imm32_0_7:$imm)>;
1482 def : Pat<(nxv2f64 (op (nxv2f64 ZPR64:$Zn), (nxv2f64 ZPR64:$Zm), (i32 imm32_0_7:$imm))),
1483 (!cast<Instruction>(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, imm32_0_7:$imm)>;
1487 //===----------------------------------------------------------------------===//
1488 // SVE Floating Point Arithmetic - Unpredicated Group
1489 //===----------------------------------------------------------------------===//
1491 class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty>
1492 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
1493 asm, "\t$Zd, $Zn, $Zm",
1499 let Inst{31-24} = 0b01100101;
1500 let Inst{23-22} = sz;
1502 let Inst{20-16} = Zm;
1503 let Inst{15-13} = 0b000;
1504 let Inst{12-10} = opc;
1509 multiclass sve_fp_3op_u_zd<bits<3> opc, string asm, SDPatternOperator op> {
1510 def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>;
1511 def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>;
1512 def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>;
1514 def : SVE_2_Op_Pat<nxv8f16, op, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1515 def : SVE_2_Op_Pat<nxv4f32, op, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1516 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
1520 multiclass sve_fp_3op_u_zd_ftsmul<bits<3> opc, string asm, SDPatternOperator op> {
1521 def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>;
1522 def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>;
1523 def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>;
1525 def : SVE_2_Op_Pat<nxv8f16, op, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>;
1526 def : SVE_2_Op_Pat<nxv4f32, op, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>;
1527 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
1530 //===----------------------------------------------------------------------===//
1531 // SVE Floating Point Fused Multiply-Add Group
1532 //===----------------------------------------------------------------------===//
1534 class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty>
1535 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
1536 asm, "\t$Zda, $Pg/m, $Zn, $Zm",
1543 let Inst{31-24} = 0b01100101;
1544 let Inst{23-22} = sz;
1546 let Inst{20-16} = Zm;
1548 let Inst{14-13} = opc;
1549 let Inst{12-10} = Pg;
1551 let Inst{4-0} = Zda;
1553 let Constraints = "$Zda = $_Zda";
1554 let DestructiveInstType = Destructive;
1555 let ElementSize = zprty.ElementSize;
1558 multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm, SDPatternOperator op> {
1559 def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>;
1560 def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>;
1561 def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>;
1563 def : SVE_4_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1564 def : SVE_4_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1565 def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
1568 class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm,
1570 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
1571 asm, "\t$Zdn, $Pg/m, $Zm, $Za",
1578 let Inst{31-24} = 0b01100101;
1579 let Inst{23-22} = sz;
1581 let Inst{20-16} = Za;
1583 let Inst{14-13} = opc;
1584 let Inst{12-10} = Pg;
1586 let Inst{4-0} = Zdn;
1588 let Constraints = "$Zdn = $_Zdn";
1589 let DestructiveInstType = Destructive;
1590 let ElementSize = zprty.ElementSize;
1593 multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm, SDPatternOperator op> {
1594 def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>;
1595 def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>;
1596 def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>;
1598 def : SVE_4_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1599 def : SVE_4_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1600 def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
1603 //===----------------------------------------------------------------------===//
1604 // SVE Floating Point Multiply-Add - Indexed Group
1605 //===----------------------------------------------------------------------===//
1607 class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm,
1609 ZPRRegOp zprty2, Operand itype>
1610 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop),
1611 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
1614 let Inst{31-24} = 0b01100100;
1615 let Inst{23-22} = sz;
1617 let Inst{15-11} = 0;
1620 let Inst{4-0} = Zda;
1622 let Constraints = "$Zda = $_Zda";
1623 let DestructiveInstType = Destructive;
1624 let ElementSize = ElementSizeNone;
1627 multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm,
1628 SDPatternOperator op> {
1629 def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
1632 let Inst{22} = iop{2};
1633 let Inst{20-19} = iop{1-0};
1634 let Inst{18-16} = Zm;
1636 def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS32b> {
1639 let Inst{20-19} = iop;
1640 let Inst{18-16} = Zm;
1642 def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD32b> {
1646 let Inst{19-16} = Zm;
1649 def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexH32b:$idx))),
1650 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, VectorIndexH32b:$idx)>;
1651 def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexS32b:$idx))),
1652 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b:$idx)>;
1653 def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 VectorIndexD32b:$idx))),
1654 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b:$idx)>;
1658 //===----------------------------------------------------------------------===//
1659 // SVE Floating Point Multiply - Indexed Group
1660 //===----------------------------------------------------------------------===//
1662 class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty,
1663 ZPRRegOp zprty2, Operand itype>
1664 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop),
1665 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
1668 let Inst{31-24} = 0b01100100;
1669 let Inst{23-22} = sz;
1671 let Inst{15-10} = 0b001000;
1676 multiclass sve_fp_fmul_by_indexed_elem<string asm, SDPatternOperator op> {
1677 def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
1680 let Inst{22} = iop{2};
1681 let Inst{20-19} = iop{1-0};
1682 let Inst{18-16} = Zm;
1684 def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS32b> {
1687 let Inst{20-19} = iop;
1688 let Inst{18-16} = Zm;
1690 def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD32b> {
1694 let Inst{19-16} = Zm;
1697 def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, (i32 VectorIndexH32b:$idx))),
1698 (!cast<Instruction>(NAME # _H) $Op1, $Op2, VectorIndexH32b:$idx)>;
1699 def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, (i32 VectorIndexS32b:$idx))),
1700 (!cast<Instruction>(NAME # _S) $Op1, $Op2, VectorIndexS32b:$idx)>;
1701 def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b:$idx))),
1702 (!cast<Instruction>(NAME # _D) $Op1, $Op2, VectorIndexD32b:$idx)>;
1705 //===----------------------------------------------------------------------===//
1706 // SVE Floating Point Complex Multiply-Add Group
1707 //===----------------------------------------------------------------------===//
1709 class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty>
1710 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
1711 complexrotateop:$imm),
1712 asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
1713 "", []>, Sched<[]> {
1719 let Inst{31-24} = 0b01100100;
1720 let Inst{23-22} = sz;
1722 let Inst{20-16} = Zm;
1724 let Inst{14-13} = imm;
1725 let Inst{12-10} = Pg;
1727 let Inst{4-0} = Zda;
1729 let Constraints = "$Zda = $_Zda";
1730 let DestructiveInstType = Destructive;
1731 let ElementSize = zprty.ElementSize;
1734 multiclass sve_fp_fcmla<string asm, SDPatternOperator op> {
1735 def _H : sve_fp_fcmla<0b01, asm, ZPR16>;
1736 def _S : sve_fp_fcmla<0b10, asm, ZPR32>;
1737 def _D : sve_fp_fcmla<0b11, asm, ZPR64>;
1739 def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop:$imm))),
1740 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1741 def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop:$imm))),
1742 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1743 def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop:$imm))),
1744 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1747 //===----------------------------------------------------------------------===//
1748 // SVE Floating Point Complex Multiply-Add - Indexed Group
1749 //===----------------------------------------------------------------------===//
1751 class sve_fp_fcmla_by_indexed_elem<bits<2> sz, string asm,
1753 ZPRRegOp zprty2, Operand itype>
1754 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop,
1755 complexrotateop:$imm),
1756 asm, "\t$Zda, $Zn, $Zm$iop, $imm",
1757 "", []>, Sched<[]> {
1761 let Inst{31-24} = 0b01100100;
1762 let Inst{23-22} = sz;
1764 let Inst{15-12} = 0b0001;
1765 let Inst{11-10} = imm;
1767 let Inst{4-0} = Zda;
1769 let Constraints = "$Zda = $_Zda";
1770 let DestructiveInstType = Destructive;
1771 let ElementSize = ElementSizeNone;
1774 multiclass sve_fp_fcmla_by_indexed_elem<string asm, SDPatternOperator op> {
1775 def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS32b> {
1778 let Inst{20-19} = iop;
1779 let Inst{18-16} = Zm;
1781 def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD32b> {
1785 let Inst{19-16} = Zm;
1788 def : Pat<(nxv8f16 (op nxv8f16:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 VectorIndexS32b:$idx), (i32 complexrotateop:$imm))),
1789 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, VectorIndexS32b:$idx, complexrotateop:$imm)>;
1790 def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b:$idx), (i32 complexrotateop:$imm))),
1791 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b:$idx, complexrotateop:$imm)>;
1794 //===----------------------------------------------------------------------===//
1795 // SVE Floating Point Complex Addition Group
1796 //===----------------------------------------------------------------------===//
1798 class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty>
1799 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
1800 complexrotateopodd:$imm),
1801 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
1808 let Inst{31-24} = 0b01100100;
1809 let Inst{23-22} = sz;
1810 let Inst{21-17} = 0;
1812 let Inst{15-13} = 0b100;
1813 let Inst{12-10} = Pg;
1815 let Inst{4-0} = Zdn;
1817 let Constraints = "$Zdn = $_Zdn";
1818 let DestructiveInstType = Destructive;
1819 let ElementSize = zprty.ElementSize;
1822 multiclass sve_fp_fcadd<string asm, SDPatternOperator op> {
1823 def _H : sve_fp_fcadd<0b01, asm, ZPR16>;
1824 def _S : sve_fp_fcadd<0b10, asm, ZPR32>;
1825 def _D : sve_fp_fcadd<0b11, asm, ZPR64>;
1827 def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, (i32 complexrotateopodd:$imm))),
1828 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, complexrotateopodd:$imm)>;
1829 def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 complexrotateopodd:$imm))),
1830 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, complexrotateopodd:$imm)>;
1831 def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, (i32 complexrotateopodd:$imm))),
1832 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, complexrotateopodd:$imm)>;
1835 //===----------------------------------------------------------------------===//
1836 // SVE2 Floating Point Convert Group
1837 //===----------------------------------------------------------------------===//
1839 class sve2_fp_convert_precision<bits<4> opc, string asm,
1840 ZPRRegOp zprty1, ZPRRegOp zprty2>
1841 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
1842 asm, "\t$Zd, $Pg/m, $Zn",
1848 let Inst{31-24} = 0b01100100;
1849 let Inst{23-22} = opc{3-2};
1850 let Inst{21-18} = 0b0010;
1851 let Inst{17-16} = opc{1-0};
1852 let Inst{15-13} = 0b101;
1853 let Inst{12-10} = Pg;
1857 let Constraints = "$Zd = $_Zd";
1860 multiclass sve2_fp_convert_down_narrow<string asm, string op> {
1861 def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>;
1862 def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>;
1864 def : SVE_3_Op_Pat<nxv8f16, !cast<SDPatternOperator>(op # _f16f32), nxv8f16, nxv16i1, nxv4f32, !cast<Instruction>(NAME # _StoH)>;
1865 def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv16i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
1868 multiclass sve2_fp_convert_up_long<string asm, string op> {
1869 def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>;
1870 def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>;
1872 def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f16), nxv4f32, nxv16i1, nxv8f16, !cast<Instruction>(NAME # _HtoS)>;
1873 def : SVE_3_Op_Pat<nxv2f64, !cast<SDPatternOperator>(op # _f64f32), nxv2f64, nxv16i1, nxv4f32, !cast<Instruction>(NAME # _StoD)>;
1876 multiclass sve2_fp_convert_down_odd_rounding_top<string asm, string op> {
1877 def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>;
1879 def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv16i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
1882 //===----------------------------------------------------------------------===//
1883 // SVE2 Floating Point Pairwise Group
1884 //===----------------------------------------------------------------------===//
1886 class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
1888 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
1889 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
1895 let Inst{31-24} = 0b01100100;
1896 let Inst{23-22} = sz;
1897 let Inst{21-19} = 0b010;
1898 let Inst{18-16} = opc;
1899 let Inst{15-13} = 0b100;
1900 let Inst{12-10} = Pg;
1902 let Inst{4-0} = Zdn;
1904 let Constraints = "$Zdn = $_Zdn";
1905 let DestructiveInstType = Destructive;
1906 let ElementSize = zprty.ElementSize;
1909 multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm, SDPatternOperator op> {
1910 def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>;
1911 def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>;
1912 def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
1914 def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1915 def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1916 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
1919 //===----------------------------------------------------------------------===//
1920 // SVE2 Floating Point Widening Multiply-Add - Indexed Group
1921 //===----------------------------------------------------------------------===//
1923 class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
1924 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
1925 VectorIndexH32b:$iop),
1926 asm, "\t$Zda, $Zn, $Zm$iop",
1933 let Inst{31-21} = 0b01100100101;
1934 let Inst{20-19} = iop{2-1};
1935 let Inst{18-16} = Zm;
1936 let Inst{15-14} = 0b01;
1937 let Inst{13} = opc{1};
1939 let Inst{11} = iop{0};
1940 let Inst{10} = opc{0};
1942 let Inst{4-0} = Zda;
1944 let Constraints = "$Zda = $_Zda";
1945 let DestructiveInstType = Destructive;
1946 let ElementSize = ElementSizeNone;
1949 multiclass sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm,
1950 SDPatternOperator op> {
1951 def NAME : sve2_fp_mla_long_by_indexed_elem<opc, asm>;
1952 def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, nxv8f16, nxv8f16, i32, VectorIndexH32b, !cast<Instruction>(NAME)>;
1955 //===----------------------------------------------------------------------===//
1956 // SVE2 Floating Point Widening Multiply-Add Group
1957 //===----------------------------------------------------------------------===//
1959 class sve2_fp_mla_long<bits<2> opc, string asm>
1960 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
1961 asm, "\t$Zda, $Zn, $Zm",
1967 let Inst{31-21} = 0b01100100101;
1968 let Inst{20-16} = Zm;
1969 let Inst{15-14} = 0b10;
1970 let Inst{13} = opc{1};
1971 let Inst{12-11} = 0b00;
1972 let Inst{10} = opc{0};
1974 let Inst{4-0} = Zda;
1976 let Constraints = "$Zda = $_Zda";
1977 let DestructiveInstType = Destructive;
1978 let ElementSize = ElementSizeNone;
1981 multiclass sve2_fp_mla_long<bits<2> opc, string asm, SDPatternOperator op> {
1982 def NAME : sve2_fp_mla_long<opc, asm>;
1983 def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv8f16, nxv8f16, !cast<Instruction>(NAME)>;
1986 //===----------------------------------------------------------------------===//
1987 // SVE Stack Allocation Group
1988 //===----------------------------------------------------------------------===//
1990 class sve_int_arith_vl<bit opc, string asm>
1991 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
1992 asm, "\t$Rd, $Rn, $imm6",
1998 let Inst{31-23} = 0b000001000;
2001 let Inst{20-16} = Rn;
2002 let Inst{15-11} = 0b01010;
2003 let Inst{10-5} = imm6;
2007 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
2008 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
2009 asm, "\t$Rd, $imm6",
2014 let Inst{31-23} = 0b000001001;
2017 let Inst{20-16} = opc2{4-0};
2018 let Inst{15-11} = 0b01010;
2019 let Inst{10-5} = imm6;
2023 //===----------------------------------------------------------------------===//
2024 // SVE Permute - In Lane Group
2025 //===----------------------------------------------------------------------===//
2027 class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm,
2029 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
2030 asm, "\t$Zd, $Zn, $Zm",
2036 let Inst{31-24} = 0b00000101;
2037 let Inst{23-22} = sz8_64;
2039 let Inst{20-16} = Zm;
2040 let Inst{15-13} = 0b011;
2041 let Inst{12-10} = opc;
2046 multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm,
2047 SDPatternOperator op> {
2048 def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>;
2049 def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>;
2050 def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>;
2051 def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
2053 def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2054 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2055 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2056 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2058 def : SVE_2_Op_Pat<nxv8f16, op, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
2059 def : SVE_2_Op_Pat<nxv4f16, op, nxv4f16, nxv4f16, !cast<Instruction>(NAME # _S)>;
2060 def : SVE_2_Op_Pat<nxv4f32, op, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
2061 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
2064 //===----------------------------------------------------------------------===//
2065 // SVE Floating Point Unary Operations Group
2066 //===----------------------------------------------------------------------===//
2068 class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
2069 RegisterOperand o_zprtype, ElementSizeEnum size>
2070 : I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
2071 asm, "\t$Zd, $Pg/m, $Zn",
2077 let Inst{31-24} = 0b01100101;
2078 let Inst{23-22} = opc{6-5};
2080 let Inst{20-16} = opc{4-0};
2081 let Inst{15-13} = 0b101;
2082 let Inst{12-10} = Pg;
2086 let Constraints = "$Zd = $_Zd";
2087 let DestructiveInstType = Destructive;
2088 let ElementSize = size;
2091 multiclass sve_fp_2op_p_zd<bits<7> opc, string asm,
2092 RegisterOperand i_zprtype,
2093 RegisterOperand o_zprtype,
2094 SDPatternOperator op, ValueType vt1,
2095 ValueType vt2, ValueType vt3, ElementSizeEnum Sz> {
2096 def NAME : sve_fp_2op_p_zd<opc, asm, i_zprtype, o_zprtype, Sz>;
2098 def : SVE_3_Op_Pat<vt1, op, vt1, vt2, vt3, !cast<Instruction>(NAME)>;
2101 multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm, SDPatternOperator op> {
2102 def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>;
2103 def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>;
2104 def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>;
2106 def : SVE_3_Op_Pat<nxv8f16, op, nxv8f16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
2107 def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
2108 def : SVE_3_Op_Pat<nxv2f64, op, nxv2f64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
2111 multiclass sve2_fp_flogb<string asm, SDPatternOperator op> {
2112 def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>;
2113 def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>;
2114 def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>;
2116 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
2117 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
2118 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
2121 multiclass sve2_fp_convert_down_odd_rounding<string asm, string op> {
2122 def _DtoS : sve_fp_2op_p_zd<0b0001010, asm, ZPR64, ZPR32, ElementSizeD>;
2123 def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv16i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
2126 //===----------------------------------------------------------------------===//
2127 // SVE Floating Point Unary Operations - Unpredicated Group
2128 //===----------------------------------------------------------------------===//
2130 class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm,
2132 : I<(outs zprty:$Zd), (ins zprty:$Zn),
2138 let Inst{31-24} = 0b01100101;
2139 let Inst{23-22} = sz;
2140 let Inst{21-19} = 0b001;
2141 let Inst{18-16} = opc;
2142 let Inst{15-10} = 0b001100;
2147 multiclass sve_fp_2op_u_zd<bits<3> opc, string asm, SDPatternOperator op> {
2148 def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>;
2149 def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>;
2150 def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>;
2152 def : SVE_1_Op_Pat<nxv8f16, op, nxv8f16, !cast<Instruction>(NAME # _H)>;
2153 def : SVE_1_Op_Pat<nxv4f32, op, nxv4f32, !cast<Instruction>(NAME # _S)>;
2154 def : SVE_1_Op_Pat<nxv2f64, op, nxv2f64, !cast<Instruction>(NAME # _D)>;
2157 //===----------------------------------------------------------------------===//
2158 // SVE Integer Arithmetic - Binary Predicated Group
2159 //===----------------------------------------------------------------------===//
2161 class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
2162 string asm, ZPRRegOp zprty>
2163 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
2164 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
2168 let Inst{31-24} = 0b00000100;
2169 let Inst{23-22} = sz8_64;
2171 let Inst{20-19} = fmt;
2172 let Inst{18-16} = opc;
2173 let Inst{15-13} = 0b000;
2174 let Inst{12-10} = Pg;
2176 let Inst{4-0} = Zdn;
2178 let Constraints = "$Zdn = $_Zdn";
2179 let DestructiveInstType = Destructive;
2180 let ElementSize = zprty.ElementSize;
2183 multiclass sve_int_bin_pred_log<bits<3> opc, string asm, SDPatternOperator op> {
2184 def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>;
2185 def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>;
2186 def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>;
2187 def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>;
2189 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2190 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2191 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2192 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2195 multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm, SDPatternOperator op> {
2196 def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
2197 def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
2198 def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
2199 def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
2201 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2202 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2203 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2204 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2207 multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm, SDPatternOperator op> {
2208 def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>;
2209 def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>;
2210 def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>;
2211 def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>;
2213 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2214 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2215 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2216 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2219 multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm, SDPatternOperator op> {
2220 def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>;
2221 def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>;
2222 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
2223 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
2225 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2226 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2227 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2228 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2231 // Special case for divides which are not defined for 8b/16b elements.
2232 multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm, SDPatternOperator op> {
2233 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
2234 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
2236 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2237 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2240 //===----------------------------------------------------------------------===//
2241 // SVE Integer Multiply-Add Group
2242 //===----------------------------------------------------------------------===//
2244 class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
2246 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
2247 asm, "\t$Zdn, $Pg/m, $Zm, $Za",
2254 let Inst{31-24} = 0b00000100;
2255 let Inst{23-22} = sz8_64;
2257 let Inst{20-16} = Zm;
2258 let Inst{15-14} = 0b11;
2260 let Inst{12-10} = Pg;
2262 let Inst{4-0} = Zdn;
2264 let Constraints = "$Zdn = $_Zdn";
2265 let DestructiveInstType = Destructive;
2266 let ElementSize = zprty.ElementSize;
2269 multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm, SDPatternOperator op> {
2270 def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>;
2271 def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>;
2272 def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>;
2273 def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>;
2275 def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2276 def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2277 def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2278 def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2281 class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
2283 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
2284 asm, "\t$Zda, $Pg/m, $Zn, $Zm",
2291 let Inst{31-24} = 0b00000100;
2292 let Inst{23-22} = sz8_64;
2294 let Inst{20-16} = Zm;
2295 let Inst{15-14} = 0b01;
2297 let Inst{12-10} = Pg;
2299 let Inst{4-0} = Zda;
2301 let Constraints = "$Zda = $_Zda";
2302 let DestructiveInstType = Destructive;
2303 let ElementSize = zprty.ElementSize;
2306 multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm, SDPatternOperator op> {
2307 def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>;
2308 def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>;
2309 def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>;
2310 def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>;
2312 def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
2313 def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
2314 def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
2315 def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
2318 //===----------------------------------------------------------------------===//
2319 // SVE2 Integer Multiply-Add - Unpredicated Group
2320 //===----------------------------------------------------------------------===//
2322 class sve2_int_mla<bits<2> sz, bits<5> opc, string asm,
2323 ZPRRegOp zprty1, ZPRRegOp zprty2>
2324 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
2325 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
2329 let Inst{31-24} = 0b01000100;
2330 let Inst{23-22} = sz;
2332 let Inst{20-16} = Zm;
2334 let Inst{14-10} = opc;
2336 let Inst{4-0} = Zda;
2338 let Constraints = "$Zda = $_Zda";
2339 let DestructiveInstType = Destructive;
2340 let ElementSize = ElementSizeNone;
2343 multiclass sve2_int_mla<bit S, string asm> {
2344 def _B : sve2_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>;
2345 def _H : sve2_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>;
2346 def _S : sve2_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>;
2347 def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>;
2350 multiclass sve2_int_mla_long<bits<5> opc, string asm> {
2351 def _H : sve2_int_mla<0b01, opc, asm, ZPR16, ZPR8>;
2352 def _S : sve2_int_mla<0b10, opc, asm, ZPR32, ZPR16>;
2353 def _D : sve2_int_mla<0b11, opc, asm, ZPR64, ZPR32>;
2356 //===----------------------------------------------------------------------===//
2357 // SVE2 Integer Multiply-Add - Indexed Group
2358 //===----------------------------------------------------------------------===//
2360 class sve2_int_mla_by_indexed_elem<bits<2> sz, bits<6> opc, string asm,
2361 ZPRRegOp zprty1, ZPRRegOp zprty2,
2362 ZPRRegOp zprty3, Operand itype>
2363 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
2364 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
2367 let Inst{31-24} = 0b01000100;
2368 let Inst{23-22} = sz;
2370 let Inst{15-10} = opc;
2372 let Inst{4-0} = Zda;
2374 let Constraints = "$Zda = $_Zda";
2375 let DestructiveInstType = Destructive;
2376 let ElementSize = ElementSizeNone;
2379 multiclass sve2_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm> {
2380 def _H : sve2_int_mla_by_indexed_elem<{0, ?}, { 0b000, opc, S }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> {
2383 let Inst{22} = iop{2};
2384 let Inst{20-19} = iop{1-0};
2385 let Inst{18-16} = Zm;
2387 def _S : sve2_int_mla_by_indexed_elem<0b10, { 0b000, opc, S }, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> {
2390 let Inst{20-19} = iop;
2391 let Inst{18-16} = Zm;
2393 def _D : sve2_int_mla_by_indexed_elem<0b11, { 0b000, opc, S }, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> {
2397 let Inst{19-16} = Zm;
2401 //===----------------------------------------------------------------------===//
2402 // SVE2 Integer Multiply-Add Long - Indexed Group
2403 //===----------------------------------------------------------------------===//
2405 multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm> {
2406 def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
2407 asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
2410 let Inst{20-19} = iop{2-1};
2411 let Inst{18-16} = Zm;
2412 let Inst{11} = iop{0};
2414 def _D : sve2_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
2415 asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
2418 let Inst{20} = iop{1};
2419 let Inst{19-16} = Zm;
2420 let Inst{11} = iop{0};
2424 //===----------------------------------------------------------------------===//
2425 // SVE Integer Dot Product Group
2426 //===----------------------------------------------------------------------===//
2428 class sve_intx_dot<bit sz, bit U, string asm, ZPRRegOp zprty1,
2430 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm,
2431 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
2435 let Inst{31-23} = 0b010001001;
2438 let Inst{20-16} = Zm;
2439 let Inst{15-11} = 0;
2442 let Inst{4-0} = Zda;
2444 let Constraints = "$Zda = $_Zda";
2445 let DestructiveInstType = Destructive;
2448 multiclass sve_intx_dot<bit opc, string asm, SDPatternOperator op> {
2449 def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>;
2450 def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>;
2452 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _S)>;
2453 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _D)>;
2456 //===----------------------------------------------------------------------===//
2457 // SVE Integer Dot Product Group - Indexed Group
2458 //===----------------------------------------------------------------------===//
2460 class sve_intx_dot_by_indexed_elem<bit sz, bit U, string asm,
2461 ZPRRegOp zprty1, ZPRRegOp zprty2,
2462 ZPRRegOp zprty3, Operand itype>
2463 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
2464 asm, "\t$Zda, $Zn, $Zm$iop",
2465 "", []>, Sched<[]> {
2468 let Inst{31-23} = 0b010001001;
2471 let Inst{15-11} = 0;
2474 let Inst{4-0} = Zda;
2476 let Constraints = "$Zda = $_Zda";
2477 let DestructiveInstType = Destructive;
2480 multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm,
2481 SDPatternOperator op> {
2482 def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b> {
2485 let Inst{20-19} = iop;
2486 let Inst{18-16} = Zm;
2488 def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b> {
2492 let Inst{19-16} = Zm;
2495 def : Pat<(nxv4i32 (op nxv4i32:$Op1, nxv16i8:$Op2, nxv16i8:$Op3, (i32 VectorIndexS32b:$idx))),
2496 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b:$idx)>;
2497 def : Pat<(nxv2i64 (op nxv2i64:$Op1, nxv8i16:$Op2, nxv8i16:$Op3, (i32 VectorIndexD32b:$idx))),
2498 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b:$idx)>;
2501 //===----------------------------------------------------------------------===//
2502 // SVE2 Complex Integer Dot Product Group
2503 //===----------------------------------------------------------------------===//
2505 class sve2_complex_int_arith<bits<2> sz, bits<4> opc, string asm,
2506 ZPRRegOp zprty1, ZPRRegOp zprty2>
2507 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm,
2508 complexrotateop:$rot),
2509 asm, "\t$Zda, $Zn, $Zm, $rot", "", []>, Sched<[]> {
2514 let Inst{31-24} = 0b01000100;
2515 let Inst{23-22} = sz;
2517 let Inst{20-16} = Zm;
2518 let Inst{15-12} = opc;
2519 let Inst{11-10} = rot;
2521 let Inst{4-0} = Zda;
2523 let Constraints = "$Zda = $_Zda";
2524 let DestructiveInstType = Destructive;
2525 let ElementSize = ElementSizeNone;
2528 multiclass sve2_cintx_dot<string asm> {
2529 def _S : sve2_complex_int_arith<0b10, 0b0001, asm, ZPR32, ZPR8>;
2530 def _D : sve2_complex_int_arith<0b11, 0b0001, asm, ZPR64, ZPR16>;
2533 //===----------------------------------------------------------------------===//
2534 // SVE2 Complex Multiply-Add Group
2535 //===----------------------------------------------------------------------===//
2537 multiclass sve2_int_cmla<bit opc, string asm> {
2538 def _B : sve2_complex_int_arith<0b00, { 0b001, opc }, asm, ZPR8, ZPR8>;
2539 def _H : sve2_complex_int_arith<0b01, { 0b001, opc }, asm, ZPR16, ZPR16>;
2540 def _S : sve2_complex_int_arith<0b10, { 0b001, opc }, asm, ZPR32, ZPR32>;
2541 def _D : sve2_complex_int_arith<0b11, { 0b001, opc }, asm, ZPR64, ZPR64>;
2544 //===----------------------------------------------------------------------===//
2545 // SVE2 Complex Integer Dot Product - Indexed Group
2546 //===----------------------------------------------------------------------===//
2548 class sve2_complex_int_arith_indexed<bits<2> sz, bits<4> opc, string asm,
2549 ZPRRegOp zprty1, ZPRRegOp zprty2,
2550 ZPRRegOp zprty3, Operand itype>
2551 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop,
2552 complexrotateop:$rot),
2553 asm, "\t$Zda, $Zn, $Zm$iop, $rot", "", []>, Sched<[]> {
2557 let Inst{31-24} = 0b01000100;
2558 let Inst{23-22} = sz;
2560 let Inst{15-12} = opc;
2561 let Inst{11-10} = rot;
2563 let Inst{4-0} = Zda;
2565 let Constraints = "$Zda = $_Zda";
2566 let DestructiveInstType = Destructive;
2567 let ElementSize = ElementSizeNone;
2570 multiclass sve2_cintx_dot_by_indexed_elem<string asm> {
2571 def _S : sve2_complex_int_arith_indexed<0b10, 0b0100, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> {
2574 let Inst{20-19} = iop;
2575 let Inst{18-16} = Zm;
2577 def _D : sve2_complex_int_arith_indexed<0b11, 0b0100, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> {
2581 let Inst{19-16} = Zm;
2585 //===----------------------------------------------------------------------===//
2586 // SVE2 Complex Multiply-Add - Indexed Group
2587 //===----------------------------------------------------------------------===//
2589 multiclass sve2_cmla_by_indexed_elem<bit opc, string asm> {
2590 def _H : sve2_complex_int_arith_indexed<0b10, { 0b011, opc }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexS> {
2593 let Inst{20-19} = iop;
2594 let Inst{18-16} = Zm;
2596 def _S : sve2_complex_int_arith_indexed<0b11, { 0b011, opc }, asm, ZPR32, ZPR32, ZPR4b32, VectorIndexD> {
2600 let Inst{19-16} = Zm;
2604 //===----------------------------------------------------------------------===//
2605 // SVE2 Integer Multiply - Unpredicated Group
2606 //===----------------------------------------------------------------------===//
2608 class sve2_int_mul<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty>
2609 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
2610 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2614 let Inst{31-24} = 0b00000100;
2615 let Inst{23-22} = sz;
2617 let Inst{20-16} = Zm;
2618 let Inst{15-13} = 0b011;
2619 let Inst{12-10} = opc;
2624 multiclass sve2_int_mul<bits<3> opc, string asm> {
2625 def _B : sve2_int_mul<0b00, opc, asm, ZPR8>;
2626 def _H : sve2_int_mul<0b01, opc, asm, ZPR16>;
2627 def _S : sve2_int_mul<0b10, opc, asm, ZPR32>;
2628 def _D : sve2_int_mul<0b11, opc, asm, ZPR64>;
2631 //===----------------------------------------------------------------------===//
2632 // SVE2 Integer Multiply - Indexed Group
2633 //===----------------------------------------------------------------------===//
2635 class sve2_int_mul_by_indexed_elem<bits<2> sz, bits<4> opc, string asm,
2636 ZPRRegOp zprty1, ZPRRegOp zprty2,
2637 ZPRRegOp zprty3, Operand itype>
2638 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop),
2639 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
2642 let Inst{31-24} = 0b01000100;
2643 let Inst{23-22} = sz;
2645 let Inst{15-14} = 0b11;
2646 let Inst{13-10} = opc;
2651 multiclass sve2_int_mul_by_indexed_elem<bits<4> opc, string asm> {
2652 def _H : sve2_int_mul_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> {
2655 let Inst{22} = iop{2};
2656 let Inst{20-19} = iop{1-0};
2657 let Inst{18-16} = Zm;
2659 def _S : sve2_int_mul_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> {
2662 let Inst{20-19} = iop;
2663 let Inst{18-16} = Zm;
2665 def _D : sve2_int_mul_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> {
2669 let Inst{19-16} = Zm;
2673 multiclass sve2_int_mul_long_by_indexed_elem<bits<3> opc, string asm> {
2674 def _S : sve2_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm,
2675 ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
2678 let Inst{20-19} = iop{2-1};
2679 let Inst{18-16} = Zm;
2680 let Inst{11} = iop{0};
2682 def _D : sve2_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm,
2683 ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
2686 let Inst{20} = iop{1};
2687 let Inst{19-16} = Zm;
2688 let Inst{11} = iop{0};
2692 //===----------------------------------------------------------------------===//
2693 // SVE2 Integer - Predicated Group
2694 //===----------------------------------------------------------------------===//
2696 class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
2698 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
2699 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
2703 let Inst{31-24} = 0b01000100;
2704 let Inst{23-22} = sz;
2706 let Inst{20-16} = opc{5-1};
2707 let Inst{15-14} = 0b10;
2708 let Inst{13} = opc{0};
2709 let Inst{12-10} = Pg;
2711 let Inst{4-0} = Zdn;
2713 let Constraints = "$Zdn = $_Zdn";
2714 let DestructiveInstType = Destructive;
2715 let ElementSize = zprty.ElementSize;
2718 multiclass sve2_int_arith_pred<bits<6> opc, string asm> {
2719 def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>;
2720 def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>;
2721 def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>;
2722 def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>;
2725 class sve2_int_sadd_long_accum_pairwise<bits<2> sz, bit U, string asm,
2726 ZPRRegOp zprty1, ZPRRegOp zprty2>
2727 : I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn),
2728 asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> {
2732 let Inst{31-24} = 0b01000100;
2733 let Inst{23-22} = sz;
2734 let Inst{21-17} = 0b00010;
2736 let Inst{15-13} = 0b101;
2737 let Inst{12-10} = Pg;
2739 let Inst{4-0} = Zda;
2741 let Constraints = "$Zda = $_Zda";
2742 let DestructiveInstType = Destructive;
2743 let ElementSize = zprty1.ElementSize;
2746 multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm> {
2747 def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>;
2748 def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>;
2749 def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>;
2752 class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
2753 string asm, ZPRRegOp zprty>
2754 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
2755 asm, "\t$Zd, $Pg/m, $Zn",
2761 let Inst{31-24} = 0b01000100;
2762 let Inst{23-22} = sz;
2763 let Inst{21-20} = 0b00;
2766 let Inst{17-16} = opc;
2767 let Inst{15-13} = 0b101;
2768 let Inst{12-10} = Pg;
2772 let Constraints = "$Zd = $_Zd";
2773 let DestructiveInstType = Destructive;
2774 let ElementSize = zprty.ElementSize;
2777 multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm> {
2778 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
2781 multiclass sve2_int_un_pred_arit<bits<3> opc, string asm> {
2782 def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>;
2783 def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>;
2784 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
2785 def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>;
2788 //===----------------------------------------------------------------------===//
2789 // SVE2 Widening Integer Arithmetic Group
2790 //===----------------------------------------------------------------------===//
2792 class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm,
2793 ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3>
2794 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm),
2795 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2799 let Inst{31-24} = 0b01000101;
2800 let Inst{23-22} = sz;
2802 let Inst{20-16} = Zm;
2804 let Inst{14-10} = opc;
2809 multiclass sve2_wide_int_arith_long<bits<5> opc, string asm> {
2810 def _H : sve2_wide_int_arith<0b01, opc, asm, ZPR16, ZPR8, ZPR8>;
2811 def _S : sve2_wide_int_arith<0b10, opc, asm, ZPR32, ZPR16, ZPR16>;
2812 def _D : sve2_wide_int_arith<0b11, opc, asm, ZPR64, ZPR32, ZPR32>;
2815 multiclass sve2_wide_int_arith_wide<bits<3> opc, string asm> {
2816 def _H : sve2_wide_int_arith<0b01, { 0b10, opc }, asm, ZPR16, ZPR16, ZPR8>;
2817 def _S : sve2_wide_int_arith<0b10, { 0b10, opc }, asm, ZPR32, ZPR32, ZPR16>;
2818 def _D : sve2_wide_int_arith<0b11, { 0b10, opc }, asm, ZPR64, ZPR64, ZPR32>;
2821 multiclass sve2_pmul_long<bits<1> opc, string asm> {
2822 def _H : sve2_wide_int_arith<0b01, {0b1101, opc}, asm, ZPR16, ZPR8, ZPR8>;
2823 def _D : sve2_wide_int_arith<0b11, {0b1101, opc}, asm, ZPR64, ZPR32, ZPR32>;
2826 //===----------------------------------------------------------------------===//
2828 //===----------------------------------------------------------------------===//
2830 class sve2_misc<bits<2> sz, bits<4> opc, string asm,
2831 ZPRRegOp zprty1, ZPRRegOp zprty2>
2832 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
2833 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2837 let Inst{31-24} = 0b01000101;
2838 let Inst{23-22} = sz;
2840 let Inst{20-16} = Zm;
2841 let Inst{15-14} = 0b10;
2842 let Inst{13-10} = opc;
2847 multiclass sve2_misc_bitwise<bits<4> opc, string asm> {
2848 def _B : sve2_misc<0b00, opc, asm, ZPR8, ZPR8>;
2849 def _H : sve2_misc<0b01, opc, asm, ZPR16, ZPR16>;
2850 def _S : sve2_misc<0b10, opc, asm, ZPR32, ZPR32>;
2851 def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>;
2854 multiclass sve2_misc_int_addsub_long_interleaved<bits<2> opc, string asm> {
2855 def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
2856 def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
2857 def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
2860 class sve2_bitwise_xor_interleaved<bits<2> sz, bits<1> opc, string asm,
2861 ZPRRegOp zprty1, ZPRRegOp zprty2>
2862 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
2863 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2867 let Inst{31-24} = 0b01000101;
2868 let Inst{23-22} = sz;
2870 let Inst{20-16} = Zm;
2871 let Inst{15-11} = 0b10010;
2876 let Constraints = "$Zd = $_Zd";
2877 let DestructiveInstType = Destructive;
2878 let ElementSize = ElementSizeNone;
2881 multiclass sve2_bitwise_xor_interleaved<bit opc, string asm> {
2882 def _B : sve2_bitwise_xor_interleaved<0b00, opc, asm, ZPR8, ZPR8>;
2883 def _H : sve2_bitwise_xor_interleaved<0b01, opc, asm, ZPR16, ZPR16>;
2884 def _S : sve2_bitwise_xor_interleaved<0b10, opc, asm, ZPR32, ZPR32>;
2885 def _D : sve2_bitwise_xor_interleaved<0b11, opc, asm, ZPR64, ZPR64>;
2888 class sve2_bitwise_shift_left_long<bits<3> tsz8_64, bits<2> opc, string asm,
2889 ZPRRegOp zprty1, ZPRRegOp zprty2,
2891 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
2892 asm, "\t$Zd, $Zn, $imm",
2893 "", []>, Sched<[]> {
2897 let Inst{31-23} = 0b010001010;
2898 let Inst{22} = tsz8_64{2};
2900 let Inst{20-19} = tsz8_64{1-0};
2901 let Inst{18-16} = imm{2-0}; // imm3
2902 let Inst{15-12} = 0b1010;
2903 let Inst{11-10} = opc;
2908 multiclass sve2_bitwise_shift_left_long<bits<2> opc, string asm> {
2909 def _H : sve2_bitwise_shift_left_long<{0,0,1}, opc, asm,
2910 ZPR16, ZPR8, vecshiftL8>;
2911 def _S : sve2_bitwise_shift_left_long<{0,1,?}, opc, asm,
2912 ZPR32, ZPR16, vecshiftL16> {
2913 let Inst{19} = imm{3};
2915 def _D : sve2_bitwise_shift_left_long<{1,?,?}, opc, asm,
2916 ZPR64, ZPR32, vecshiftL32> {
2917 let Inst{20-19} = imm{4-3};
2921 //===----------------------------------------------------------------------===//
2922 // SVE2 Accumulate Group
2923 //===----------------------------------------------------------------------===//
2925 class sve2_int_bin_shift_imm<bits<4> tsz8_64, bit opc, string asm,
2926 ZPRRegOp zprty, Operand immtype>
2927 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, immtype:$imm),
2928 asm, "\t$Zd, $Zn, $imm",
2929 "", []>, Sched<[]> {
2933 let Inst{31-24} = 0b01000101;
2934 let Inst{23-22} = tsz8_64{3-2};
2936 let Inst{20-19} = tsz8_64{1-0};
2937 let Inst{18-16} = imm{2-0}; // imm3
2938 let Inst{15-11} = 0b11110;
2943 let Constraints = "$Zd = $_Zd";
2946 multiclass sve2_int_bin_shift_imm_left<bit opc, string asm> {
2947 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
2948 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
2949 let Inst{19} = imm{3};
2951 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
2952 let Inst{20-19} = imm{4-3};
2954 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
2955 let Inst{22} = imm{5};
2956 let Inst{20-19} = imm{4-3};
2960 multiclass sve2_int_bin_shift_imm_right<bit opc, string asm> {
2961 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2962 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
2963 let Inst{19} = imm{3};
2965 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
2966 let Inst{20-19} = imm{4-3};
2968 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
2969 let Inst{22} = imm{5};
2970 let Inst{20-19} = imm{4-3};
2974 class sve2_int_bin_accum_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
2975 ZPRRegOp zprty, Operand immtype>
2976 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm),
2977 asm, "\t$Zda, $Zn, $imm",
2978 "", []>, Sched<[]> {
2982 let Inst{31-24} = 0b01000101;
2983 let Inst{23-22} = tsz8_64{3-2};
2985 let Inst{20-19} = tsz8_64{1-0};
2986 let Inst{18-16} = imm{2-0}; // imm3
2987 let Inst{15-12} = 0b1110;
2988 let Inst{11-10} = opc;
2990 let Inst{4-0} = Zda;
2992 let Constraints = "$Zda = $_Zda";
2993 let DestructiveInstType = Destructive;
2994 let ElementSize = ElementSizeNone;
2997 multiclass sve2_int_bin_accum_shift_imm_right<bits<2> opc, string asm> {
2998 def _B : sve2_int_bin_accum_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2999 def _H : sve2_int_bin_accum_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
3000 let Inst{19} = imm{3};
3002 def _S : sve2_int_bin_accum_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
3003 let Inst{20-19} = imm{4-3};
3005 def _D : sve2_int_bin_accum_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
3006 let Inst{22} = imm{5};
3007 let Inst{20-19} = imm{4-3};
3011 class sve2_int_cadd<bits<2> sz, bit opc, string asm, ZPRRegOp zprty>
3012 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot),
3013 asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> {
3017 let Inst{31-24} = 0b01000101;
3018 let Inst{23-22} = sz;
3019 let Inst{21-17} = 0b00000;
3021 let Inst{15-11} = 0b11011;
3024 let Inst{4-0} = Zdn;
3026 let Constraints = "$Zdn = $_Zdn";
3027 let DestructiveInstType = Destructive;
3028 let ElementSize = ElementSizeNone;
3031 multiclass sve2_int_cadd<bit opc, string asm> {
3032 def _B : sve2_int_cadd<0b00, opc, asm, ZPR8>;
3033 def _H : sve2_int_cadd<0b01, opc, asm, ZPR16>;
3034 def _S : sve2_int_cadd<0b10, opc, asm, ZPR32>;
3035 def _D : sve2_int_cadd<0b11, opc, asm, ZPR64>;
3038 class sve2_int_absdiff_accum<bits<2> sz, bits<4> opc, string asm,
3039 ZPRRegOp zprty1, ZPRRegOp zprty2>
3040 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
3041 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
3045 let Inst{31-24} = 0b01000101;
3046 let Inst{23-22} = sz;
3048 let Inst{20-16} = Zm;
3049 let Inst{15-14} = 0b11;
3050 let Inst{13-10} = opc;
3052 let Inst{4-0} = Zda;
3054 let Constraints = "$Zda = $_Zda";
3055 let DestructiveInstType = Destructive;
3056 let ElementSize = ElementSizeNone;
3059 multiclass sve2_int_absdiff_accum<bit opc, string asm> {
3060 def _B : sve2_int_absdiff_accum<0b00, { 0b111, opc }, asm, ZPR8, ZPR8>;
3061 def _H : sve2_int_absdiff_accum<0b01, { 0b111, opc }, asm, ZPR16, ZPR16>;
3062 def _S : sve2_int_absdiff_accum<0b10, { 0b111, opc }, asm, ZPR32, ZPR32>;
3063 def _D : sve2_int_absdiff_accum<0b11, { 0b111, opc }, asm, ZPR64, ZPR64>;
3066 multiclass sve2_int_absdiff_accum_long<bits<2> opc, string asm> {
3067 def _H : sve2_int_absdiff_accum<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
3068 def _S : sve2_int_absdiff_accum<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
3069 def _D : sve2_int_absdiff_accum<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
3072 multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm> {
3073 def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm,
3075 def _D : sve2_int_absdiff_accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm,
3079 //===----------------------------------------------------------------------===//
3080 // SVE2 Narrowing Group
3081 //===----------------------------------------------------------------------===//
3083 class sve2_int_bin_shift_imm_narrow_bottom<bits<3> tsz8_64, bits<3> opc,
3084 string asm, ZPRRegOp zprty1,
3085 ZPRRegOp zprty2, Operand immtype>
3086 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
3087 asm, "\t$Zd, $Zn, $imm",
3088 "", []>, Sched<[]> {
3092 let Inst{31-23} = 0b010001010;
3093 let Inst{22} = tsz8_64{2};
3095 let Inst{20-19} = tsz8_64{1-0};
3096 let Inst{18-16} = imm{2-0}; // imm3
3097 let Inst{15-14} = 0b00;
3098 let Inst{13-11} = opc;
3104 multiclass sve2_int_bin_shift_imm_right_narrow_bottom<bits<3> opc, string asm,
3105 SDPatternOperator op> {
3106 def _B : sve2_int_bin_shift_imm_narrow_bottom<{0,0,1}, opc, asm, ZPR8, ZPR16,
3108 def _H : sve2_int_bin_shift_imm_narrow_bottom<{0,1,?}, opc, asm, ZPR16, ZPR32,
3110 let Inst{19} = imm{3};
3112 def _S : sve2_int_bin_shift_imm_narrow_bottom<{1,?,?}, opc, asm, ZPR32, ZPR64,
3114 let Inst{20-19} = imm{4-3};
3116 def : SVE_2_Op_Imm_Pat<nxv16i8, op, nxv8i16, i32, tvecshiftR8, !cast<Instruction>(NAME # _B)>;
3117 def : SVE_2_Op_Imm_Pat<nxv8i16, op, nxv4i32, i32, tvecshiftR16, !cast<Instruction>(NAME # _H)>;
3118 def : SVE_2_Op_Imm_Pat<nxv4i32, op, nxv2i64, i32, tvecshiftR32, !cast<Instruction>(NAME # _S)>;
3121 class sve2_int_bin_shift_imm_narrow_top<bits<3> tsz8_64, bits<3> opc,
3122 string asm, ZPRRegOp zprty1,
3123 ZPRRegOp zprty2, Operand immtype>
3124 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, immtype:$imm),
3125 asm, "\t$Zd, $Zn, $imm",
3126 "", []>, Sched<[]> {
3130 let Inst{31-23} = 0b010001010;
3131 let Inst{22} = tsz8_64{2};
3133 let Inst{20-19} = tsz8_64{1-0};
3134 let Inst{18-16} = imm{2-0}; // imm3
3135 let Inst{15-14} = 0b00;
3136 let Inst{13-11} = opc;
3141 let Constraints = "$Zd = $_Zd";
3144 multiclass sve2_int_bin_shift_imm_right_narrow_top<bits<3> opc, string asm,
3145 SDPatternOperator op> {
3146 def _B : sve2_int_bin_shift_imm_narrow_top<{0,0,1}, opc, asm, ZPR8, ZPR16,
3148 def _H : sve2_int_bin_shift_imm_narrow_top<{0,1,?}, opc, asm, ZPR16, ZPR32,
3150 let Inst{19} = imm{3};
3152 def _S : sve2_int_bin_shift_imm_narrow_top<{1,?,?}, opc, asm, ZPR32, ZPR64,
3154 let Inst{20-19} = imm{4-3};
3156 def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv8i16, i32, tvecshiftR8, !cast<Instruction>(NAME # _B)>;
3157 def : SVE_3_Op_Imm_Pat<nxv8i16, op, nxv8i16, nxv4i32, i32, tvecshiftR16, !cast<Instruction>(NAME # _H)>;
3158 def : SVE_3_Op_Imm_Pat<nxv4i32, op, nxv4i32, nxv2i64, i32, tvecshiftR32, !cast<Instruction>(NAME # _S)>;
3161 class sve2_int_addsub_narrow_high_bottom<bits<2> sz, bits<2> opc, string asm,
3162 ZPRRegOp zprty1, ZPRRegOp zprty2>
3163 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
3164 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
3168 let Inst{31-24} = 0b01000101;
3169 let Inst{23-22} = sz;
3171 let Inst{20-16} = Zm;
3172 let Inst{15-13} = 0b011;
3173 let Inst{12-11} = opc; // S, R
3174 let Inst{10} = 0b0; // Top
3179 multiclass sve2_int_addsub_narrow_high_bottom<bits<2> opc, string asm,
3180 SDPatternOperator op> {
3181 def _B : sve2_int_addsub_narrow_high_bottom<0b01, opc, asm, ZPR8, ZPR16>;
3182 def _H : sve2_int_addsub_narrow_high_bottom<0b10, opc, asm, ZPR16, ZPR32>;
3183 def _S : sve2_int_addsub_narrow_high_bottom<0b11, opc, asm, ZPR32, ZPR64>;
3185 def : SVE_2_Op_Pat<nxv16i8, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _B)>;
3186 def : SVE_2_Op_Pat<nxv8i16, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _H)>;
3187 def : SVE_2_Op_Pat<nxv4i32, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _S)>;
3190 class sve2_int_addsub_narrow_high_top<bits<2> sz, bits<2> opc, string asm,
3191 ZPRRegOp zprty1, ZPRRegOp zprty2>
3192 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
3193 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
3197 let Inst{31-24} = 0b01000101;
3198 let Inst{23-22} = sz;
3200 let Inst{20-16} = Zm;
3201 let Inst{15-13} = 0b011;
3202 let Inst{12-11} = opc; // S, R
3203 let Inst{10} = 0b1; // Top
3207 let Constraints = "$Zd = $_Zd";
3210 multiclass sve2_int_addsub_narrow_high_top<bits<2> opc, string asm,
3211 SDPatternOperator op> {
3212 def _B : sve2_int_addsub_narrow_high_top<0b01, opc, asm, ZPR8, ZPR16>;
3213 def _H : sve2_int_addsub_narrow_high_top<0b10, opc, asm, ZPR16, ZPR32>;
3214 def _S : sve2_int_addsub_narrow_high_top<0b11, opc, asm, ZPR32, ZPR64>;
3216 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _B)>;
3217 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _H)>;
3218 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _S)>;
3221 class sve2_int_sat_extract_narrow_bottom<bits<3> tsz8_64, bits<2> opc, string asm,
3222 ZPRRegOp zprty1, ZPRRegOp zprty2>
3223 : I<(outs zprty1:$Zd), (ins zprty2:$Zn),
3224 asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
3227 let Inst{31-23} = 0b010001010;
3228 let Inst{22} = tsz8_64{2};
3230 let Inst{20-19} = tsz8_64{1-0};
3231 let Inst{18-13} = 0b000010;
3232 let Inst{12-11} = opc;
3238 multiclass sve2_int_sat_extract_narrow_bottom<bits<2> opc, string asm,
3239 SDPatternOperator op> {
3240 def _B : sve2_int_sat_extract_narrow_bottom<0b001, opc, asm, ZPR8, ZPR16>;
3241 def _H : sve2_int_sat_extract_narrow_bottom<0b010, opc, asm, ZPR16, ZPR32>;
3242 def _S : sve2_int_sat_extract_narrow_bottom<0b100, opc, asm, ZPR32, ZPR64>;
3244 def : SVE_1_Op_Pat<nxv16i8, op, nxv8i16, !cast<Instruction>(NAME # _B)>;
3245 def : SVE_1_Op_Pat<nxv8i16, op, nxv4i32, !cast<Instruction>(NAME # _H)>;
3246 def : SVE_1_Op_Pat<nxv4i32, op, nxv2i64, !cast<Instruction>(NAME # _S)>;
3249 class sve2_int_sat_extract_narrow_top<bits<3> tsz8_64, bits<2> opc, string asm,
3250 ZPRRegOp zprty1, ZPRRegOp zprty2>
3251 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn),
3252 asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
3255 let Inst{31-23} = 0b010001010;
3256 let Inst{22} = tsz8_64{2};
3258 let Inst{20-19} = tsz8_64{1-0};
3259 let Inst{18-13} = 0b000010;
3260 let Inst{12-11} = opc;
3265 let Constraints = "$Zd = $_Zd";
3268 multiclass sve2_int_sat_extract_narrow_top<bits<2> opc, string asm,
3269 SDPatternOperator op> {
3270 def _B : sve2_int_sat_extract_narrow_top<0b001, opc, asm, ZPR8, ZPR16>;
3271 def _H : sve2_int_sat_extract_narrow_top<0b010, opc, asm, ZPR16, ZPR32>;
3272 def _S : sve2_int_sat_extract_narrow_top<0b100, opc, asm, ZPR32, ZPR64>;
3274 def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv8i16, !cast<Instruction>(NAME # _B)>;
3275 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv4i32, !cast<Instruction>(NAME # _H)>;
3276 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
3279 //===----------------------------------------------------------------------===//
3280 // SVE Integer Arithmetic - Unary Predicated Group
3281 //===----------------------------------------------------------------------===//
3283 class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
3284 string asm, ZPRRegOp zprty>
3285 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
3286 asm, "\t$Zd, $Pg/m, $Zn",
3292 let Inst{31-24} = 0b00000100;
3293 let Inst{23-22} = sz8_64;
3294 let Inst{21-20} = 0b01;
3295 let Inst{19} = opc{0};
3296 let Inst{18-16} = opc{3-1};
3297 let Inst{15-13} = 0b101;
3298 let Inst{12-10} = Pg;
3302 let Constraints = "$Zd = $_Zd";
3303 let DestructiveInstType = Destructive;
3304 let ElementSize = zprty.ElementSize;
3307 multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm,
3308 SDPatternOperator op> {
3309 def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>;
3310 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
3311 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
3312 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
3314 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
3315 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
3316 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
3317 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
3320 multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm,
3321 SDPatternOperator op> {
3322 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
3323 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
3324 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
3326 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
3327 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
3328 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
3331 multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm,
3332 SDPatternOperator op> {
3333 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
3334 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
3336 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
3337 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
3340 multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm,
3341 SDPatternOperator op> {
3342 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
3344 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
3347 multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
3348 SDPatternOperator op> {
3349 def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>;
3350 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
3351 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
3352 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
3354 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
3355 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
3356 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
3357 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
3359 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
3360 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
3361 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
3364 multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm,
3365 SDPatternOperator op> {
3366 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
3367 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
3368 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
3370 def : SVE_3_Op_Pat<nxv8f16, op, nxv8f16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
3371 def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
3372 def : SVE_3_Op_Pat<nxv2f64, op, nxv2f64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
3375 //===----------------------------------------------------------------------===//
3376 // SVE Integer Wide Immediate - Unpredicated Group
3377 //===----------------------------------------------------------------------===//
3378 class sve_int_dup_imm<bits<2> sz8_64, string asm,
3379 ZPRRegOp zprty, Operand immtype>
3380 : I<(outs zprty:$Zd), (ins immtype:$imm),
3386 let Inst{31-24} = 0b00100101;
3387 let Inst{23-22} = sz8_64;
3388 let Inst{21-14} = 0b11100011;
3389 let Inst{13} = imm{8}; // sh
3390 let Inst{12-5} = imm{7-0}; // imm8
3393 let isReMaterializable = 1;
3396 multiclass sve_int_dup_imm<string asm> {
3397 def _B : sve_int_dup_imm<0b00, asm, ZPR8, cpy_imm8_opt_lsl_i8>;
3398 def _H : sve_int_dup_imm<0b01, asm, ZPR16, cpy_imm8_opt_lsl_i16>;
3399 def _S : sve_int_dup_imm<0b10, asm, ZPR32, cpy_imm8_opt_lsl_i32>;
3400 def _D : sve_int_dup_imm<0b11, asm, ZPR64, cpy_imm8_opt_lsl_i64>;
3402 def : InstAlias<"mov $Zd, $imm",
3403 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm), 1>;
3404 def : InstAlias<"mov $Zd, $imm",
3405 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm), 1>;
3406 def : InstAlias<"mov $Zd, $imm",
3407 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>;
3408 def : InstAlias<"mov $Zd, $imm",
3409 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>;
3411 def : InstAlias<"fmov $Zd, #0.0",
3412 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, 0, 0), 1>;
3413 def : InstAlias<"fmov $Zd, #0.0",
3414 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>;
3415 def : InstAlias<"fmov $Zd, #0.0",
3416 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, 0, 0), 1>;
3419 class sve_int_dup_fpimm<bits<2> sz8_64, Operand fpimmtype,
3420 string asm, ZPRRegOp zprty>
3421 : I<(outs zprty:$Zd), (ins fpimmtype:$imm8),
3422 asm, "\t$Zd, $imm8",
3427 let Inst{31-24} = 0b00100101;
3428 let Inst{23-22} = sz8_64;
3429 let Inst{21-14} = 0b11100111;
3431 let Inst{12-5} = imm8;
3434 let isReMaterializable = 1;
3437 multiclass sve_int_dup_fpimm<string asm> {
3438 def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>;
3439 def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>;
3440 def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>;
3442 def : InstAlias<"fmov $Zd, $imm8",
3443 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>;
3444 def : InstAlias<"fmov $Zd, $imm8",
3445 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>;
3446 def : InstAlias<"fmov $Zd, $imm8",
3447 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>;
3450 class sve_int_arith_imm0<bits<2> sz8_64, bits<3> opc, string asm,
3451 ZPRRegOp zprty, Operand immtype>
3452 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
3453 asm, "\t$Zdn, $_Zdn, $imm",
3458 let Inst{31-24} = 0b00100101;
3459 let Inst{23-22} = sz8_64;
3460 let Inst{21-19} = 0b100;
3461 let Inst{18-16} = opc;
3462 let Inst{15-14} = 0b11;
3463 let Inst{13} = imm{8}; // sh
3464 let Inst{12-5} = imm{7-0}; // imm8
3465 let Inst{4-0} = Zdn;
3467 let Constraints = "$Zdn = $_Zdn";
3468 let DestructiveInstType = Destructive;
3469 let ElementSize = ElementSizeNone;
3472 multiclass sve_int_arith_imm0<bits<3> opc, string asm, SDPatternOperator op> {
3473 def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>;
3474 def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>;
3475 def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>;
3476 def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>;
3478 def : SVE_1_Op_Imm_OptLsl_Pat<nxv16i8, op, ZPR8, i32, SVEAddSubImm8Pat, !cast<Instruction>(NAME # _B)>;
3479 def : SVE_1_Op_Imm_OptLsl_Pat<nxv8i16, op, ZPR16, i32, SVEAddSubImm16Pat, !cast<Instruction>(NAME # _H)>;
3480 def : SVE_1_Op_Imm_OptLsl_Pat<nxv4i32, op, ZPR32, i32, SVEAddSubImm32Pat, !cast<Instruction>(NAME # _S)>;
3481 def : SVE_1_Op_Imm_OptLsl_Pat<nxv2i64, op, ZPR64, i64, SVEAddSubImm64Pat, !cast<Instruction>(NAME # _D)>;
3484 multiclass sve_int_arith_imm0_subr<bits<3> opc, string asm, SDPatternOperator op> {
3485 def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>;
3486 def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>;
3487 def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>;
3488 def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>;
3490 def : SVE_1_Op_Imm_OptLsl_Reverse_Pat<nxv16i8, op, ZPR8, i32, SVEAddSubImm8Pat, !cast<Instruction>(NAME # _B)>;
3491 def : SVE_1_Op_Imm_OptLsl_Reverse_Pat<nxv8i16, op, ZPR16, i32, SVEAddSubImm16Pat, !cast<Instruction>(NAME # _H)>;
3492 def : SVE_1_Op_Imm_OptLsl_Reverse_Pat<nxv4i32, op, ZPR32, i32, SVEAddSubImm32Pat, !cast<Instruction>(NAME # _S)>;
3493 def : SVE_1_Op_Imm_OptLsl_Reverse_Pat<nxv2i64, op, ZPR64, i64, SVEAddSubImm64Pat, !cast<Instruction>(NAME # _D)>;
3496 class sve_int_arith_imm<bits<2> sz8_64, bits<6> opc, string asm,
3497 ZPRRegOp zprty, Operand immtype>
3498 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
3499 asm, "\t$Zdn, $_Zdn, $imm",
3504 let Inst{31-24} = 0b00100101;
3505 let Inst{23-22} = sz8_64;
3506 let Inst{21-16} = opc;
3507 let Inst{15-13} = 0b110;
3508 let Inst{12-5} = imm;
3509 let Inst{4-0} = Zdn;
3511 let Constraints = "$Zdn = $_Zdn";
3512 let DestructiveInstType = Destructive;
3513 let ElementSize = ElementSizeNone;
3516 multiclass sve_int_arith_imm1<bits<2> opc, string asm, SDPatternOperator op> {
3517 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, simm8>;
3518 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, simm8>;
3519 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, simm8>;
3520 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, simm8>;
3522 def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _B)>;
3523 def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _H)>;
3524 def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _S)>;
3525 def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithSImmPat, !cast<Instruction>(NAME # _D)>;
3528 multiclass sve_int_arith_imm1_unsigned<bits<2> opc, string asm, SDPatternOperator op> {
3529 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, imm0_255>;
3530 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, imm0_255>;
3531 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, imm0_255>;
3532 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, imm0_255>;
3534 def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithUImmPat, !cast<Instruction>(NAME # _B)>;
3535 def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithUImmPat, !cast<Instruction>(NAME # _H)>;
3536 def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithUImmPat, !cast<Instruction>(NAME # _S)>;
3537 def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithUImmPat, !cast<Instruction>(NAME # _D)>;
3540 multiclass sve_int_arith_imm2<string asm, SDPatternOperator op> {
3541 def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>;
3542 def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
3543 def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
3544 def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
3546 def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _B)>;
3547 def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _H)>;
3548 def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _S)>;
3549 def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithSImmPat, !cast<Instruction>(NAME # _D)>;
3552 //===----------------------------------------------------------------------===//
3553 // SVE Bitwise Logical - Unpredicated Group
3554 //===----------------------------------------------------------------------===//
3556 class sve_int_bin_cons_log<bits<2> opc, string asm>
3557 : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm),
3558 asm, "\t$Zd, $Zn, $Zm",
3564 let Inst{31-24} = 0b00000100;
3565 let Inst{23-22} = opc{1-0};
3567 let Inst{20-16} = Zm;
3568 let Inst{15-10} = 0b001100;
3573 multiclass sve_int_bin_cons_log<bits<2> opc, string asm, SDPatternOperator op> {
3574 def NAME : sve_int_bin_cons_log<opc, asm>;
3576 def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME)>;
3577 def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME)>;
3578 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME)>;
3579 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME)>;
3581 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
3582 (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>;
3583 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
3584 (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
3585 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
3586 (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
3589 class sve2_int_bitwise_ternary_op_d<bits<3> opc, string asm>
3590 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk),
3591 asm, "\t$Zdn, $_Zdn, $Zm, $Zk",
3597 let Inst{31-24} = 0b00000100;
3598 let Inst{23-22} = opc{2-1};
3600 let Inst{20-16} = Zm;
3601 let Inst{15-11} = 0b00111;
3602 let Inst{10} = opc{0};
3604 let Inst{4-0} = Zdn;
3606 let Constraints = "$Zdn = $_Zdn";
3607 let DestructiveInstType = Destructive;
3608 let ElementSize = ElementSizeNone;
3611 multiclass sve2_int_bitwise_ternary_op<bits<3> opc, string asm> {
3612 def NAME : sve2_int_bitwise_ternary_op_d<opc, asm>;
3614 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
3615 (!cast<Instruction>(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>;
3616 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
3617 (!cast<Instruction>(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>;
3618 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
3619 (!cast<Instruction>(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>;
3622 class sve2_int_rotate_right_imm<bits<4> tsz8_64, string asm,
3623 ZPRRegOp zprty, Operand immtype>
3624 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm),
3625 asm, "\t$Zdn, $_Zdn, $Zm, $imm",
3631 let Inst{31-24} = 0b00000100;
3632 let Inst{23-22} = tsz8_64{3-2};
3634 let Inst{20-19} = tsz8_64{1-0};
3635 let Inst{18-16} = imm{2-0}; // imm3
3636 let Inst{15-10} = 0b001101;
3638 let Inst{4-0} = Zdn;
3640 let Constraints = "$Zdn = $_Zdn";
3641 let DestructiveInstType = Destructive;
3642 let ElementSize = ElementSizeNone;
3645 multiclass sve2_int_rotate_right_imm<string asm> {
3646 def _B : sve2_int_rotate_right_imm<{0,0,0,1}, asm, ZPR8, vecshiftR8>;
3647 def _H : sve2_int_rotate_right_imm<{0,0,1,?}, asm, ZPR16, vecshiftR16> {
3648 let Inst{19} = imm{3};
3650 def _S : sve2_int_rotate_right_imm<{0,1,?,?}, asm, ZPR32, vecshiftR32> {
3651 let Inst{20-19} = imm{4-3};
3653 def _D : sve2_int_rotate_right_imm<{1,?,?,?}, asm, ZPR64, vecshiftR64> {
3654 let Inst{22} = imm{5};
3655 let Inst{20-19} = imm{4-3};
3659 //===----------------------------------------------------------------------===//
3660 // SVE Integer Wide Immediate - Predicated Group
3661 //===----------------------------------------------------------------------===//
3663 class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype,
3664 string asm, ZPRRegOp zprty>
3665 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8),
3666 asm, "\t$Zd, $Pg/m, $imm8",
3672 let Inst{31-24} = 0b00000101;
3673 let Inst{23-22} = sz;
3674 let Inst{21-20} = 0b01;
3675 let Inst{19-16} = Pg;
3676 let Inst{15-13} = 0b110;
3677 let Inst{12-5} = imm8;
3680 let Constraints = "$Zd = $_Zd";
3681 let DestructiveInstType = Destructive;
3682 let ElementSize = zprty.ElementSize;
3685 multiclass sve_int_dup_fpimm_pred<string asm> {
3686 def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>;
3687 def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>;
3688 def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>;
3690 def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
3691 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8), 1>;
3692 def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
3693 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8), 1>;
3694 def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
3695 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8), 1>;
3698 class sve_int_dup_imm_pred<bits<2> sz8_64, bit m, string asm,
3699 ZPRRegOp zprty, string pred_qual, dag iops>
3700 : I<(outs zprty:$Zd), iops,
3701 asm, "\t$Zd, $Pg"#pred_qual#", $imm",
3702 "", []>, Sched<[]> {
3706 let Inst{31-24} = 0b00000101;
3707 let Inst{23-22} = sz8_64;
3708 let Inst{21-20} = 0b01;
3709 let Inst{19-16} = Pg;
3712 let Inst{13} = imm{8}; // sh
3713 let Inst{12-5} = imm{7-0}; // imm8
3716 let DestructiveInstType = Destructive;
3717 let ElementSize = zprty.ElementSize;
3720 multiclass sve_int_dup_imm_pred_merge<string asm> {
3721 let Constraints = "$Zd = $_Zd" in {
3722 def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
3723 def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
3724 def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
3725 def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
3728 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3729 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>;
3730 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3731 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>;
3732 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3733 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>;
3734 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3735 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>;
3737 def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
3738 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, 0, 0), 0>;
3739 def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
3740 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, 0, 0), 0>;
3741 def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
3742 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, 0, 0), 0>;
3745 multiclass sve_int_dup_imm_pred_zero<string asm> {
3746 def _B : sve_int_dup_imm_pred<0b00, 0, asm, ZPR8, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
3747 def _H : sve_int_dup_imm_pred<0b01, 0, asm, ZPR16, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
3748 def _S : sve_int_dup_imm_pred<0b10, 0, asm, ZPR32, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
3749 def _D : sve_int_dup_imm_pred<0b11, 0, asm, ZPR64, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
3751 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3752 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>;
3753 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3754 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>;
3755 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3756 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>;
3757 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3758 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>;
3761 //===----------------------------------------------------------------------===//
3762 // SVE Integer Compare - Vectors Group
3763 //===----------------------------------------------------------------------===//
3765 class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
3766 PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2>
3767 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
3768 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
3775 let Inst{31-24} = 0b00100100;
3776 let Inst{23-22} = sz8_64;
3778 let Inst{20-16} = Zm;
3779 let Inst{15} = opc{2};
3780 let Inst{14} = cmp_1;
3781 let Inst{13} = opc{1};
3782 let Inst{12-10} = Pg;
3784 let Inst{4} = opc{0};
3790 multiclass sve_int_cmp_0<bits<3> opc, string asm, SDPatternOperator op,
3792 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>;
3793 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>;
3794 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
3795 def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
3797 def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
3798 def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
3799 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
3800 def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
3803 multiclass sve_int_cmp_0_wide<bits<3> opc, string asm, SDPatternOperator op> {
3804 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
3805 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
3806 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
3808 def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv2i64, !cast<Instruction>(NAME # _B)>;
3809 def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv2i64, !cast<Instruction>(NAME # _H)>;
3810 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
3813 multiclass sve_int_cmp_1_wide<bits<3> opc, string asm, SDPatternOperator op> {
3814 def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
3815 def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
3816 def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
3818 def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv2i64, !cast<Instruction>(NAME # _B)>;
3819 def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv2i64, !cast<Instruction>(NAME # _H)>;
3820 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
3824 //===----------------------------------------------------------------------===//
3825 // SVE Integer Compare - Signed Immediate Group
3826 //===----------------------------------------------------------------------===//
3828 class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
3831 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
3832 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
3839 let Inst{31-24} = 0b00100101;
3840 let Inst{23-22} = sz8_64;
3842 let Inst{20-16} = imm5;
3843 let Inst{15} = opc{2};
3845 let Inst{13} = opc{1};
3846 let Inst{12-10} = Pg;
3848 let Inst{4} = opc{0};
3852 let ElementSize = pprty.ElementSize;
3855 multiclass sve_int_scmp_vi<bits<3> opc, string asm, CondCode cc,
3856 SDPatternOperator op = null_frag,
3857 SDPatternOperator inv_op = null_frag> {
3858 def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>;
3859 def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>;
3860 def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>;
3861 def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>;
3864 def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
3865 (nxv16i8 (AArch64dup (simm5_32b:$imm))),
3867 (!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, simm5_32b:$imm)>;
3868 def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
3869 (nxv8i16 (AArch64dup (simm5_32b:$imm))),
3871 (!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, simm5_32b:$imm)>;
3872 def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
3873 (nxv4i32 (AArch64dup (simm5_32b:$imm))),
3875 (!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, simm5_32b:$imm)>;
3876 def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
3877 (nxv2i64 (AArch64dup (simm5_64b:$imm))),
3879 (!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, simm5_64b:$imm)>;
3881 // Intrinsic version
3882 def : Pat<(nxv16i1 (op (nxv16i1 PPR_3b:$Pg),
3884 (nxv16i8 (AArch64dup (simm5_32b:$imm))))),
3885 (!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3886 def : Pat<(nxv8i1 (op (nxv8i1 PPR_3b:$Pg),
3888 (nxv8i16 (AArch64dup (simm5_32b:$imm))))),
3889 (!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3890 def : Pat<(nxv4i1 (op (nxv4i1 PPR_3b:$Pg),
3892 (nxv4i32 (AArch64dup (simm5_32b:$imm))))),
3893 (!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3894 def : Pat<(nxv2i1 (op (nxv2i1 PPR_3b:$Pg),
3896 (nxv2i64 (AArch64dup (simm5_64b:$imm))))),
3897 (!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, simm5_64b:$imm)>;
3899 // Inverted intrinsic version
3900 def : Pat<(nxv16i1 (inv_op (nxv16i1 PPR_3b:$Pg),
3901 (nxv16i8 (AArch64dup (simm5_32b:$imm))),
3902 (nxv16i8 ZPR:$Zs1))),
3903 (!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3904 def : Pat<(nxv8i1 (inv_op (nxv8i1 PPR_3b:$Pg),
3905 (nxv8i16 (AArch64dup (simm5_32b:$imm))),
3906 (nxv8i16 ZPR:$Zs1))),
3907 (!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3908 def : Pat<(nxv4i1 (inv_op (nxv4i1 PPR_3b:$Pg),
3909 (nxv4i32 (AArch64dup (simm5_32b:$imm))),
3910 (nxv4i32 ZPR:$Zs1))),
3911 (!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3912 def : Pat<(nxv2i1 (inv_op (nxv2i1 PPR_3b:$Pg),
3913 (nxv2i64 (AArch64dup (simm5_64b:$imm))),
3914 (nxv2i64 ZPR:$Zs1))),
3915 (!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, simm5_64b:$imm)>;
3919 //===----------------------------------------------------------------------===//
3920 // SVE Integer Compare - Unsigned Immediate Group
3921 //===----------------------------------------------------------------------===//
3923 class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
3924 ZPRRegOp zprty, Operand immtype>
3925 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
3926 asm, "\t$Pd, $Pg/z, $Zn, $imm7",
3933 let Inst{31-24} = 0b00100100;
3934 let Inst{23-22} = sz8_64;
3936 let Inst{20-14} = imm7;
3937 let Inst{13} = opc{1};
3938 let Inst{12-10} = Pg;
3940 let Inst{4} = opc{0};
3946 multiclass sve_int_ucmp_vi<bits<2> opc, string asm, CondCode cc,
3947 SDPatternOperator op = null_frag,
3948 SDPatternOperator inv_op = null_frag> {
3949 def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>;
3950 def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>;
3951 def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>;
3952 def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127_64b>;
3955 def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
3956 (nxv16i8 (AArch64dup (imm0_127:$imm))),
3958 (!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, imm0_127:$imm)>;
3959 def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
3960 (nxv8i16 (AArch64dup (imm0_127:$imm))),
3962 (!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, imm0_127:$imm)>;
3963 def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
3964 (nxv4i32 (AArch64dup (imm0_127:$imm))),
3966 (!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, imm0_127:$imm)>;
3967 def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
3968 (nxv2i64 (AArch64dup (imm0_127_64b:$imm))),
3970 (!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, imm0_127_64b:$imm)>;
3972 // Intrinsic version
3973 def : Pat<(nxv16i1 (op (nxv16i1 PPR_3b:$Pg),
3975 (nxv16i8 (AArch64dup (imm0_127:$imm))))),
3976 (!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3977 def : Pat<(nxv8i1 (op (nxv8i1 PPR_3b:$Pg),
3979 (nxv8i16 (AArch64dup (imm0_127:$imm))))),
3980 (!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3981 def : Pat<(nxv4i1 (op (nxv4i1 PPR_3b:$Pg),
3983 (nxv4i32 (AArch64dup (imm0_127:$imm))))),
3984 (!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3985 def : Pat<(nxv2i1 (op (nxv2i1 PPR_3b:$Pg),
3987 (nxv2i64 (AArch64dup (imm0_127_64b:$imm))))),
3988 (!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, imm0_127_64b:$imm)>;
3990 // Inverted intrinsic version
3991 def : Pat<(nxv16i1 (inv_op (nxv16i1 PPR_3b:$Pg),
3992 (nxv16i8 (AArch64dup (imm0_127:$imm))),
3993 (nxv16i8 ZPR:$Zs1))),
3994 (!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3995 def : Pat<(nxv8i1 (inv_op (nxv8i1 PPR_3b:$Pg),
3996 (nxv8i16 (AArch64dup (imm0_127:$imm))),
3997 (nxv8i16 ZPR:$Zs1))),
3998 (!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3999 def : Pat<(nxv4i1 (inv_op (nxv4i1 PPR_3b:$Pg),
4000 (nxv4i32 (AArch64dup (imm0_127:$imm))),
4001 (nxv4i32 ZPR:$Zs1))),
4002 (!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
4003 def : Pat<(nxv2i1 (inv_op (nxv2i1 PPR_3b:$Pg),
4004 (nxv2i64 (AArch64dup (imm0_127_64b:$imm))),
4005 (nxv2i64 ZPR:$Zs1))),
4006 (!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, imm0_127_64b:$imm)>;
4010 //===----------------------------------------------------------------------===//
4011 // SVE Integer Compare - Scalars Group
4012 //===----------------------------------------------------------------------===//
4014 class sve_int_cterm<bit sz, bit opc, string asm, RegisterClass rt>
4015 : I<(outs), (ins rt:$Rn, rt:$Rm),
4021 let Inst{31-23} = 0b001001011;
4024 let Inst{20-16} = Rm;
4025 let Inst{15-10} = 0b001000;
4028 let Inst{3-0} = 0b0000;
4033 class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm,
4034 RegisterClass gprty, PPRRegOp pprty,
4035 ValueType vt, SDPatternOperator op>
4036 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
4037 asm, "\t$Pd, $Rn, $Rm",
4038 "", []>, Sched<[]> {
4042 let Inst{31-24} = 0b00100101;
4043 let Inst{23-22} = sz8_64;
4045 let Inst{20-16} = Rm;
4046 let Inst{15-13} = 0b000;
4047 let Inst{12-10} = opc{3-1};
4049 let Inst{4} = opc{0};
4055 multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op> {
4056 def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8, nxv16i1, op>;
4057 def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16, nxv8i1, op>;
4058 def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32, nxv4i1, op>;
4059 def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64, nxv2i1, op>;
4061 def : SVE_2_Op_Pat<nxv16i1, op, i32, i32, !cast<Instruction>(NAME # _B)>;
4062 def : SVE_2_Op_Pat<nxv8i1, op, i32, i32, !cast<Instruction>(NAME # _H)>;
4063 def : SVE_2_Op_Pat<nxv4i1, op, i32, i32, !cast<Instruction>(NAME # _S)>;
4064 def : SVE_2_Op_Pat<nxv2i1, op, i32, i32, !cast<Instruction>(NAME # _D)>;
4067 multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op> {
4068 def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8, nxv16i1, op>;
4069 def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16, nxv8i1, op>;
4070 def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32, nxv4i1, op>;
4071 def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64, nxv2i1, op>;
4073 def : SVE_2_Op_Pat<nxv16i1, op, i64, i64, !cast<Instruction>(NAME # _B)>;
4074 def : SVE_2_Op_Pat<nxv8i1, op, i64, i64, !cast<Instruction>(NAME # _H)>;
4075 def : SVE_2_Op_Pat<nxv4i1, op, i64, i64, !cast<Instruction>(NAME # _S)>;
4076 def : SVE_2_Op_Pat<nxv2i1, op, i64, i64, !cast<Instruction>(NAME # _D)>;
4079 class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm,
4081 : I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
4082 asm, "\t$Pd, $Rn, $Rm",
4083 "", []>, Sched<[]> {
4087 let Inst{31-24} = 0b00100101;
4088 let Inst{23-22} = sz8_64;
4090 let Inst{20-16} = Rm;
4091 let Inst{15-10} = 0b001100;
4099 multiclass sve2_int_while_rr<bits<1> rw, string asm> {
4100 def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>;
4101 def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>;
4102 def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>;
4103 def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>;
4106 //===----------------------------------------------------------------------===//
4107 // SVE Floating Point Fast Reduction Group
4108 //===----------------------------------------------------------------------===//
4110 class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm,
4111 ZPRRegOp zprty, RegisterClass dstRegClass>
4112 : I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
4113 asm, "\t$Vd, $Pg, $Zn",
4119 let Inst{31-24} = 0b01100101;
4120 let Inst{23-22} = sz;
4121 let Inst{21-19} = 0b000;
4122 let Inst{18-16} = opc;
4123 let Inst{15-13} = 0b001;
4124 let Inst{12-10} = Pg;
4129 multiclass sve_fp_fast_red<bits<3> opc, string asm, SDPatternOperator op> {
4130 def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>;
4131 def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>;
4132 def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>;
4134 def : SVE_2_Op_Pat<f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
4135 def : SVE_2_Op_Pat<f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
4136 def : SVE_2_Op_Pat<f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
4140 //===----------------------------------------------------------------------===//
4141 // SVE Floating Point Accumulating Reduction Group
4142 //===----------------------------------------------------------------------===//
4144 class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm,
4145 ZPRRegOp zprty, RegisterClass dstRegClass>
4146 : I<(outs dstRegClass:$Vdn), (ins PPR3bAny:$Pg, dstRegClass:$_Vdn, zprty:$Zm),
4147 asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
4154 let Inst{31-24} = 0b01100101;
4155 let Inst{23-22} = sz;
4156 let Inst{21-19} = 0b011;
4157 let Inst{18-16} = opc;
4158 let Inst{15-13} = 0b001;
4159 let Inst{12-10} = Pg;
4161 let Inst{4-0} = Vdn;
4163 let Constraints = "$Vdn = $_Vdn";
4166 multiclass sve_fp_2op_p_vd<bits<3> opc, string asm, SDPatternOperator op> {
4167 def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>;
4168 def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>;
4169 def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>;
4171 def : SVE_3_Op_Pat<f16, op, nxv8i1, f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
4172 def : SVE_3_Op_Pat<f32, op, nxv4i1, f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
4173 def : SVE_3_Op_Pat<f64, op, nxv2i1, f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
4176 //===----------------------------------------------------------------------===//
4177 // SVE Floating Point Compare - Vectors Group
4178 //===----------------------------------------------------------------------===//
4180 class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
4182 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
4183 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
4190 let Inst{31-24} = 0b01100101;
4191 let Inst{23-22} = sz;
4193 let Inst{20-16} = Zm;
4194 let Inst{15} = opc{2};
4196 let Inst{13} = opc{1};
4197 let Inst{12-10} = Pg;
4199 let Inst{4} = opc{0};
4203 multiclass sve_fp_3op_p_pd<bits<3> opc, string asm, SDPatternOperator op> {
4204 def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
4205 def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
4206 def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
4208 def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
4209 def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
4210 def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
4214 //===----------------------------------------------------------------------===//
4215 // SVE Floating Point Compare - with Zero Group
4216 //===----------------------------------------------------------------------===//
4218 class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
4220 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn),
4221 asm, "\t$Pd, $Pg/z, $Zn, #0.0",
4227 let Inst{31-24} = 0b01100101;
4228 let Inst{23-22} = sz;
4229 let Inst{21-18} = 0b0100;
4230 let Inst{17-16} = opc{2-1};
4231 let Inst{15-13} = 0b001;
4232 let Inst{12-10} = Pg;
4234 let Inst{4} = opc{0};
4238 multiclass sve_fp_2op_p_pd<bits<3> opc, string asm> {
4239 def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
4240 def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
4241 def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
4245 //===----------------------------------------------------------------------===//
4246 //SVE Index Generation Group
4247 //===----------------------------------------------------------------------===//
4249 class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
4251 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
4252 asm, "\t$Zd, $imm5, $imm5b",
4253 "", []>, Sched<[]> {
4257 let Inst{31-24} = 0b00000100;
4258 let Inst{23-22} = sz8_64;
4260 let Inst{20-16} = imm5b;
4261 let Inst{15-10} = 0b010000;
4262 let Inst{9-5} = imm5;
4266 multiclass sve_int_index_ii<string asm> {
4267 def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>;
4268 def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>;
4269 def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
4270 def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
4273 class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty,
4274 RegisterClass srcRegType, Operand imm_ty>
4275 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
4276 asm, "\t$Zd, $imm5, $Rm",
4277 "", []>, Sched<[]> {
4281 let Inst{31-24} = 0b00000100;
4282 let Inst{23-22} = sz8_64;
4284 let Inst{20-16} = Rm;
4285 let Inst{15-10} = 0b010010;
4286 let Inst{9-5} = imm5;
4290 multiclass sve_int_index_ir<string asm> {
4291 def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>;
4292 def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>;
4293 def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
4294 def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
4297 class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty,
4298 RegisterClass srcRegType, Operand imm_ty>
4299 : I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5),
4300 asm, "\t$Zd, $Rn, $imm5",
4301 "", []>, Sched<[]> {
4305 let Inst{31-24} = 0b00000100;
4306 let Inst{23-22} = sz8_64;
4308 let Inst{20-16} = imm5;
4309 let Inst{15-10} = 0b010001;
4314 multiclass sve_int_index_ri<string asm> {
4315 def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>;
4316 def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>;
4317 def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
4318 def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
4321 class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty,
4322 RegisterClass srcRegType>
4323 : I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm),
4324 asm, "\t$Zd, $Rn, $Rm",
4325 "", []>, Sched<[]> {
4329 let Inst{31-24} = 0b00000100;
4330 let Inst{23-22} = sz8_64;
4332 let Inst{20-16} = Rm;
4333 let Inst{15-10} = 0b010011;
4338 multiclass sve_int_index_rr<string asm> {
4339 def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
4340 def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
4341 def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
4342 def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
4345 //===----------------------------------------------------------------------===//
4346 // SVE Bitwise Shift - Predicated Group
4347 //===----------------------------------------------------------------------===//
4348 class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
4349 ZPRRegOp zprty, Operand immtype,
4350 ElementSizeEnum size>
4351 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
4352 asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
4358 let Inst{31-24} = 0b00000100;
4359 let Inst{23-22} = tsz8_64{3-2};
4360 let Inst{21-20} = 0b00;
4361 let Inst{19-16} = opc;
4362 let Inst{15-13} = 0b100;
4363 let Inst{12-10} = Pg;
4364 let Inst{9-8} = tsz8_64{1-0};
4365 let Inst{7-5} = imm{2-0}; // imm3
4366 let Inst{4-0} = Zdn;
4368 let Constraints = "$Zdn = $_Zdn";
4369 let DestructiveInstType = Destructive;
4370 let ElementSize = size;
4373 multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> {
4374 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8,
4376 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16,
4378 let Inst{8} = imm{3};
4380 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32,
4382 let Inst{9-8} = imm{4-3};
4384 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64,
4386 let Inst{22} = imm{5};
4387 let Inst{9-8} = imm{4-3};
4391 multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm,
4392 SDPatternOperator op = null_frag> {
4393 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8,
4395 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16,
4397 let Inst{8} = imm{3};
4399 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32,
4401 let Inst{9-8} = imm{4-3};
4403 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64,
4405 let Inst{22} = imm{5};
4406 let Inst{9-8} = imm{4-3};
4409 def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i1, nxv16i8, i32, vecshiftR8, !cast<Instruction>(NAME # _B)>;
4410 def : SVE_3_Op_Imm_Pat<nxv8i16, op, nxv8i1, nxv8i16, i32, vecshiftR16, !cast<Instruction>(NAME # _H)>;
4411 def : SVE_3_Op_Imm_Pat<nxv4i32, op, nxv4i1, nxv4i32, i32, vecshiftR32, !cast<Instruction>(NAME # _S)>;
4412 def : SVE_3_Op_Imm_Pat<nxv2i64, op, nxv2i1, nxv2i64, i32, vecshiftR64, !cast<Instruction>(NAME # _D)>;
4415 class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
4416 string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
4417 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
4418 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
4424 let Inst{31-24} = 0b00000100;
4425 let Inst{23-22} = sz8_64;
4426 let Inst{21-20} = 0b01;
4427 let Inst{19} = wide;
4428 let Inst{18-16} = opc;
4429 let Inst{15-13} = 0b100;
4430 let Inst{12-10} = Pg;
4432 let Inst{4-0} = Zdn;
4434 let Constraints = "$Zdn = $_Zdn";
4435 let DestructiveInstType = Destructive;
4436 let ElementSize = zprty.ElementSize;
4439 multiclass sve_int_bin_pred_shift<bits<3> opc, string asm,
4440 SDPatternOperator op> {
4441 def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>;
4442 def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>;
4443 def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>;
4444 def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>;
4446 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
4447 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
4448 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
4449 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
4452 multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm,
4453 SDPatternOperator op> {
4454 def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>;
4455 def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>;
4456 def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>;
4458 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv2i64, !cast<Instruction>(NAME # _B)>;
4459 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv2i64, !cast<Instruction>(NAME # _H)>;
4460 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
4463 //===----------------------------------------------------------------------===//
4464 // SVE Shift - Unpredicated Group
4465 //===----------------------------------------------------------------------===//
4467 class sve_int_bin_cons_shift_wide<bits<2> sz8_64, bits<2> opc, string asm,
4469 : I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm),
4470 asm, "\t$Zd, $Zn, $Zm",
4476 let Inst{31-24} = 0b00000100;
4477 let Inst{23-22} = sz8_64;
4479 let Inst{20-16} = Zm;
4480 let Inst{15-12} = 0b1000;
4481 let Inst{11-10} = opc;
4486 multiclass sve_int_bin_cons_shift_wide<bits<2> opc, string asm> {
4487 def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>;
4488 def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>;
4489 def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>;
4492 class sve_int_bin_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
4493 ZPRRegOp zprty, Operand immtype>
4494 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
4495 asm, "\t$Zd, $Zn, $imm",
4496 "", []>, Sched<[]> {
4500 let Inst{31-24} = 0b00000100;
4501 let Inst{23-22} = tsz8_64{3-2};
4503 let Inst{20-19} = tsz8_64{1-0};
4504 let Inst{18-16} = imm{2-0}; // imm3
4505 let Inst{15-12} = 0b1001;
4506 let Inst{11-10} = opc;
4511 multiclass sve_int_bin_cons_shift_imm_left<bits<2> opc, string asm> {
4512 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
4513 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
4514 let Inst{19} = imm{3};
4516 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
4517 let Inst{20-19} = imm{4-3};
4519 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
4520 let Inst{22} = imm{5};
4521 let Inst{20-19} = imm{4-3};
4525 multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm> {
4526 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
4527 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
4528 let Inst{19} = imm{3};
4530 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
4531 let Inst{20-19} = imm{4-3};
4533 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
4534 let Inst{22} = imm{5};
4535 let Inst{20-19} = imm{4-3};
4538 //===----------------------------------------------------------------------===//
4539 // SVE Memory - Store Group
4540 //===----------------------------------------------------------------------===//
4542 class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
4543 RegisterOperand VecList>
4544 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
4545 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4552 let Inst{31-25} = 0b1110010;
4553 let Inst{24-23} = msz;
4554 let Inst{22-21} = esz;
4556 let Inst{19-16} = imm4;
4557 let Inst{15-13} = 0b111;
4558 let Inst{12-10} = Pg;
4565 multiclass sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
4566 RegisterOperand listty, ZPRRegOp zprty>
4568 def NAME : sve_mem_cst_si<msz, esz, asm, listty>;
4570 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4571 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
4572 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4573 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4574 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4575 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4578 class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
4579 string asm, Operand immtype>
4580 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
4581 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4588 let Inst{31-25} = 0b1110010;
4589 let Inst{24-23} = sz;
4590 let Inst{22-21} = nregs;
4592 let Inst{19-16} = imm4;
4593 let Inst{15-13} = 0b111;
4594 let Inst{12-10} = Pg;
4601 multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
4602 string asm, Operand immtype> {
4603 def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
4605 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4606 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4609 class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
4610 string asm, RegisterOperand gprty>
4611 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4612 asm, "\t$Zt, $Pg, [$Rn, $Rm]",
4619 let Inst{31-25} = 0b1110010;
4620 let Inst{24-23} = sz;
4621 let Inst{22-21} = nregs;
4622 let Inst{20-16} = Rm;
4623 let Inst{15-13} = 0b011;
4624 let Inst{12-10} = Pg;
4631 class sve_mem_cst_ss_base<bits<4> dtype, string asm,
4632 RegisterOperand listty, RegisterOperand gprty>
4633 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4634 asm, "\t$Zt, $Pg, [$Rn, $Rm]",
4641 let Inst{31-25} = 0b1110010;
4642 let Inst{24-21} = dtype;
4643 let Inst{20-16} = Rm;
4644 let Inst{15-13} = 0b010;
4645 let Inst{12-10} = Pg;
4652 multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
4653 RegisterOperand listty, ZPRRegOp zprty,
4654 RegisterOperand gprty> {
4655 def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
4657 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
4658 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4661 class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList>
4662 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
4663 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4670 let Inst{31-25} = 0b1110010;
4671 let Inst{24-23} = msz;
4672 let Inst{22-20} = 0b001;
4673 let Inst{19-16} = imm4;
4674 let Inst{15-13} = 0b111;
4675 let Inst{12-10} = Pg;
4682 multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty,
4684 def NAME : sve_mem_cstnt_si<msz, asm, listty>;
4686 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4687 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4688 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4689 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
4690 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4691 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4694 class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty,
4695 RegisterOperand gprty>
4696 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4697 asm, "\t$Zt, $Pg, [$Rn, $Rm]",
4704 let Inst{31-25} = 0b1110010;
4705 let Inst{24-23} = msz;
4706 let Inst{22-21} = 0b00;
4707 let Inst{20-16} = Rm;
4708 let Inst{15-13} = 0b011;
4709 let Inst{12-10} = Pg;
4716 multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
4717 ZPRRegOp zprty, RegisterOperand gprty> {
4718 def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
4720 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
4721 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4724 class sve2_mem_sstnt_vs_base<bits<3> opc, string asm,
4725 RegisterOperand listty, ZPRRegOp zprty>
4726 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
4727 asm, "\t$Zt, $Pg, [$Zn, $Rm]",
4734 let Inst{31-25} = 0b1110010;
4735 let Inst{24-22} = opc;
4737 let Inst{20-16} = Rm;
4738 let Inst{15-13} = 0b001;
4739 let Inst{12-10} = Pg;
4746 multiclass sve2_mem_sstnt_vs<bits<3> opc, string asm,
4747 RegisterOperand listty, ZPRRegOp zprty> {
4748 def _REAL : sve2_mem_sstnt_vs_base<opc, asm, listty, zprty>;
4750 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
4751 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
4752 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4753 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
4754 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4755 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
4758 class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
4759 RegisterOperand VecList, RegisterOperand zprext>
4760 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
4761 asm, "\t$Zt, $Pg, [$Rn, $Zm]",
4768 let Inst{31-25} = 0b1110010;
4769 let Inst{24-22} = opc;
4770 let Inst{21} = scaled;
4771 let Inst{20-16} = Zm;
4775 let Inst{12-10} = Pg;
4782 multiclass sve_mem_32b_sst_sv_32_scaled<bits<3> opc, string asm,
4783 SDPatternOperator sxtw_op,
4784 SDPatternOperator uxtw_op,
4785 RegisterOperand sxtw_opnd,
4786 RegisterOperand uxtw_opnd,
4788 def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, Z_s, uxtw_opnd>;
4789 def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, Z_s, sxtw_opnd>;
4791 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4792 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
4793 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4794 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
4796 def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
4797 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4798 def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
4799 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4802 multiclass sve_mem_64b_sst_sv_32_scaled<bits<3> opc, string asm,
4803 SDPatternOperator sxtw_op,
4804 SDPatternOperator uxtw_op,
4805 RegisterOperand sxtw_opnd,
4806 RegisterOperand uxtw_opnd,
4808 def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, Z_d, uxtw_opnd>;
4809 def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, Z_d, sxtw_opnd>;
4811 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4812 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
4813 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4814 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
4816 def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
4817 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4818 def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
4819 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4822 multiclass sve_mem_64b_sst_sv_32_unscaled<bits<3> opc, string asm,
4823 SDPatternOperator sxtw_op,
4824 SDPatternOperator uxtw_op,
4825 RegisterOperand sxtw_opnd,
4826 RegisterOperand uxtw_opnd,
4828 def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, Z_d, uxtw_opnd>;
4829 def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, Z_d, sxtw_opnd>;
4831 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4832 (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
4833 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4834 (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
4836 def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
4837 (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4838 def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
4839 (!cast<Instruction>(NAME # _SXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4842 multiclass sve_mem_32b_sst_sv_32_unscaled<bits<3> opc, string asm,
4843 SDPatternOperator sxtw_op,
4844 SDPatternOperator uxtw_op,
4845 RegisterOperand sxtw_opnd,
4846 RegisterOperand uxtw_opnd,
4848 def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, Z_s, uxtw_opnd>;
4849 def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, Z_s, sxtw_opnd>;
4851 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4852 (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
4853 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4854 (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
4856 def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
4857 (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4858 def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
4859 (!cast<Instruction>(NAME # _SXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4862 class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm,
4863 RegisterOperand zprext>
4864 : I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
4865 asm, "\t$Zt, $Pg, [$Rn, $Zm]",
4872 let Inst{31-25} = 0b1110010;
4873 let Inst{24-23} = msz;
4875 let Inst{21} = scaled;
4876 let Inst{20-16} = Zm;
4877 let Inst{15-13} = 0b101;
4878 let Inst{12-10} = Pg;
4885 multiclass sve_mem_sst_sv_64_scaled<bits<2> msz, string asm,
4886 SDPatternOperator op,
4887 RegisterOperand zprext,
4889 def _SCALED_REAL : sve_mem_sst_sv2<msz, 1, asm, zprext>;
4891 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4892 (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
4894 def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt),
4895 (!cast<Instruction>(NAME # _SCALED_REAL) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
4898 multiclass sve_mem_sst_sv_64_unscaled<bits<2> msz, string asm,
4899 SDPatternOperator op,
4901 def _REAL : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>;
4903 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4904 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
4906 def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
4907 (!cast<Instruction>(NAME # _REAL) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
4910 class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty,
4911 RegisterOperand VecList, Operand imm_ty>
4912 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5),
4913 asm, "\t$Zt, $Pg, [$Zn, $imm5]",
4920 let Inst{31-25} = 0b1110010;
4921 let Inst{24-23} = opc{2-1};
4923 let Inst{21} = opc{0};
4924 let Inst{20-16} = imm5;
4925 let Inst{15-13} = 0b101;
4926 let Inst{12-10} = Pg;
4933 multiclass sve_mem_32b_sst_vi_ptrs<bits<3> opc, string asm,
4935 SDPatternOperator op,
4937 def _IMM : sve_mem_sst_vi<opc, asm, ZPR32, Z_s, imm_ty>;
4939 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4940 (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
4941 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
4942 (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
4943 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4944 (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
4946 def : Pat<(op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt),
4947 (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
4950 multiclass sve_mem_64b_sst_vi_ptrs<bits<3> opc, string asm,
4952 SDPatternOperator op,
4954 def _IMM : sve_mem_sst_vi<opc, asm, ZPR64, Z_d, imm_ty>;
4956 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4957 (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
4958 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
4959 (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
4960 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4961 (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
4963 def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
4964 (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
4967 class sve_mem_z_spill<string asm>
4968 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
4969 asm, "\t$Zt, [$Rn, $imm9, mul vl]",
4975 let Inst{31-22} = 0b1110010110;
4976 let Inst{21-16} = imm9{8-3};
4977 let Inst{15-13} = 0b010;
4978 let Inst{12-10} = imm9{2-0};
4985 multiclass sve_mem_z_spill<string asm> {
4986 def NAME : sve_mem_z_spill<asm>;
4988 def : InstAlias<asm # "\t$Zt, [$Rn]",
4989 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
4992 class sve_mem_p_spill<string asm>
4993 : I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
4994 asm, "\t$Pt, [$Rn, $imm9, mul vl]",
5000 let Inst{31-22} = 0b1110010110;
5001 let Inst{21-16} = imm9{8-3};
5002 let Inst{15-13} = 0b000;
5003 let Inst{12-10} = imm9{2-0};
5011 multiclass sve_mem_p_spill<string asm> {
5012 def NAME : sve_mem_p_spill<asm>;
5014 def : InstAlias<asm # "\t$Pt, [$Rn]",
5015 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
5018 //===----------------------------------------------------------------------===//
5019 // SVE Permute - Predicates Group
5020 //===----------------------------------------------------------------------===//
5022 class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
5024 : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
5025 asm, "\t$Pd, $Pn, $Pm",
5031 let Inst{31-24} = 0b00000101;
5032 let Inst{23-22} = sz8_64;
5033 let Inst{21-20} = 0b10;
5034 let Inst{19-16} = Pm;
5035 let Inst{15-13} = 0b010;
5036 let Inst{12-10} = opc;
5043 multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm,
5044 SDPatternOperator op> {
5045 def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
5046 def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
5047 def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
5048 def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
5050 def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
5051 def : SVE_2_Op_Pat<nxv8i1, op, nxv8i1, nxv8i1, !cast<Instruction>(NAME # _H)>;
5052 def : SVE_2_Op_Pat<nxv4i1, op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>;
5053 def : SVE_2_Op_Pat<nxv2i1, op, nxv2i1, nxv2i1, !cast<Instruction>(NAME # _D)>;
5056 class sve_int_perm_punpk<bit opc, string asm>
5057 : I<(outs PPR16:$Pd), (ins PPR8:$Pn),
5063 let Inst{31-17} = 0b000001010011000;
5065 let Inst{15-9} = 0b0100000;
5071 multiclass sve_int_perm_punpk<bit opc, string asm, SDPatternOperator op> {
5072 def NAME : sve_int_perm_punpk<opc, asm>;
5074 def : SVE_1_Op_Pat<nxv8i1, op, nxv16i1, !cast<Instruction>(NAME)>;
5075 def : SVE_1_Op_Pat<nxv4i1, op, nxv8i1, !cast<Instruction>(NAME)>;
5076 def : SVE_1_Op_Pat<nxv2i1, op, nxv4i1, !cast<Instruction>(NAME)>;
5079 class sve_int_rdffr_pred<bit s, string asm>
5080 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg),
5081 asm, "\t$Pd, $Pg/z",
5086 let Inst{31-23} = 0b001001010;
5088 let Inst{21-9} = 0b0110001111000;
5093 let Defs = !if(!eq (s, 1), [NZCV], []);
5097 class sve_int_rdffr_unpred<string asm> : I<
5098 (outs PPR8:$Pd), (ins),
5103 let Inst{31-4} = 0b0010010100011001111100000000;
5109 class sve_int_wrffr<string asm>
5110 : I<(outs), (ins PPR8:$Pn),
5115 let Inst{31-9} = 0b00100101001010001001000;
5117 let Inst{4-0} = 0b00000;
5119 let hasSideEffects = 1;
5123 class sve_int_setffr<string asm>
5128 let Inst{31-0} = 0b00100101001011001001000000000000;
5130 let hasSideEffects = 1;
5134 //===----------------------------------------------------------------------===//
5135 // SVE Permute Vector - Predicated Group
5136 //===----------------------------------------------------------------------===//
5138 class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm,
5139 ZPRRegOp zprty, RegisterClass rt>
5140 : I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm),
5141 asm, "\t$Rdn, $Pg, $_Rdn, $Zm",
5147 let Inst{31-24} = 0b00000101;
5148 let Inst{23-22} = sz8_64;
5149 let Inst{21-17} = 0b11000;
5151 let Inst{15-13} = 0b101;
5152 let Inst{12-10} = Pg;
5154 let Inst{4-0} = Rdn;
5156 let Constraints = "$Rdn = $_Rdn";
5159 multiclass sve_int_perm_clast_rz<bit ab, string asm, SDPatternOperator op> {
5160 def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>;
5161 def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>;
5162 def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>;
5163 def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>;
5165 def : SVE_3_Op_Pat<i32, op, nxv16i1, i32, nxv16i8, !cast<Instruction>(NAME # _B)>;
5166 def : SVE_3_Op_Pat<i32, op, nxv8i1, i32, nxv8i16, !cast<Instruction>(NAME # _H)>;
5167 def : SVE_3_Op_Pat<i32, op, nxv4i1, i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
5168 def : SVE_3_Op_Pat<i64, op, nxv2i1, i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
5171 class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm,
5172 ZPRRegOp zprty, RegisterClass rt>
5173 : I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm),
5174 asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
5180 let Inst{31-24} = 0b00000101;
5181 let Inst{23-22} = sz8_64;
5182 let Inst{21-17} = 0b10101;
5184 let Inst{15-13} = 0b100;
5185 let Inst{12-10} = Pg;
5187 let Inst{4-0} = Vdn;
5189 let Constraints = "$Vdn = $_Vdn";
5192 multiclass sve_int_perm_clast_vz<bit ab, string asm, SDPatternOperator op> {
5193 def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>;
5194 def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>;
5195 def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>;
5196 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>;
5198 def : SVE_3_Op_Pat<f16, op, nxv8i1, f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
5199 def : SVE_3_Op_Pat<f32, op, nxv4i1, f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
5200 def : SVE_3_Op_Pat<f64, op, nxv2i1, f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
5203 class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm,
5205 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
5206 asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
5212 let Inst{31-24} = 0b00000101;
5213 let Inst{23-22} = sz8_64;
5214 let Inst{21-17} = 0b10100;
5216 let Inst{15-13} = 0b100;
5217 let Inst{12-10} = Pg;
5219 let Inst{4-0} = Zdn;
5221 let Constraints = "$Zdn = $_Zdn";
5222 let DestructiveInstType = Destructive;
5223 let ElementSize = ElementSizeNone;
5226 multiclass sve_int_perm_clast_zz<bit ab, string asm, SDPatternOperator op> {
5227 def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>;
5228 def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>;
5229 def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>;
5230 def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>;
5232 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
5233 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
5234 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
5235 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
5237 def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
5238 def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
5239 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
5242 class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm,
5243 ZPRRegOp zprty, RegisterClass resultRegType>
5244 : I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn),
5245 asm, "\t$Rd, $Pg, $Zn",
5251 let Inst{31-24} = 0b00000101;
5252 let Inst{23-22} = sz8_64;
5253 let Inst{21-17} = 0b10000;
5255 let Inst{15-13} = 0b101;
5256 let Inst{12-10} = Pg;
5261 multiclass sve_int_perm_last_r<bit ab, string asm, SDPatternOperator op> {
5262 def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>;
5263 def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>;
5264 def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>;
5265 def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>;
5267 def : SVE_2_Op_Pat<i32, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
5268 def : SVE_2_Op_Pat<i32, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
5269 def : SVE_2_Op_Pat<i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
5270 def : SVE_2_Op_Pat<i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
5273 class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm,
5274 ZPRRegOp zprty, RegisterClass dstRegtype>
5275 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
5276 asm, "\t$Vd, $Pg, $Zn",
5282 let Inst{31-24} = 0b00000101;
5283 let Inst{23-22} = sz8_64;
5284 let Inst{21-17} = 0b10001;
5286 let Inst{15-13} = 0b100;
5287 let Inst{12-10} = Pg;
5292 multiclass sve_int_perm_last_v<bit ab, string asm, SDPatternOperator op> {
5293 def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>;
5294 def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>;
5295 def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>;
5296 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>;
5298 def : SVE_2_Op_Pat<f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
5299 def : SVE_2_Op_Pat<f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
5300 def : SVE_2_Op_Pat<f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
5301 def : SVE_2_Op_Pat<f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
5304 class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty>
5305 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
5306 asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
5312 let Inst{31-24} = 0b00000101;
5313 let Inst{23-22} = sz8_64;
5314 let Inst{21-13} = 0b101100100;
5315 let Inst{12-10} = Pg;
5317 let Inst{4-0} = Zdn;
5319 let Constraints = "$Zdn = $_Zdn";
5320 let DestructiveInstType = Destructive;
5321 let ElementSize = ElementSizeNone;
5324 multiclass sve_int_perm_splice<string asm, SDPatternOperator op> {
5325 def _B : sve_int_perm_splice<0b00, asm, ZPR8>;
5326 def _H : sve_int_perm_splice<0b01, asm, ZPR16>;
5327 def _S : sve_int_perm_splice<0b10, asm, ZPR32>;
5328 def _D : sve_int_perm_splice<0b11, asm, ZPR64>;
5330 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
5331 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
5332 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
5333 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
5335 def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
5336 def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
5337 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
5340 class sve2_int_perm_splice_cons<bits<2> sz8_64, string asm,
5341 ZPRRegOp zprty, RegisterOperand VecList>
5342 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn),
5343 asm, "\t$Zd, $Pg, $Zn",
5349 let Inst{31-24} = 0b00000101;
5350 let Inst{23-22} = sz8_64;
5351 let Inst{21-13} = 0b101101100;
5352 let Inst{12-10} = Pg;
5357 multiclass sve2_int_perm_splice_cons<string asm> {
5358 def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>;
5359 def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>;
5360 def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>;
5361 def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>;
5364 class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm,
5366 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
5367 asm, "\t$Zd, $Pg/m, $Zn",
5373 let Inst{31-24} = 0b00000101;
5374 let Inst{23-22} = sz8_64;
5375 let Inst{21-18} = 0b1001;
5376 let Inst{17-16} = opc;
5377 let Inst{15-13} = 0b100;
5378 let Inst{12-10} = Pg;
5382 let Constraints = "$Zd = $_Zd";
5383 let DestructiveInstType = Destructive;
5384 let ElementSize = zprty.ElementSize;
5387 multiclass sve_int_perm_rev_rbit<string asm, SDPatternOperator op> {
5388 def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>;
5389 def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>;
5390 def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>;
5391 def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>;
5393 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
5394 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
5395 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
5396 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
5399 multiclass sve_int_perm_rev_revb<string asm,
5400 SDPatternOperator int_op,
5401 SDPatternOperator ir_op> {
5402 def _H : sve_int_perm_rev<0b01, 0b00, asm, ZPR16>;
5403 def _S : sve_int_perm_rev<0b10, 0b00, asm, ZPR32>;
5404 def _D : sve_int_perm_rev<0b11, 0b00, asm, ZPR64>;
5406 def : SVE_3_Op_Pat<nxv8i16, int_op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
5407 def : SVE_3_Op_Pat<nxv4i32, int_op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
5408 def : SVE_3_Op_Pat<nxv2i64, int_op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
5410 def : SVE_1_Op_AllActive_Pat<nxv8i16, ir_op, nxv8i16, !cast<Instruction>(NAME # _H), PTRUE_H>;
5411 def : SVE_1_Op_AllActive_Pat<nxv4i32, ir_op, nxv4i32, !cast<Instruction>(NAME # _S), PTRUE_S>;
5412 def : SVE_1_Op_AllActive_Pat<nxv2i64, ir_op, nxv2i64, !cast<Instruction>(NAME # _D), PTRUE_D>;
5415 multiclass sve_int_perm_rev_revh<string asm, SDPatternOperator op> {
5416 def _S : sve_int_perm_rev<0b10, 0b01, asm, ZPR32>;
5417 def _D : sve_int_perm_rev<0b11, 0b01, asm, ZPR64>;
5419 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
5420 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
5423 multiclass sve_int_perm_rev_revw<string asm, SDPatternOperator op> {
5424 def _D : sve_int_perm_rev<0b11, 0b10, asm, ZPR64>;
5426 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
5429 class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
5430 RegisterClass srcRegType>
5431 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
5432 asm, "\t$Zd, $Pg/m, $Rn",
5438 let Inst{31-24} = 0b00000101;
5439 let Inst{23-22} = sz8_64;
5440 let Inst{21-13} = 0b101000101;
5441 let Inst{12-10} = Pg;
5445 let Constraints = "$Zd = $_Zd";
5446 let DestructiveInstType = Destructive;
5447 let ElementSize = zprty.ElementSize;
5450 multiclass sve_int_perm_cpy_r<string asm> {
5451 def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>;
5452 def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>;
5453 def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>;
5454 def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
5456 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
5457 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
5458 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
5459 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
5460 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
5461 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
5462 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
5463 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>;
5466 class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty,
5467 RegisterClass srcRegtype>
5468 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
5469 asm, "\t$Zd, $Pg/m, $Vn",
5475 let Inst{31-24} = 0b00000101;
5476 let Inst{23-22} = sz8_64;
5477 let Inst{21-13} = 0b100000100;
5478 let Inst{12-10} = Pg;
5482 let Constraints = "$Zd = $_Zd";
5483 let DestructiveInstType = Destructive;
5484 let ElementSize = zprty.ElementSize;
5487 multiclass sve_int_perm_cpy_v<string asm> {
5488 def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
5489 def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
5490 def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>;
5491 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
5493 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5494 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
5495 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5496 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
5497 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5498 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
5499 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5500 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
5503 class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
5504 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
5505 asm, "\t$Zd, $Pg, $Zn",
5511 let Inst{31-23} = 0b000001011;
5513 let Inst{21-13} = 0b100001100;
5514 let Inst{12-10} = Pg;
5519 multiclass sve_int_perm_compact<string asm, SDPatternOperator op> {
5520 def _S : sve_int_perm_compact<0b0, asm, ZPR32>;
5521 def _D : sve_int_perm_compact<0b1, asm, ZPR64>;
5523 def : SVE_2_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
5524 def : SVE_2_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
5525 def : SVE_2_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
5526 def : SVE_2_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
5530 //===----------------------------------------------------------------------===//
5531 // SVE Memory - Contiguous Load Group
5532 //===----------------------------------------------------------------------===//
5534 class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
5535 RegisterOperand VecList>
5536 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
5537 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
5544 let Inst{31-25} = 0b1010010;
5545 let Inst{24-21} = dtype;
5547 let Inst{19-16} = imm4;
5548 let Inst{15-13} = 0b101;
5549 let Inst{12-10} = Pg;
5554 let Uses = !if(!eq(nf, 1), [FFR], []);
5555 let Defs = !if(!eq(nf, 1), [FFR], []);
5558 multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
5559 RegisterOperand listty, ZPRRegOp zprty> {
5560 def "" : sve_mem_cld_si_base<dtype, nf, asm, listty>;
5562 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5563 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
5564 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
5565 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
5566 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5567 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5570 multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
5572 : sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
5574 class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList>
5575 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
5576 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
5583 let Inst{31-25} = 0b1010010;
5584 let Inst{24-23} = msz;
5585 let Inst{22-20} = 0b000;
5586 let Inst{19-16} = imm4;
5587 let Inst{15-13} = 0b111;
5588 let Inst{12-10} = Pg;
5595 multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty,
5597 def NAME : sve_mem_cldnt_si_base<msz, asm, listty>;
5599 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5600 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
5601 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
5602 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
5603 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5604 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5607 class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList,
5608 RegisterOperand gprty>
5609 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5610 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
5617 let Inst{31-25} = 0b1010010;
5618 let Inst{24-23} = msz;
5619 let Inst{22-21} = 0b00;
5620 let Inst{20-16} = Rm;
5621 let Inst{15-13} = 0b110;
5622 let Inst{12-10} = Pg;
5629 multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty,
5630 ZPRRegOp zprty, RegisterOperand gprty> {
5631 def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>;
5633 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
5634 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
5637 class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList>
5638 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
5639 asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
5644 let Inst{31-25} = 0b1010010;
5645 let Inst{24-23} = sz;
5646 let Inst{22-20} = 0;
5647 let Inst{19-16} = imm4;
5648 let Inst{15-13} = 0b001;
5649 let Inst{12-10} = Pg;
5656 multiclass sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand listty,
5658 def NAME : sve_mem_ldqr_si<sz, asm, listty>;
5659 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5660 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5661 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5662 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
5663 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
5664 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
5667 class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList,
5668 RegisterOperand gprty>
5669 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5670 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
5675 let Inst{31-25} = 0b1010010;
5676 let Inst{24-23} = sz;
5677 let Inst{22-21} = 0;
5678 let Inst{20-16} = Rm;
5679 let Inst{15-13} = 0;
5680 let Inst{12-10} = Pg;
5687 multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty,
5688 ZPRRegOp zprty, RegisterOperand gprty> {
5689 def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>;
5691 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
5692 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
5695 class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
5696 RegisterOperand VecList, Operand immtype>
5697 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
5698 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
5705 let Inst{31-25} = 0b1000010;
5706 let Inst{24-23} = dtypeh;
5708 let Inst{21-16} = imm6;
5710 let Inst{14-13} = dtypel;
5711 let Inst{12-10} = Pg;
5718 multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
5719 RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> {
5720 def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>;
5722 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5723 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
5724 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]",
5725 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
5726 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5727 (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5730 class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
5731 RegisterOperand VecList>
5732 : I<(outs VecList:$Zt), iops,
5733 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
5740 let Inst{31-25} = 0b1010010;
5741 let Inst{24-21} = dtype;
5742 let Inst{20-16} = Rm;
5743 let Inst{15-14} = 0b01;
5745 let Inst{12-10} = Pg;
5750 let Uses = !if(!eq(ff, 1), [FFR], []);
5751 let Defs = !if(!eq(ff, 1), [FFR], []);
5754 multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
5755 ZPRRegOp zprty, RegisterOperand gprty> {
5756 def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5759 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
5760 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
5763 multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty,
5764 ZPRRegOp zprty, RegisterOperand gprty> {
5765 def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5768 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
5769 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
5771 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5772 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
5774 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5775 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
5778 multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty,
5780 : sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>;
5782 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
5783 string asm, Operand immtype>
5784 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
5785 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
5792 let Inst{31-25} = 0b1010010;
5793 let Inst{24-23} = sz;
5794 let Inst{22-21} = nregs;
5796 let Inst{19-16} = imm4;
5797 let Inst{15-13} = 0b111;
5798 let Inst{12-10} = Pg;
5805 multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
5806 string asm, Operand immtype> {
5807 def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
5809 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
5810 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5813 class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
5814 string asm, RegisterOperand gprty>
5815 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5816 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
5823 let Inst{31-25} = 0b1010010;
5824 let Inst{24-23} = sz;
5825 let Inst{22-21} = nregs;
5826 let Inst{20-16} = Rm;
5827 let Inst{15-13} = 0b110;
5828 let Inst{12-10} = Pg;
5835 //===----------------------------------------------------------------------===//
5836 // SVE Memory - 32-bit Gather and Unsized Contiguous Group
5837 //===----------------------------------------------------------------------===//
5839 // bit xs is '1' if offsets are signed
5840 // bit scaled is '1' if the offsets are scaled
5841 class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
5842 RegisterOperand zprext>
5843 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
5844 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
5851 let Inst{31-25} = 0b1000010;
5852 let Inst{24-23} = opc{3-2};
5854 let Inst{21} = scaled;
5855 let Inst{20-16} = Zm;
5857 let Inst{14-13} = opc{1-0};
5858 let Inst{12-10} = Pg;
5863 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
5864 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
5867 multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm,
5868 SDPatternOperator sxtw_op,
5869 SDPatternOperator uxtw_op,
5870 RegisterOperand sxtw_opnd,
5871 RegisterOperand uxtw_opnd,
5873 def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>;
5874 def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
5876 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5877 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
5878 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5879 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
5881 def : Pat<(nxv4i32 (uxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$indices), vt)),
5882 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
5883 def : Pat<(nxv4i32 (sxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$indices), vt)),
5884 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
5887 multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
5888 SDPatternOperator sxtw_op,
5889 SDPatternOperator uxtw_op,
5890 RegisterOperand sxtw_opnd,
5891 RegisterOperand uxtw_opnd,
5893 def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>;
5894 def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
5896 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5897 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
5898 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5899 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
5901 def : Pat<(nxv4i32 (uxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt)),
5902 (!cast<Instruction>(NAME # _UXTW_REAL) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
5903 def : Pat<(nxv4i32 (sxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt)),
5904 (!cast<Instruction>(NAME # _SXTW_REAL) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
5908 class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
5909 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
5910 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
5917 let Inst{31-25} = 0b1000010;
5918 let Inst{24-23} = opc{3-2};
5919 let Inst{22-21} = 0b01;
5920 let Inst{20-16} = imm5;
5922 let Inst{14-13} = opc{1-0};
5923 let Inst{12-10} = Pg;
5928 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
5929 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
5932 multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty,
5933 SDPatternOperator op, ValueType vt> {
5934 def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
5936 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5937 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
5938 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
5939 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
5940 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5941 (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
5943 def : Pat<(nxv4i32 (op (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt)),
5944 (!cast<Instruction>(NAME # _IMM_REAL) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
5947 class sve_mem_prfm_si<bits<2> msz, string asm>
5948 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
5949 asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]",
5956 let Inst{31-22} = 0b1000010111;
5957 let Inst{21-16} = imm6;
5959 let Inst{14-13} = msz;
5960 let Inst{12-10} = Pg;
5963 let Inst{3-0} = prfop;
5965 let hasSideEffects = 1;
5968 multiclass sve_mem_prfm_si<bits<2> msz, string asm> {
5969 def NAME : sve_mem_prfm_si<msz, asm>;
5971 def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]",
5972 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5975 class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty>
5976 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5977 asm, "\t$prfop, $Pg, [$Rn, $Rm]",
5984 let Inst{31-25} = 0b1000010;
5985 let Inst{24-23} = opc{2-1};
5986 let Inst{22-21} = 0b00;
5987 let Inst{20-16} = Rm;
5989 let Inst{14} = opc{0};
5991 let Inst{12-10} = Pg;
5994 let Inst{3-0} = prfop;
5996 let hasSideEffects = 1;
5999 class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
6000 RegisterOperand zprext>
6001 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
6002 asm, "\t$prfop, $Pg, [$Rn, $Zm]",
6009 let Inst{31-23} = 0b100001000;
6012 let Inst{20-16} = Zm;
6014 let Inst{14-13} = msz;
6015 let Inst{12-10} = Pg;
6018 let Inst{3-0} = prfop;
6020 let hasSideEffects = 1;
6023 multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm,
6024 RegisterOperand sxtw_opnd,
6025 RegisterOperand uxtw_opnd> {
6026 def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
6027 def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
6030 class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
6031 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
6032 asm, "\t$prfop, $Pg, [$Zn, $imm5]",
6039 let Inst{31-25} = 0b1000010;
6040 let Inst{24-23} = msz;
6041 let Inst{22-21} = 0b00;
6042 let Inst{20-16} = imm5;
6043 let Inst{15-13} = 0b111;
6044 let Inst{12-10} = Pg;
6047 let Inst{3-0} = prfop;
6050 multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
6051 def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
6053 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
6054 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
6057 class sve_mem_z_fill<string asm>
6058 : I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9),
6059 asm, "\t$Zt, [$Rn, $imm9, mul vl]",
6065 let Inst{31-22} = 0b1000010110;
6066 let Inst{21-16} = imm9{8-3};
6067 let Inst{15-13} = 0b010;
6068 let Inst{12-10} = imm9{2-0};
6075 multiclass sve_mem_z_fill<string asm> {
6076 def NAME : sve_mem_z_fill<asm>;
6078 def : InstAlias<asm # "\t$Zt, [$Rn]",
6079 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
6082 class sve_mem_p_fill<string asm>
6083 : I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
6084 asm, "\t$Pt, [$Rn, $imm9, mul vl]",
6090 let Inst{31-22} = 0b1000010110;
6091 let Inst{21-16} = imm9{8-3};
6092 let Inst{15-13} = 0b000;
6093 let Inst{12-10} = imm9{2-0};
6101 multiclass sve_mem_p_fill<string asm> {
6102 def NAME : sve_mem_p_fill<asm>;
6104 def : InstAlias<asm # "\t$Pt, [$Rn]",
6105 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
6108 class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,
6109 RegisterOperand VecList>
6110 : I<(outs VecList:$Zt), iops,
6111 asm, "\t$Zt, $Pg/z, [$Zn, $Rm]",
6119 let Inst{30} = opc{4};
6120 let Inst{29-25} = 0b00010;
6121 let Inst{24-23} = opc{3-2};
6122 let Inst{22-21} = 0b00;
6123 let Inst{20-16} = Rm;
6125 let Inst{14-13} = opc{1-0};
6126 let Inst{12-10} = Pg;
6133 multiclass sve2_mem_gldnt_vs<bits<5> opc, string asm,
6134 RegisterOperand listty, ZPRRegOp zprty> {
6135 def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
6138 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
6139 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
6140 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
6141 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
6142 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
6143 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
6146 //===----------------------------------------------------------------------===//
6147 // SVE Memory - 64-bit Gather Group
6148 //===----------------------------------------------------------------------===//
6150 // bit xs is '1' if offsets are signed
6151 // bit scaled is '1' if the offsets are scaled
6152 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
6153 class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
6154 RegisterOperand zprext>
6155 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
6156 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
6163 let Inst{31-25} = 0b1100010;
6164 let Inst{24-23} = opc{3-2};
6166 let Inst{21} = scaled;
6167 let Inst{20-16} = Zm;
6169 let Inst{14-13} = opc{1-0};
6170 let Inst{12-10} = Pg;
6175 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
6176 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
6179 multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm,
6180 SDPatternOperator sxtw_op,
6181 SDPatternOperator uxtw_op,
6182 RegisterOperand sxtw_opnd,
6183 RegisterOperand uxtw_opnd,
6185 def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>;
6186 def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
6188 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
6189 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
6190 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
6191 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
6193 def : Pat<(nxv2i64 (uxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
6194 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
6195 def : Pat<(nxv2i64 (sxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
6196 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
6199 multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
6200 SDPatternOperator sxtw_op,
6201 SDPatternOperator uxtw_op,
6202 RegisterOperand sxtw_opnd,
6203 RegisterOperand uxtw_opnd,
6205 def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>;
6206 def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
6208 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
6209 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
6210 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
6211 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
6213 def : Pat<(nxv2i64 (uxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
6214 (!cast<Instruction>(NAME # _UXTW_REAL) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
6215 def : Pat<(nxv2i64 (sxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
6216 (!cast<Instruction>(NAME # _SXTW_REAL) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
6219 multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
6220 SDPatternOperator op,
6221 RegisterOperand zprext, ValueType vt> {
6222 def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
6224 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
6225 (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
6227 def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
6228 (!cast<Instruction>(NAME # _SCALED_REAL) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
6231 multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm,
6232 SDPatternOperator op, ValueType vt> {
6233 def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
6235 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
6236 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
6238 def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
6239 (!cast<Instruction>(NAME # _REAL) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
6242 class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
6243 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
6244 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
6251 let Inst{31-25} = 0b1100010;
6252 let Inst{24-23} = opc{3-2};
6253 let Inst{22-21} = 0b01;
6254 let Inst{20-16} = imm5;
6256 let Inst{14-13} = opc{1-0};
6257 let Inst{12-10} = Pg;
6262 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
6263 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
6266 multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty,
6267 SDPatternOperator op, ValueType vt> {
6268 def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
6270 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
6271 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
6272 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
6273 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
6274 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
6275 (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
6277 def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt)),
6278 (!cast<Instruction>(NAME # _IMM_REAL) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
6281 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
6282 class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
6283 RegisterOperand zprext>
6284 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
6285 asm, "\t$prfop, $Pg, [$Rn, $Zm]",
6292 let Inst{31-23} = 0b110001000;
6295 let Inst{20-16} = Zm;
6297 let Inst{14-13} = msz;
6298 let Inst{12-10} = Pg;
6301 let Inst{3-0} = prfop;
6303 let hasSideEffects = 1;
6306 multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm,
6307 RegisterOperand sxtw_opnd,
6308 RegisterOperand uxtw_opnd> {
6309 def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
6310 def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
6313 multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm,
6314 RegisterOperand zprext> {
6315 def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
6319 class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
6320 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
6321 asm, "\t$prfop, $Pg, [$Zn, $imm5]",
6328 let Inst{31-25} = 0b1100010;
6329 let Inst{24-23} = msz;
6330 let Inst{22-21} = 0b00;
6331 let Inst{20-16} = imm5;
6332 let Inst{15-13} = 0b111;
6333 let Inst{12-10} = Pg;
6336 let Inst{3-0} = prfop;
6338 let hasSideEffects = 1;
6341 multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
6342 def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
6344 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
6345 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
6349 //===----------------------------------------------------------------------===//
6350 // SVE Compute Vector Address Group
6351 //===----------------------------------------------------------------------===//
6353 class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm,
6354 ZPRRegOp zprty, RegisterOperand zprext>
6355 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm),
6356 asm, "\t$Zd, [$Zn, $Zm]",
6362 let Inst{31-24} = 0b00000100;
6363 let Inst{23-22} = opc;
6365 let Inst{20-16} = Zm;
6366 let Inst{15-12} = 0b1010;
6367 let Inst{11-10} = msz;
6372 multiclass sve_int_bin_cons_misc_0_a_uxtw<bits<2> opc, string asm> {
6373 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtUXTW8>;
6374 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtUXTW16>;
6375 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtUXTW32>;
6376 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtUXTW64>;
6379 multiclass sve_int_bin_cons_misc_0_a_sxtw<bits<2> opc, string asm> {
6380 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtSXTW8>;
6381 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtSXTW16>;
6382 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtSXTW32>;
6383 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtSXTW64>;
6386 multiclass sve_int_bin_cons_misc_0_a_32_lsl<bits<2> opc, string asm> {
6387 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR32, ZPR32ExtLSL8>;
6388 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR32, ZPR32ExtLSL16>;
6389 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR32, ZPR32ExtLSL32>;
6390 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR32, ZPR32ExtLSL64>;
6393 multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> {
6394 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtLSL8>;
6395 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtLSL16>;
6396 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>;
6397 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>;
6401 //===----------------------------------------------------------------------===//
6402 // SVE Integer Misc - Unpredicated Group
6403 //===----------------------------------------------------------------------===//
6405 class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty>
6406 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
6407 asm, "\t$Zd, $Zn, $Zm",
6413 let Inst{31-24} = 0b00000100;
6414 let Inst{23-22} = sz;
6416 let Inst{20-16} = Zm;
6417 let Inst{15-10} = 0b101100;
6422 multiclass sve_int_bin_cons_misc_0_b<string asm, SDPatternOperator op> {
6423 def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>;
6424 def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>;
6425 def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>;
6427 def : SVE_2_Op_Pat<nxv8f16, op, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>;
6428 def : SVE_2_Op_Pat<nxv4f32, op, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>;
6429 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
6432 class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty>
6433 : I<(outs zprty:$Zd), (ins zprty:$Zn),
6439 let Inst{31-24} = 0b00000100;
6440 let Inst{23-22} = opc{7-6};
6442 let Inst{20-16} = opc{5-1};
6443 let Inst{15-11} = 0b10111;
6444 let Inst{10} = opc{0};
6449 multiclass sve_int_bin_cons_misc_0_c_fexpa<string asm, SDPatternOperator op> {
6450 def _H : sve_int_bin_cons_misc_0_c<0b01000000, asm, ZPR16>;
6451 def _S : sve_int_bin_cons_misc_0_c<0b10000000, asm, ZPR32>;
6452 def _D : sve_int_bin_cons_misc_0_c<0b11000000, asm, ZPR64>;
6454 def : SVE_1_Op_Pat<nxv8f16, op, nxv8i16, !cast<Instruction>(NAME # _H)>;
6455 def : SVE_1_Op_Pat<nxv4f32, op, nxv4i32, !cast<Instruction>(NAME # _S)>;
6456 def : SVE_1_Op_Pat<nxv2f64, op, nxv2i64, !cast<Instruction>(NAME # _D)>;
6459 //===----------------------------------------------------------------------===//
6460 // SVE Integer Reduction Group
6461 //===----------------------------------------------------------------------===//
6463 class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
6464 ZPRRegOp zprty, RegisterClass regtype>
6465 : I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
6466 asm, "\t$Vd, $Pg, $Zn",
6472 let Inst{31-24} = 0b00000100;
6473 let Inst{23-22} = sz8_32;
6475 let Inst{20-19} = fmt;
6476 let Inst{18-16} = opc;
6477 let Inst{15-13} = 0b001;
6478 let Inst{12-10} = Pg;
6483 multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm, SDPatternOperator op> {
6484 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
6485 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
6486 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
6488 def : SVE_2_Op_Pat<i64, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
6489 def : SVE_2_Op_Pat<i64, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
6490 def : SVE_2_Op_Pat<i64, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
6493 multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm, SDPatternOperator op, SDPatternOperator opSaddv> {
6494 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
6495 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
6496 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
6497 def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>;
6499 def : SVE_2_Op_Pat<i64, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
6500 def : SVE_2_Op_Pat<i64, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
6501 def : SVE_2_Op_Pat<i64, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
6502 def : SVE_2_Op_Pat<i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
6503 def : SVE_2_Op_Pat<i64, opSaddv, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
6506 multiclass sve_int_reduce_1<bits<3> opc, string asm, SDPatternOperator op> {
6507 def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>;
6508 def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>;
6509 def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>;
6510 def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>;
6512 def : SVE_2_Op_Pat_Reduce_To_Neon<v16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B), bsub>;
6513 def : SVE_2_Op_Pat_Reduce_To_Neon<v8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H), hsub>;
6514 def : SVE_2_Op_Pat_Reduce_To_Neon<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S), ssub>;
6515 def : SVE_2_Op_Pat_Reduce_To_Neon<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D), dsub>;
6518 multiclass sve_int_reduce_2<bits<3> opc, string asm, SDPatternOperator op> {
6519 def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>;
6520 def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>;
6521 def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>;
6522 def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>;
6524 def : SVE_2_Op_Pat_Reduce_To_Neon<v16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B), bsub>;
6525 def : SVE_2_Op_Pat_Reduce_To_Neon<v8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H), hsub>;
6526 def : SVE_2_Op_Pat_Reduce_To_Neon<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S), ssub>;
6527 def : SVE_2_Op_Pat_Reduce_To_Neon<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D), dsub>;
6530 class sve_int_movprfx_pred<bits<2> sz8_32, bits<3> opc, string asm,
6531 ZPRRegOp zprty, string pg_suffix, dag iops>
6532 : I<(outs zprty:$Zd), iops,
6533 asm, "\t$Zd, $Pg"#pg_suffix#", $Zn",
6539 let Inst{31-24} = 0b00000100;
6540 let Inst{23-22} = sz8_32;
6541 let Inst{21-19} = 0b010;
6542 let Inst{18-16} = opc;
6543 let Inst{15-13} = 0b001;
6544 let Inst{12-10} = Pg;
6548 let ElementSize = zprty.ElementSize;
6551 multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> {
6552 let Constraints = "$Zd = $_Zd" in {
6553 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m",
6554 (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>;
6555 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m",
6556 (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>;
6557 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m",
6558 (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>;
6559 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m",
6560 (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>;
6564 multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> {
6565 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z",
6566 (ins PPR3bAny:$Pg, ZPR8:$Zn)>;
6567 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z",
6568 (ins PPR3bAny:$Pg, ZPR16:$Zn)>;
6569 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z",
6570 (ins PPR3bAny:$Pg, ZPR32:$Zn)>;
6571 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z",
6572 (ins PPR3bAny:$Pg, ZPR64:$Zn)>;
6575 //===----------------------------------------------------------------------===//
6576 // SVE Propagate Break Group
6577 //===----------------------------------------------------------------------===//
6579 class sve_int_brkp<bits<2> opc, string asm>
6580 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
6581 asm, "\t$Pd, $Pg/z, $Pn, $Pm",
6588 let Inst{31-24} = 0b00100101;
6590 let Inst{22} = opc{1};
6591 let Inst{21-20} = 0b00;
6592 let Inst{19-16} = Pm;
6593 let Inst{15-14} = 0b11;
6594 let Inst{13-10} = Pg;
6597 let Inst{4} = opc{0};
6600 let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
6604 //===----------------------------------------------------------------------===//
6605 // SVE Partition Break Group
6606 //===----------------------------------------------------------------------===//
6608 class sve_int_brkn<bit S, string asm>
6609 : I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm),
6610 asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm",
6616 let Inst{31-23} = 0b001001010;
6618 let Inst{21-14} = 0b01100001;
6619 let Inst{13-10} = Pg;
6623 let Inst{3-0} = Pdm;
6625 let Constraints = "$Pdm = $_Pdm";
6626 let Defs = !if(!eq (S, 0b1), [NZCV], []);
6629 class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
6630 : I<(outs PPR8:$Pd), iops,
6631 asm, "\t$Pd, $Pg"#suffix#", $Pn",
6637 let Inst{31-24} = 0b00100101;
6638 let Inst{23-22} = opc{2-1};
6639 let Inst{21-14} = 0b01000001;
6640 let Inst{13-10} = Pg;
6643 let Inst{4} = opc{0};
6646 let Constraints = !if(!eq (opc{0}, 1), "$Pd = $_Pd", "");
6647 let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
6651 multiclass sve_int_break_m<bits<3> opc, string asm> {
6652 def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>;
6655 multiclass sve_int_break_z<bits<3> opc, string asm> {
6656 def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
6659 //===----------------------------------------------------------------------===//
6660 // SVE2 String Processing Group
6661 //===----------------------------------------------------------------------===//
6663 class sve2_char_match<bit sz, bit opc, string asm,
6664 PPRRegOp pprty, ZPRRegOp zprty>
6665 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
6666 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
6673 let Inst{31-23} = 0b010001010;
6676 let Inst{20-16} = Zm;
6677 let Inst{15-13} = 0b100;
6678 let Inst{12-10} = Pg;
6686 multiclass sve2_char_match<bit opc, string asm> {
6687 def _B : sve2_char_match<0b0, opc, asm, PPR8, ZPR8>;
6688 def _H : sve2_char_match<0b1, opc, asm, PPR16, ZPR16>;
6691 //===----------------------------------------------------------------------===//
6692 // SVE2 Histogram Computation - Segment Group
6693 //===----------------------------------------------------------------------===//
6695 class sve2_hist_gen_segment<string asm>
6696 : I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm),
6697 asm, "\t$Zd, $Zn, $Zm",
6703 let Inst{31-21} = 0b01000101001;
6704 let Inst{20-16} = Zm;
6705 let Inst{15-10} = 0b101000;
6710 //===----------------------------------------------------------------------===//
6711 // SVE2 Histogram Computation - Vector Group
6712 //===----------------------------------------------------------------------===//
6714 class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty>
6715 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
6716 asm, "\t$Zd, $Pg/z, $Zn, $Zm",
6723 let Inst{31-23} = 0b010001011;
6726 let Inst{20-16} = Zm;
6727 let Inst{15-13} = 0b110;
6728 let Inst{12-10} = Pg;
6733 multiclass sve2_hist_gen_vector<string asm> {
6734 def _S : sve2_hist_gen_vector<0b0, asm, ZPR32>;
6735 def _D : sve2_hist_gen_vector<0b1, asm, ZPR64>;
6738 //===----------------------------------------------------------------------===//
6739 // SVE2 Crypto Extensions Group
6740 //===----------------------------------------------------------------------===//
6742 class sve2_crypto_cons_bin_op<bit opc, string asm, ZPRRegOp zprty>
6743 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
6744 asm, "\t$Zd, $Zn, $Zm",
6750 let Inst{31-21} = 0b01000101001;
6751 let Inst{20-16} = Zm;
6752 let Inst{15-11} = 0b11110;
6758 class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty>
6759 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm),
6760 asm, "\t$Zdn, $_Zdn, $Zm",
6765 let Inst{31-17} = 0b010001010010001;
6766 let Inst{16} = opc{1};
6767 let Inst{15-11} = 0b11100;
6768 let Inst{10} = opc{0};
6770 let Inst{4-0} = Zdn;
6772 let Constraints = "$Zdn = $_Zdn";
6775 class sve2_crypto_unary_op<bit opc, string asm>
6776 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn),
6777 asm, "\t$Zdn, $_Zdn",
6781 let Inst{31-11} = 0b010001010010000011100;
6783 let Inst{9-5} = 0b00000;
6784 let Inst{4-0} = Zdn;
6786 let Constraints = "$Zdn = $_Zdn";