1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
13 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this.
14 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this.
15 #include "llvm/Support/CodeGen.h"
19 class AMDGPUTargetMachine;
21 class GCNTargetMachine;
32 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
33 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
34 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
35 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
36 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
37 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
40 FunctionPass *createR600VectorRegMerger();
41 FunctionPass *createR600ExpandSpecialInstrsPass();
42 FunctionPass *createR600EmitClauseMarkers();
43 FunctionPass *createR600ClauseMergePass();
44 FunctionPass *createR600Packetizer();
45 FunctionPass *createR600ControlFlowFinalizer();
46 FunctionPass *createAMDGPUCFGStructurizerPass();
47 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
50 FunctionPass *createGCNDPPCombinePass();
51 FunctionPass *createSIAnnotateControlFlowPass();
52 FunctionPass *createSIFoldOperandsPass();
53 FunctionPass *createSIPeepholeSDWAPass();
54 FunctionPass *createSILowerI1CopiesPass();
55 FunctionPass *createSIFixupVectorISelPass();
56 FunctionPass *createSIAddIMGInitPass();
57 FunctionPass *createSIShrinkInstructionsPass();
58 FunctionPass *createSILoadStoreOptimizerPass();
59 FunctionPass *createSIWholeQuadModePass();
60 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
61 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
62 FunctionPass *createSIFixSGPRCopiesPass();
63 FunctionPass *createSIMemoryLegalizerPass();
64 FunctionPass *createSIInsertWaitcntsPass();
65 FunctionPass *createSIPreAllocateWWMRegsPass();
66 FunctionPass *createSIFormMemoryClausesPass();
68 FunctionPass *createSIPostRABundlerPass();
69 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
70 FunctionPass *createAMDGPUUseNativeCallsPass();
71 FunctionPass *createAMDGPUCodeGenPreparePass();
72 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
73 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
74 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
75 FunctionPass *createAMDGPURewriteOutArgumentsPass();
76 FunctionPass *createSIModeRegisterPass();
78 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
80 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
81 extern char &AMDGPUMachineCFGStructurizerID;
83 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
85 Pass *createAMDGPUAnnotateKernelFeaturesPass();
86 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
87 extern char &AMDGPUAnnotateKernelFeaturesID;
89 FunctionPass *createAMDGPUAtomicOptimizerPass();
90 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
91 extern char &AMDGPUAtomicOptimizerID;
93 ModulePass *createAMDGPULowerIntrinsicsPass();
94 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
95 extern char &AMDGPULowerIntrinsicsID;
97 ModulePass *createAMDGPUFixFunctionBitcastsPass();
98 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
99 extern char &AMDGPUFixFunctionBitcastsID;
101 FunctionPass *createAMDGPULowerKernelArgumentsPass();
102 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
103 extern char &AMDGPULowerKernelArgumentsID;
105 ModulePass *createAMDGPULowerKernelAttributesPass();
106 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
107 extern char &AMDGPULowerKernelAttributesID;
109 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
110 extern char &AMDGPUPropagateAttributesEarlyID;
112 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
113 extern char &AMDGPUPropagateAttributesLateID;
115 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
116 extern char &AMDGPURewriteOutArgumentsID;
118 void initializeGCNDPPCombinePass(PassRegistry &);
119 extern char &GCNDPPCombineID;
121 void initializeR600ClauseMergePassPass(PassRegistry &);
122 extern char &R600ClauseMergePassID;
124 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
125 extern char &R600ControlFlowFinalizerID;
127 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
128 extern char &R600ExpandSpecialInstrsPassID;
130 void initializeR600VectorRegMergerPass(PassRegistry &);
131 extern char &R600VectorRegMergerID;
133 void initializeR600PacketizerPass(PassRegistry &);
134 extern char &R600PacketizerID;
136 void initializeSIFoldOperandsPass(PassRegistry &);
137 extern char &SIFoldOperandsID;
139 void initializeSIPeepholeSDWAPass(PassRegistry &);
140 extern char &SIPeepholeSDWAID;
142 void initializeSIShrinkInstructionsPass(PassRegistry&);
143 extern char &SIShrinkInstructionsID;
145 void initializeSIFixSGPRCopiesPass(PassRegistry &);
146 extern char &SIFixSGPRCopiesID;
148 void initializeSIFixVGPRCopiesPass(PassRegistry &);
149 extern char &SIFixVGPRCopiesID;
151 void initializeSIFixupVectorISelPass(PassRegistry &);
152 extern char &SIFixupVectorISelID;
154 void initializeSILowerI1CopiesPass(PassRegistry &);
155 extern char &SILowerI1CopiesID;
157 void initializeSILowerSGPRSpillsPass(PassRegistry &);
158 extern char &SILowerSGPRSpillsID;
160 void initializeSILoadStoreOptimizerPass(PassRegistry &);
161 extern char &SILoadStoreOptimizerID;
163 void initializeSIWholeQuadModePass(PassRegistry &);
164 extern char &SIWholeQuadModeID;
166 void initializeSILowerControlFlowPass(PassRegistry &);
167 extern char &SILowerControlFlowID;
169 void initializeSIRemoveShortExecBranchesPass(PassRegistry &);
170 extern char &SIRemoveShortExecBranchesID;
172 void initializeSIPreEmitPeepholePass(PassRegistry &);
173 extern char &SIPreEmitPeepholeID;
175 void initializeSIInsertSkipsPass(PassRegistry &);
176 extern char &SIInsertSkipsPassID;
178 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
179 extern char &SIOptimizeExecMaskingID;
181 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
182 extern char &SIPreAllocateWWMRegsID;
184 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
185 extern char &AMDGPUSimplifyLibCallsID;
187 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
188 extern char &AMDGPUUseNativeCallsID;
190 void initializeSIAddIMGInitPass(PassRegistry &);
191 extern char &SIAddIMGInitID;
193 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
194 extern char &AMDGPUPerfHintAnalysisID;
196 // Passes common to R600 and SI
197 FunctionPass *createAMDGPUPromoteAlloca();
198 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
199 extern char &AMDGPUPromoteAllocaID;
201 FunctionPass *createAMDGPUPromoteAllocaToVector();
202 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
203 extern char &AMDGPUPromoteAllocaToVectorID;
205 Pass *createAMDGPUStructurizeCFGPass();
206 FunctionPass *createAMDGPUISelDag(
207 TargetMachine *TM = nullptr,
208 CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
209 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
210 ModulePass *createR600OpenCLImageTypeLoweringPass();
211 FunctionPass *createAMDGPUAnnotateUniformValues();
213 ModulePass *createAMDGPUPrintfRuntimeBinding();
214 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
215 extern char &AMDGPUPrintfRuntimeBindingID;
217 ModulePass* createAMDGPUUnifyMetadataPass();
218 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
219 extern char &AMDGPUUnifyMetadataID;
221 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
222 extern char &SIOptimizeExecMaskingPreRAID;
224 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
225 extern char &AMDGPUAnnotateUniformValuesPassID;
227 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
228 extern char &AMDGPUCodeGenPrepareID;
230 void initializeSIAnnotateControlFlowPass(PassRegistry&);
231 extern char &SIAnnotateControlFlowPassID;
233 void initializeSIMemoryLegalizerPass(PassRegistry&);
234 extern char &SIMemoryLegalizerID;
236 void initializeSIModeRegisterPass(PassRegistry&);
237 extern char &SIModeRegisterID;
239 void initializeSIInsertHardClausesPass(PassRegistry &);
240 extern char &SIInsertHardClausesID;
242 void initializeSIInsertWaitcntsPass(PassRegistry&);
243 extern char &SIInsertWaitcntsID;
245 void initializeSIFormMemoryClausesPass(PassRegistry&);
246 extern char &SIFormMemoryClausesID;
248 void initializeSIPostRABundlerPass(PassRegistry&);
249 extern char &SIPostRABundlerID;
251 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
252 extern char &AMDGPUUnifyDivergentExitNodesID;
254 ImmutablePass *createAMDGPUAAWrapperPass();
255 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
256 ImmutablePass *createAMDGPUExternalAAWrapperPass();
257 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
259 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
261 Pass *createAMDGPUFunctionInliningPass();
262 void initializeAMDGPUInlinerPass(PassRegistry&);
264 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
265 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
266 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
268 void initializeGCNRegBankReassignPass(PassRegistry &);
269 extern char &GCNRegBankReassignID;
271 void initializeGCNNSAReassignPass(PassRegistry &);
272 extern char &GCNNSAReassignID;
277 TI_SCRATCH_RSRC_DWORD0,
278 TI_SCRATCH_RSRC_DWORD1,
279 TI_SCRATCH_RSRC_DWORD2,
280 TI_SCRATCH_RSRC_DWORD3
284 } // End namespace llvm
286 /// OpenCL uses address spaces to differentiate between
287 /// various memory regions on the hardware. On the CPU
288 /// all of the address spaces point to the same memory,
289 /// however on the GPU, each address space points to
290 /// a separate piece of memory that is unique from other
291 /// memory locations.
294 // The maximum value for flat, generic, local, private, constant and region.
295 MAX_AMDGPU_ADDRESS = 7,
297 FLAT_ADDRESS = 0, ///< Address space for flat memory.
298 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
299 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
301 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
302 LOCAL_ADDRESS = 3, ///< Address space for local memory.
303 PRIVATE_ADDRESS = 5, ///< Address space for private memory.
305 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
307 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
309 /// Address space for direct addressible parameter memory (CONST0).
311 /// Address space for indirect addressible parameter memory (VTX1).
314 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
315 // this order to be able to dynamically index a constant buffer, for
318 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
320 CONSTANT_BUFFER_0 = 8,
321 CONSTANT_BUFFER_1 = 9,
322 CONSTANT_BUFFER_2 = 10,
323 CONSTANT_BUFFER_3 = 11,
324 CONSTANT_BUFFER_4 = 12,
325 CONSTANT_BUFFER_5 = 13,
326 CONSTANT_BUFFER_6 = 14,
327 CONSTANT_BUFFER_7 = 15,
328 CONSTANT_BUFFER_8 = 16,
329 CONSTANT_BUFFER_9 = 17,
330 CONSTANT_BUFFER_10 = 18,
331 CONSTANT_BUFFER_11 = 19,
332 CONSTANT_BUFFER_12 = 20,
333 CONSTANT_BUFFER_13 = 21,
334 CONSTANT_BUFFER_14 = 22,
335 CONSTANT_BUFFER_15 = 23,
337 // Some places use this if the address space can't be determined.
338 UNKNOWN_ADDRESS_SPACE = ~0u,