contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPU.h

   1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 /// \file
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  12
  13 #include "llvm/Target/TargetMachine.h"
  14 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this.
  15 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this.
  16
  17 namespace llvm {
  18
  19 class AMDGPUTargetMachine;
  20 class FunctionPass;
  21 class GCNTargetMachine;
  22 class ModulePass;
  23 class Pass;
  24 class Target;
  25 class TargetMachine;
  26 class TargetOptions;
  27 class PassRegistry;
  28 class Module;
  29
  30 // R600 Passes
  31 FunctionPass *createR600VectorRegMerger();
  32 FunctionPass *createR600ExpandSpecialInstrsPass();
  33 FunctionPass *createR600EmitClauseMarkers();
  34 FunctionPass *createR600ClauseMergePass();
  35 FunctionPass *createR600Packetizer();
  36 FunctionPass *createR600ControlFlowFinalizer();
  37 FunctionPass *createAMDGPUCFGStructurizerPass();
  38 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
  39
  40 // SI Passes
  41 FunctionPass *createGCNDPPCombinePass();
  42 FunctionPass *createSIAnnotateControlFlowPass();
  43 FunctionPass *createSIFoldOperandsPass();
  44 FunctionPass *createSIPeepholeSDWAPass();
  45 FunctionPass *createSILowerI1CopiesPass();
  46 FunctionPass *createSIFixupVectorISelPass();
  47 FunctionPass *createSIAddIMGInitPass();
  48 FunctionPass *createSIShrinkInstructionsPass();
  49 FunctionPass *createSILoadStoreOptimizerPass();
  50 FunctionPass *createSIWholeQuadModePass();
  51 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
  52 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
  53 FunctionPass *createSIFixSGPRCopiesPass();
  54 FunctionPass *createSIMemoryLegalizerPass();
  55 FunctionPass *createSIInsertWaitcntsPass();
  56 FunctionPass *createSIPreAllocateWWMRegsPass();
  57 FunctionPass *createSIFormMemoryClausesPass();
  58 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &,
  59                                                const TargetMachine *);
  60 FunctionPass *createAMDGPUUseNativeCallsPass();
  61 FunctionPass *createAMDGPUCodeGenPreparePass();
  62 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
  63 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
  64 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
  65 FunctionPass *createAMDGPURewriteOutArgumentsPass();
  66 FunctionPass *createSIModeRegisterPass();
  67
  68 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
  69
  70 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
  71 extern char &AMDGPUMachineCFGStructurizerID;
  72
  73 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
  74
  75 Pass *createAMDGPUAnnotateKernelFeaturesPass();
  76 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
  77 extern char &AMDGPUAnnotateKernelFeaturesID;
  78
  79 FunctionPass *createAMDGPUAtomicOptimizerPass();
  80 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
  81 extern char &AMDGPUAtomicOptimizerID;
  82
  83 ModulePass *createAMDGPULowerIntrinsicsPass();
  84 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
  85 extern char &AMDGPULowerIntrinsicsID;
  86
  87 ModulePass *createAMDGPUFixFunctionBitcastsPass();
  88 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
  89 extern char &AMDGPUFixFunctionBitcastsID;
  90
  91 FunctionPass *createAMDGPULowerKernelArgumentsPass();
  92 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
  93 extern char &AMDGPULowerKernelArgumentsID;
  94
  95 ModulePass *createAMDGPULowerKernelAttributesPass();
  96 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
  97 extern char &AMDGPULowerKernelAttributesID;
  98
  99 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
 100 extern char &AMDGPUPropagateAttributesEarlyID;
 101
 102 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
 103 extern char &AMDGPUPropagateAttributesLateID;
 104
 105 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
 106 extern char &AMDGPURewriteOutArgumentsID;
 107
 108 void initializeGCNDPPCombinePass(PassRegistry &);
 109 extern char &GCNDPPCombineID;
 110
 111 void initializeR600ClauseMergePassPass(PassRegistry &);
 112 extern char &R600ClauseMergePassID;
 113
 114 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
 115 extern char &R600ControlFlowFinalizerID;
 116
 117 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
 118 extern char &R600ExpandSpecialInstrsPassID;
 119
 120 void initializeR600VectorRegMergerPass(PassRegistry &);
 121 extern char &R600VectorRegMergerID;
 122
 123 void initializeR600PacketizerPass(PassRegistry &);
 124 extern char &R600PacketizerID;
 125
 126 void initializeSIFoldOperandsPass(PassRegistry &);
 127 extern char &SIFoldOperandsID;
 128
 129 void initializeSIPeepholeSDWAPass(PassRegistry &);
 130 extern char &SIPeepholeSDWAID;
 131
 132 void initializeSIShrinkInstructionsPass(PassRegistry&);
 133 extern char &SIShrinkInstructionsID;
 134
 135 void initializeSIFixSGPRCopiesPass(PassRegistry &);
 136 extern char &SIFixSGPRCopiesID;
 137
 138 void initializeSIFixVGPRCopiesPass(PassRegistry &);
 139 extern char &SIFixVGPRCopiesID;
 140
 141 void initializeSIFixupVectorISelPass(PassRegistry &);
 142 extern char &SIFixupVectorISelID;
 143
 144 void initializeSILowerI1CopiesPass(PassRegistry &);
 145 extern char &SILowerI1CopiesID;
 146
 147 void initializeSILowerSGPRSpillsPass(PassRegistry &);
 148 extern char &SILowerSGPRSpillsID;
 149
 150 void initializeSILoadStoreOptimizerPass(PassRegistry &);
 151 extern char &SILoadStoreOptimizerID;
 152
 153 void initializeSIWholeQuadModePass(PassRegistry &);
 154 extern char &SIWholeQuadModeID;
 155
 156 void initializeSILowerControlFlowPass(PassRegistry &);
 157 extern char &SILowerControlFlowID;
 158
 159 void initializeSIInsertSkipsPass(PassRegistry &);
 160 extern char &SIInsertSkipsPassID;
 161
 162 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
 163 extern char &SIOptimizeExecMaskingID;
 164
 165 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
 166 extern char &SIPreAllocateWWMRegsID;
 167
 168 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
 169 extern char &AMDGPUSimplifyLibCallsID;
 170
 171 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
 172 extern char &AMDGPUUseNativeCallsID;
 173
 174 void initializeSIAddIMGInitPass(PassRegistry &);
 175 extern char &SIAddIMGInitID;
 176
 177 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
 178 extern char &AMDGPUPerfHintAnalysisID;
 179
 180 // Passes common to R600 and SI
 181 FunctionPass *createAMDGPUPromoteAlloca();
 182 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
 183 extern char &AMDGPUPromoteAllocaID;
 184
 185 Pass *createAMDGPUStructurizeCFGPass();
 186 FunctionPass *createAMDGPUISelDag(
 187   TargetMachine *TM = nullptr,
 188   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
 189 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 190 ModulePass *createR600OpenCLImageTypeLoweringPass();
 191 FunctionPass *createAMDGPUAnnotateUniformValues();
 192
 193 ModulePass *createAMDGPUPrintfRuntimeBinding();
 194 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
 195 extern char &AMDGPUPrintfRuntimeBindingID;
 196
 197 ModulePass* createAMDGPUUnifyMetadataPass();
 198 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
 199 extern char &AMDGPUUnifyMetadataID;
 200
 201 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
 202 extern char &SIOptimizeExecMaskingPreRAID;
 203
 204 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 205 extern char &AMDGPUAnnotateUniformValuesPassID;
 206
 207 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
 208 extern char &AMDGPUCodeGenPrepareID;
 209
 210 void initializeSIAnnotateControlFlowPass(PassRegistry&);
 211 extern char &SIAnnotateControlFlowPassID;
 212
 213 void initializeSIMemoryLegalizerPass(PassRegistry&);
 214 extern char &SIMemoryLegalizerID;
 215
 216 void initializeSIModeRegisterPass(PassRegistry&);
 217 extern char &SIModeRegisterID;
 218
 219 void initializeSIInsertWaitcntsPass(PassRegistry&);
 220 extern char &SIInsertWaitcntsID;
 221
 222 void initializeSIFormMemoryClausesPass(PassRegistry&);
 223 extern char &SIFormMemoryClausesID;
 224
 225 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
 226 extern char &AMDGPUUnifyDivergentExitNodesID;
 227
 228 ImmutablePass *createAMDGPUAAWrapperPass();
 229 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
 230 ImmutablePass *createAMDGPUExternalAAWrapperPass();
 231 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
 232
 233 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
 234
 235 Pass *createAMDGPUFunctionInliningPass();
 236 void initializeAMDGPUInlinerPass(PassRegistry&);
 237
 238 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
 239 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
 240 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
 241
 242 void initializeGCNRegBankReassignPass(PassRegistry &);
 243 extern char &GCNRegBankReassignID;
 244
 245 void initializeGCNNSAReassignPass(PassRegistry &);
 246 extern char &GCNNSAReassignID;
 247
 248 namespace AMDGPU {
 249 enum TargetIndex {
 250   TI_CONSTDATA_START,
 251   TI_SCRATCH_RSRC_DWORD0,
 252   TI_SCRATCH_RSRC_DWORD1,
 253   TI_SCRATCH_RSRC_DWORD2,
 254   TI_SCRATCH_RSRC_DWORD3
 255 };
 256 }
 257
 258 } // End namespace llvm
 259
 260 /// OpenCL uses address spaces to differentiate between
 261 /// various memory regions on the hardware. On the CPU
 262 /// all of the address spaces point to the same memory,
 263 /// however on the GPU, each address space points to
 264 /// a separate piece of memory that is unique from other
 265 /// memory locations.
 266 namespace AMDGPUAS {
 267   enum : unsigned {
 268     // The maximum value for flat, generic, local, private, constant and region.
 269     MAX_AMDGPU_ADDRESS = 7,
 270
 271     FLAT_ADDRESS = 0,     ///< Address space for flat memory.
 272     GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
 273     REGION_ADDRESS = 2,   ///< Address space for region memory. (GDS)
 274
 275     CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
 276     LOCAL_ADDRESS = 3,    ///< Address space for local memory.
 277     PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
 278
 279     CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
 280
 281     BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
 282
 283     /// Address space for direct addressible parameter memory (CONST0).
 284     PARAM_D_ADDRESS = 6,
 285     /// Address space for indirect addressible parameter memory (VTX1).
 286     PARAM_I_ADDRESS = 7,
 287
 288     // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
 289     // this order to be able to dynamically index a constant buffer, for
 290     // example:
 291     //
 292     // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
 293
 294     CONSTANT_BUFFER_0 = 8,
 295     CONSTANT_BUFFER_1 = 9,
 296     CONSTANT_BUFFER_2 = 10,
 297     CONSTANT_BUFFER_3 = 11,
 298     CONSTANT_BUFFER_4 = 12,
 299     CONSTANT_BUFFER_5 = 13,
 300     CONSTANT_BUFFER_6 = 14,
 301     CONSTANT_BUFFER_7 = 15,
 302     CONSTANT_BUFFER_8 = 16,
 303     CONSTANT_BUFFER_9 = 17,
 304     CONSTANT_BUFFER_10 = 18,
 305     CONSTANT_BUFFER_11 = 19,
 306     CONSTANT_BUFFER_12 = 20,
 307     CONSTANT_BUFFER_13 = 21,
 308     CONSTANT_BUFFER_14 = 22,
 309     CONSTANT_BUFFER_15 = 23,
 310
 311     // Some places use this if the address space can't be determined.
 312     UNKNOWN_ADDRESS_SPACE = ~0u,
 313   };
 314 }
 315
 316 #endif