1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this.
15 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this.
19 class AMDGPUTargetMachine;
21 class GCNTargetMachine;
31 FunctionPass *createR600VectorRegMerger();
32 FunctionPass *createR600ExpandSpecialInstrsPass();
33 FunctionPass *createR600EmitClauseMarkers();
34 FunctionPass *createR600ClauseMergePass();
35 FunctionPass *createR600Packetizer();
36 FunctionPass *createR600ControlFlowFinalizer();
37 FunctionPass *createAMDGPUCFGStructurizerPass();
38 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
41 FunctionPass *createGCNDPPCombinePass();
42 FunctionPass *createSIAnnotateControlFlowPass();
43 FunctionPass *createSIFoldOperandsPass();
44 FunctionPass *createSIPeepholeSDWAPass();
45 FunctionPass *createSILowerI1CopiesPass();
46 FunctionPass *createSIFixupVectorISelPass();
47 FunctionPass *createSIAddIMGInitPass();
48 FunctionPass *createSIShrinkInstructionsPass();
49 FunctionPass *createSILoadStoreOptimizerPass();
50 FunctionPass *createSIWholeQuadModePass();
51 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
52 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
53 FunctionPass *createSIFixSGPRCopiesPass();
54 FunctionPass *createSIMemoryLegalizerPass();
55 FunctionPass *createSIInsertWaitcntsPass();
56 FunctionPass *createSIPreAllocateWWMRegsPass();
57 FunctionPass *createSIFormMemoryClausesPass();
58 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &,
59 const TargetMachine *);
60 FunctionPass *createAMDGPUUseNativeCallsPass();
61 FunctionPass *createAMDGPUCodeGenPreparePass();
62 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
63 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
64 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
65 FunctionPass *createAMDGPURewriteOutArgumentsPass();
66 FunctionPass *createSIModeRegisterPass();
68 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
70 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
71 extern char &AMDGPUMachineCFGStructurizerID;
73 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
75 Pass *createAMDGPUAnnotateKernelFeaturesPass();
76 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
77 extern char &AMDGPUAnnotateKernelFeaturesID;
79 FunctionPass *createAMDGPUAtomicOptimizerPass();
80 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
81 extern char &AMDGPUAtomicOptimizerID;
83 ModulePass *createAMDGPULowerIntrinsicsPass();
84 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
85 extern char &AMDGPULowerIntrinsicsID;
87 ModulePass *createAMDGPUFixFunctionBitcastsPass();
88 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
89 extern char &AMDGPUFixFunctionBitcastsID;
91 FunctionPass *createAMDGPULowerKernelArgumentsPass();
92 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
93 extern char &AMDGPULowerKernelArgumentsID;
95 ModulePass *createAMDGPULowerKernelAttributesPass();
96 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
97 extern char &AMDGPULowerKernelAttributesID;
99 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
100 extern char &AMDGPUPropagateAttributesEarlyID;
102 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
103 extern char &AMDGPUPropagateAttributesLateID;
105 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
106 extern char &AMDGPURewriteOutArgumentsID;
108 void initializeGCNDPPCombinePass(PassRegistry &);
109 extern char &GCNDPPCombineID;
111 void initializeR600ClauseMergePassPass(PassRegistry &);
112 extern char &R600ClauseMergePassID;
114 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
115 extern char &R600ControlFlowFinalizerID;
117 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
118 extern char &R600ExpandSpecialInstrsPassID;
120 void initializeR600VectorRegMergerPass(PassRegistry &);
121 extern char &R600VectorRegMergerID;
123 void initializeR600PacketizerPass(PassRegistry &);
124 extern char &R600PacketizerID;
126 void initializeSIFoldOperandsPass(PassRegistry &);
127 extern char &SIFoldOperandsID;
129 void initializeSIPeepholeSDWAPass(PassRegistry &);
130 extern char &SIPeepholeSDWAID;
132 void initializeSIShrinkInstructionsPass(PassRegistry&);
133 extern char &SIShrinkInstructionsID;
135 void initializeSIFixSGPRCopiesPass(PassRegistry &);
136 extern char &SIFixSGPRCopiesID;
138 void initializeSIFixVGPRCopiesPass(PassRegistry &);
139 extern char &SIFixVGPRCopiesID;
141 void initializeSIFixupVectorISelPass(PassRegistry &);
142 extern char &SIFixupVectorISelID;
144 void initializeSILowerI1CopiesPass(PassRegistry &);
145 extern char &SILowerI1CopiesID;
147 void initializeSILowerSGPRSpillsPass(PassRegistry &);
148 extern char &SILowerSGPRSpillsID;
150 void initializeSILoadStoreOptimizerPass(PassRegistry &);
151 extern char &SILoadStoreOptimizerID;
153 void initializeSIWholeQuadModePass(PassRegistry &);
154 extern char &SIWholeQuadModeID;
156 void initializeSILowerControlFlowPass(PassRegistry &);
157 extern char &SILowerControlFlowID;
159 void initializeSIRemoveShortExecBranchesPass(PassRegistry &);
160 extern char &SIRemoveShortExecBranchesID;
162 void initializeSIInsertSkipsPass(PassRegistry &);
163 extern char &SIInsertSkipsPassID;
165 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
166 extern char &SIOptimizeExecMaskingID;
168 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
169 extern char &SIPreAllocateWWMRegsID;
171 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
172 extern char &AMDGPUSimplifyLibCallsID;
174 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
175 extern char &AMDGPUUseNativeCallsID;
177 void initializeSIAddIMGInitPass(PassRegistry &);
178 extern char &SIAddIMGInitID;
180 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
181 extern char &AMDGPUPerfHintAnalysisID;
183 // Passes common to R600 and SI
184 FunctionPass *createAMDGPUPromoteAlloca();
185 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
186 extern char &AMDGPUPromoteAllocaID;
188 Pass *createAMDGPUStructurizeCFGPass();
189 FunctionPass *createAMDGPUISelDag(
190 TargetMachine *TM = nullptr,
191 CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
192 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
193 ModulePass *createR600OpenCLImageTypeLoweringPass();
194 FunctionPass *createAMDGPUAnnotateUniformValues();
196 ModulePass *createAMDGPUPrintfRuntimeBinding();
197 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
198 extern char &AMDGPUPrintfRuntimeBindingID;
200 ModulePass* createAMDGPUUnifyMetadataPass();
201 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
202 extern char &AMDGPUUnifyMetadataID;
204 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
205 extern char &SIOptimizeExecMaskingPreRAID;
207 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
208 extern char &AMDGPUAnnotateUniformValuesPassID;
210 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
211 extern char &AMDGPUCodeGenPrepareID;
213 void initializeSIAnnotateControlFlowPass(PassRegistry&);
214 extern char &SIAnnotateControlFlowPassID;
216 void initializeSIMemoryLegalizerPass(PassRegistry&);
217 extern char &SIMemoryLegalizerID;
219 void initializeSIModeRegisterPass(PassRegistry&);
220 extern char &SIModeRegisterID;
222 void initializeSIInsertWaitcntsPass(PassRegistry&);
223 extern char &SIInsertWaitcntsID;
225 void initializeSIFormMemoryClausesPass(PassRegistry&);
226 extern char &SIFormMemoryClausesID;
228 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
229 extern char &AMDGPUUnifyDivergentExitNodesID;
231 ImmutablePass *createAMDGPUAAWrapperPass();
232 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
233 ImmutablePass *createAMDGPUExternalAAWrapperPass();
234 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
236 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
238 Pass *createAMDGPUFunctionInliningPass();
239 void initializeAMDGPUInlinerPass(PassRegistry&);
241 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
242 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
243 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
245 void initializeGCNRegBankReassignPass(PassRegistry &);
246 extern char &GCNRegBankReassignID;
248 void initializeGCNNSAReassignPass(PassRegistry &);
249 extern char &GCNNSAReassignID;
254 TI_SCRATCH_RSRC_DWORD0,
255 TI_SCRATCH_RSRC_DWORD1,
256 TI_SCRATCH_RSRC_DWORD2,
257 TI_SCRATCH_RSRC_DWORD3
261 } // End namespace llvm
263 /// OpenCL uses address spaces to differentiate between
264 /// various memory regions on the hardware. On the CPU
265 /// all of the address spaces point to the same memory,
266 /// however on the GPU, each address space points to
267 /// a separate piece of memory that is unique from other
268 /// memory locations.
271 // The maximum value for flat, generic, local, private, constant and region.
272 MAX_AMDGPU_ADDRESS = 7,
274 FLAT_ADDRESS = 0, ///< Address space for flat memory.
275 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
276 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
278 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
279 LOCAL_ADDRESS = 3, ///< Address space for local memory.
280 PRIVATE_ADDRESS = 5, ///< Address space for private memory.
282 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
284 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
286 /// Address space for direct addressible parameter memory (CONST0).
288 /// Address space for indirect addressible parameter memory (VTX1).
291 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
292 // this order to be able to dynamically index a constant buffer, for
295 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
297 CONSTANT_BUFFER_0 = 8,
298 CONSTANT_BUFFER_1 = 9,
299 CONSTANT_BUFFER_2 = 10,
300 CONSTANT_BUFFER_3 = 11,
301 CONSTANT_BUFFER_4 = 12,
302 CONSTANT_BUFFER_5 = 13,
303 CONSTANT_BUFFER_6 = 14,
304 CONSTANT_BUFFER_7 = 15,
305 CONSTANT_BUFFER_8 = 16,
306 CONSTANT_BUFFER_9 = 17,
307 CONSTANT_BUFFER_10 = 18,
308 CONSTANT_BUFFER_11 = 19,
309 CONSTANT_BUFFER_12 = 20,
310 CONSTANT_BUFFER_13 = 21,
311 CONSTANT_BUFFER_14 = 22,
312 CONSTANT_BUFFER_15 = 23,
314 // Some places use this if the address space can't be determined.
315 UNKNOWN_ADDRESS_SPACE = ~0u,