contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===------------------------------------------------------------===//
   8
   9 include "llvm/TableGen/SearchableTable.td"
  10 include "llvm/Target/Target.td"
  11 include "AMDGPUFeatures.td"
  12
  13 def p0 : PtrValueType<i64, 0>;
  14 def p1 : PtrValueType<i64, 1>;
  15 def p2 : PtrValueType<i32, 2>;
  16 def p3 : PtrValueType<i32, 3>;
  17 def p4 : PtrValueType<i64, 4>;
  18 def p5 : PtrValueType<i32, 5>;
  19 def p6 : PtrValueType<i32, 6>;
  20
  21
  22 class BoolToList<bit Value> {
  23   list<int> ret = !if(Value, [1]<int>, []<int>);
  24 }
  25
  26 //===------------------------------------------------------------===//
  27 // Subtarget Features (device properties)
  28 //===------------------------------------------------------------===//
  29
  30 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  31   "FastFMAF32",
  32   "true",
  33   "Assuming f32 fma is at least as fast as mul + add"
  34 >;
  35
  36 def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
  37   "FastDenormalF32",
  38   "true",
  39   "Enabling denormals does not cause f32 instructions to run at f64 rates"
  40 >;
  41
  42 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
  43   "MIMG_R128",
  44   "true",
  45   "Support 128-bit texture resources"
  46 >;
  47
  48 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
  49   "HalfRate64Ops",
  50   "true",
  51   "Most fp64 instructions are half rate instead of quarter"
  52 >;
  53
  54 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  55   "FlatAddressSpace",
  56   "true",
  57   "Support flat address space"
  58 >;
  59
  60 def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
  61   "FlatInstOffsets",
  62   "true",
  63   "Flat instructions have immediate offset addressing mode"
  64 >;
  65
  66 def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
  67   "FlatGlobalInsts",
  68   "true",
  69   "Have global_* flat memory instructions"
  70 >;
  71
  72 def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
  73   "FlatScratchInsts",
  74   "true",
  75   "Have scratch_* flat memory instructions"
  76 >;
  77
  78 def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
  79   "ScalarFlatScratchInsts",
  80   "true",
  81   "Have s_scratch_* flat memory instructions"
  82 >;
  83
  84 def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
  85   "AddNoCarryInsts",
  86   "true",
  87   "Have VALU add/sub instructions without carry out"
  88 >;
  89
  90 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
  91   "UnalignedBufferAccess",
  92   "true",
  93   "Support unaligned global loads and stores"
  94 >;
  95
  96 def FeatureTrapHandler: SubtargetFeature<"trap-handler",
  97   "TrapHandler",
  98   "true",
  99   "Trap handler support"
 100 >;
 101
 102 def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
 103   "UnalignedScratchAccess",
 104   "true",
 105   "Support unaligned scratch loads and stores"
 106 >;
 107
 108 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
 109   "HasApertureRegs",
 110   "true",
 111   "Has Memory Aperture Base and Size Registers"
 112 >;
 113
 114 def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
 115   "HasMadMixInsts",
 116   "true",
 117   "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
 118 >;
 119
 120 def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
 121   "HasFmaMixInsts",
 122   "true",
 123   "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
 124 >;
 125
 126 def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
 127   "DoesNotSupportXNACK",
 128   "true",
 129   "Hardware does not support XNACK"
 130 >;
 131
 132 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 133 // XNACK. The current default kernel driver setting is:
 134 // - graphics ring: XNACK disabled
 135 // - compute ring: XNACK enabled
 136 //
 137 // If XNACK is enabled, the VMEM latency can be worse.
 138 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 139 def FeatureXNACK : SubtargetFeature<"xnack",
 140   "EnableXNACK",
 141   "true",
 142   "Enable XNACK support"
 143 >;
 144
 145 def FeatureCuMode : SubtargetFeature<"cumode",
 146   "EnableCuMode",
 147   "true",
 148   "Enable CU wavefront execution mode"
 149 >;
 150
 151 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 152   "SGPRInitBug",
 153   "true",
 154   "VI SGPR initialization bug requiring a fixed SGPR allocation size"
 155 >;
 156
 157 def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
 158   "LDSMisalignedBug",
 159   "true",
 160   "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
 161 >;
 162
 163 def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
 164   "HasMFMAInlineLiteralBug",
 165   "true",
 166   "MFMA cannot use inline literal as SrcC"
 167 >;
 168
 169 def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
 170   "HasVcmpxPermlaneHazard",
 171   "true",
 172   "TODO: describe me"
 173 >;
 174
 175 def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
 176   "HasVMEMtoScalarWriteHazard",
 177   "true",
 178   "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
 179 >;
 180
 181 def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
 182   "HasSMEMtoVectorWriteHazard",
 183   "true",
 184   "s_load_dword followed by v_cmp page faults"
 185 >;
 186
 187 def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
 188   "HasInstFwdPrefetchBug",
 189   "true",
 190   "S_INST_PREFETCH instruction causes shader to hang"
 191 >;
 192
 193 def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
 194   "HasVcmpxExecWARHazard",
 195   "true",
 196   "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
 197 >;
 198
 199 def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
 200   "HasLdsBranchVmemWARHazard",
 201   "true",
 202   "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
 203 >;
 204
 205 def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
 206   "HasNSAtoVMEMBug",
 207   "true",
 208   "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
 209 >;
 210
 211 def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
 212   "HasFlatSegmentOffsetBug",
 213   "true",
 214   "GFX10 bug, inst_offset ignored in flat segment"
 215 >;
 216
 217 def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
 218   "HasOffset3fBug",
 219   "true",
 220   "Branch offset of 3f hardware bug"
 221 >;
 222
 223 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 224   "ldsbankcount"#Value,
 225   "LDSBankCount",
 226   !cast<string>(Value),
 227   "The number of LDS banks per compute unit."
 228 >;
 229
 230 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 231 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 232
 233 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 234   "GCN3Encoding",
 235   "true",
 236   "Encoding format for VI"
 237 >;
 238
 239 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 240   "CIInsts",
 241   "true",
 242   "Additional instructions for CI+"
 243 >;
 244
 245 def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
 246   "GFX8Insts",
 247   "true",
 248   "Additional instructions for GFX8+"
 249 >;
 250
 251 def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
 252   "GFX9Insts",
 253   "true",
 254   "Additional instructions for GFX9+"
 255 >;
 256
 257 def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
 258   "GFX10Insts",
 259   "true",
 260   "Additional instructions for GFX10+"
 261 >;
 262
 263 def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
 264   "GFX10_3Insts",
 265   "true",
 266   "Additional instructions for GFX10.3"
 267 >;
 268
 269 def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
 270   "GFX7GFX8GFX9Insts",
 271   "true",
 272   "Instructions shared in GFX7, GFX8, GFX9"
 273 >;
 274
 275 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
 276   "HasSMemRealTime",
 277   "true",
 278   "Has s_memrealtime instruction"
 279 >;
 280
 281 def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
 282   "HasInv2PiInlineImm",
 283   "true",
 284   "Has 1 / (2 * pi) as inline immediate"
 285 >;
 286
 287 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
 288   "Has16BitInsts",
 289   "true",
 290   "Has i16/f16 instructions"
 291 >;
 292
 293 def FeatureVOP3P : SubtargetFeature<"vop3p",
 294   "HasVOP3PInsts",
 295   "true",
 296   "Has VOP3P packed instructions"
 297 >;
 298
 299 def FeatureMovrel : SubtargetFeature<"movrel",
 300   "HasMovrel",
 301   "true",
 302   "Has v_movrel*_b32 instructions"
 303 >;
 304
 305 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
 306   "HasVGPRIndexMode",
 307   "true",
 308   "Has VGPR mode register indexing"
 309 >;
 310
 311 def FeatureScalarStores : SubtargetFeature<"scalar-stores",
 312   "HasScalarStores",
 313   "true",
 314   "Has store scalar memory instructions"
 315 >;
 316
 317 def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
 318   "HasScalarAtomics",
 319   "true",
 320   "Has atomic scalar memory instructions"
 321 >;
 322
 323 def FeatureSDWA : SubtargetFeature<"sdwa",
 324   "HasSDWA",
 325   "true",
 326   "Support SDWA (Sub-DWORD Addressing) extension"
 327 >;
 328
 329 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
 330   "HasSDWAOmod",
 331   "true",
 332   "Support OMod with SDWA (Sub-DWORD Addressing) extension"
 333 >;
 334
 335 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
 336   "HasSDWAScalar",
 337   "true",
 338   "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
 339 >;
 340
 341 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
 342   "HasSDWASdst",
 343   "true",
 344   "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
 345 >;
 346
 347 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
 348   "HasSDWAMac",
 349   "true",
 350   "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
 351 >;
 352
 353 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
 354   "HasSDWAOutModsVOPC",
 355   "true",
 356   "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
 357 >;
 358
 359 def FeatureDPP : SubtargetFeature<"dpp",
 360   "HasDPP",
 361   "true",
 362   "Support DPP (Data Parallel Primitives) extension"
 363 >;
 364
 365 // DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
 366 def FeatureDPP8 : SubtargetFeature<"dpp8",
 367   "HasDPP8",
 368   "true",
 369   "Support DPP8 (Data Parallel Primitives) extension"
 370 >;
 371
 372 def FeatureR128A16 : SubtargetFeature<"r128-a16",
 373   "HasR128A16",
 374   "true",
 375   "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
 376 >;
 377
 378 def FeatureGFX10A16 : SubtargetFeature<"a16",
 379   "HasGFX10A16",
 380   "true",
 381   "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
 382 >;
 383
 384 def FeatureG16 : SubtargetFeature<"g16",
 385   "HasG16",
 386   "true",
 387   "Support G16 for 16-bit gradient image operands"
 388 >;
 389
 390 def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
 391   "HasNSAEncoding",
 392   "true",
 393   "Support NSA encoding for image instructions"
 394 >;
 395
 396 def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
 397   "GFX10_BEncoding",
 398   "true",
 399   "Encoding format GFX10_B"
 400 >;
 401
 402 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
 403   "HasIntClamp",
 404   "true",
 405   "Support clamp for integer destination"
 406 >;
 407
 408 def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
 409   "HasUnpackedD16VMem",
 410   "true",
 411   "Has unpacked d16 vmem instructions"
 412 >;
 413
 414 def FeatureDLInsts : SubtargetFeature<"dl-insts",
 415   "HasDLInsts",
 416   "true",
 417   "Has v_fmac_f32 and v_xnor_b32 instructions"
 418 >;
 419
 420 def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
 421   "HasDot1Insts",
 422   "true",
 423   "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
 424 >;
 425
 426 def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
 427   "HasDot2Insts",
 428   "true",
 429   "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
 430 >;
 431
 432 def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
 433   "HasDot3Insts",
 434   "true",
 435   "Has v_dot8c_i32_i4 instruction"
 436 >;
 437
 438 def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
 439   "HasDot4Insts",
 440   "true",
 441   "Has v_dot2c_i32_i16 instruction"
 442 >;
 443
 444 def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
 445   "HasDot5Insts",
 446   "true",
 447   "Has v_dot2c_f32_f16 instruction"
 448 >;
 449
 450 def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
 451   "HasDot6Insts",
 452   "true",
 453   "Has v_dot4c_i32_i8 instruction"
 454 >;
 455
 456 def FeatureMAIInsts : SubtargetFeature<"mai-insts",
 457   "HasMAIInsts",
 458   "true",
 459   "Has mAI instructions"
 460 >;
 461
 462 def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
 463   "HasPkFmacF16Inst",
 464   "true",
 465   "Has v_pk_fmac_f16 instruction"
 466 >;
 467
 468 def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
 469   "HasAtomicFaddInsts",
 470   "true",
 471   "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
 472   "global_atomic_pk_add_f16 instructions",
 473   [FeatureFlatGlobalInsts]
 474 >;
 475
 476 def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
 477   "DoesNotSupportSRAMECC",
 478   "true",
 479   "Hardware does not support SRAM ECC"
 480 >;
 481
 482 def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
 483   "EnableSRAMECC",
 484   "true",
 485   "Enable SRAM ECC"
 486 >;
 487
 488 def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
 489   "HasNoSdstCMPX",
 490   "true",
 491   "V_CMPX does not write VCC/SGPR in addition to EXEC"
 492 >;
 493
 494 def FeatureVscnt : SubtargetFeature<"vscnt",
 495   "HasVscnt",
 496   "true",
 497   "Has separate store vscnt counter"
 498 >;
 499
 500 def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
 501   "HasGetWaveIdInst",
 502   "true",
 503   "Has s_get_waveid_in_workgroup instruction"
 504 >;
 505
 506 def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
 507   "HasSMemTimeInst",
 508   "true",
 509   "Has s_memtime instruction"
 510 >;
 511
 512 def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
 513   "HasMadMacF32Insts",
 514   "true",
 515   "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
 516 >;
 517
 518 def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
 519   "HasDsSrc2Insts",
 520   "true",
 521   "Has ds_*_src2 instructions"
 522 >;
 523
 524 def FeatureRegisterBanking : SubtargetFeature<"register-banking",
 525   "HasRegisterBanking",
 526   "true",
 527   "Has register banking"
 528 >;
 529
 530 def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
 531   "HasVOP3Literal",
 532   "true",
 533   "Can use one literal in VOP3"
 534 >;
 535
 536 def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
 537   "HasNoDataDepHazard",
 538   "true",
 539   "Does not need SW waitstates"
 540 >;
 541
 542 //===------------------------------------------------------------===//
 543 // Subtarget Features (options and debugging)
 544 //===------------------------------------------------------------===//
 545
 546 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
 547   "max-private-element-size-"#size,
 548   "MaxPrivateElementSize",
 549   !cast<string>(size),
 550   "Maximum private access size may be "#size
 551 >;
 552
 553 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
 554 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
 555 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
 556
 557 def FeatureDumpCode : SubtargetFeature <"DumpCode",
 558   "DumpCode",
 559   "true",
 560   "Dump MachineInstrs in the CodeEmitter"
 561 >;
 562
 563 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
 564   "DumpCode",
 565   "true",
 566   "Dump MachineInstrs in the CodeEmitter"
 567 >;
 568
 569 // XXX - This should probably be removed once enabled by default
 570 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
 571   "EnableLoadStoreOpt",
 572   "true",
 573   "Enable SI load/store optimizer pass"
 574 >;
 575
 576 // Performance debugging feature. Allow using DS instruction immediate
 577 // offsets even if the base pointer can't be proven to be base. On SI,
 578 // base pointer values that won't give the same result as a 16-bit add
 579 // are not safe to fold, but this will override the conservative test
 580 // for the base pointer.
 581 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
 582   "unsafe-ds-offset-folding",
 583   "EnableUnsafeDSOffsetFolding",
 584   "true",
 585   "Force using DS instruction immediate offsets on SI"
 586 >;
 587
 588 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 589   "EnableSIScheduler",
 590   "true",
 591   "Enable SI Machine Scheduler"
 592 >;
 593
 594 def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
 595   "EnableDS128",
 596   "true",
 597   "Use ds_{read|write}_b128"
 598 >;
 599
 600 // Sparse texture support requires that all result registers are zeroed when
 601 // PRTStrictNull is set to true. This feature is turned on for all architectures
 602 // but is enabled as a feature in case there are situations where PRTStrictNull
 603 // is disabled by the driver.
 604 def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
 605   "EnablePRTStrictNull",
 606   "true",
 607   "Enable zeroing of result registers for sparse texture fetches"
 608 >;
 609
 610 // Unless +-flat-for-global is specified, turn on FlatForGlobal for
 611 // all OS-es on VI and newer hardware to avoid assertion failures due
 612 // to missing ADDR64 variants of MUBUF instructions.
 613 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
 614 // instructions.
 615
 616 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 617   "FlatForGlobal",
 618   "true",
 619   "Force to generate flat instruction for global"
 620 >;
 621
 622 def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
 623   "auto-waitcnt-before-barrier",
 624   "AutoWaitcntBeforeBarrier",
 625   "true",
 626   "Hardware automatically inserts waitcnt before barrier"
 627 >;
 628
 629 def FeatureCodeObjectV3 : SubtargetFeature <
 630   "code-object-v3",
 631   "CodeObjectV3",
 632   "true",
 633   "Generate code object version 3"
 634 >;
 635
 636 def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
 637   "HasTrigReducedRange",
 638   "true",
 639   "Requires use of fract on arguments to trig instructions"
 640 >;
 641
 642 // Dummy feature used to disable assembler instructions.
 643 def FeatureDisable : SubtargetFeature<"",
 644   "FeatureDisable","true",
 645   "Dummy feature to disable assembler instructions"
 646 >;
 647
 648 class GCNSubtargetFeatureGeneration <string Value,
 649                                      string FeatureName,
 650                                      list<SubtargetFeature> Implies> :
 651         SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
 652
 653 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 654     "southern-islands",
 655   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
 656   FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
 657   FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
 658   FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
 659   FeatureDoesNotSupportXNACK]
 660 >;
 661
 662 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
 663     "sea-islands",
 664   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 665   FeatureWavefrontSize64, FeatureFlatAddressSpace,
 666   FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
 667   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
 668   FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC]
 669 >;
 670
 671 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 672   "volcanic-islands",
 673   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 674    FeatureWavefrontSize64, FeatureFlatAddressSpace,
 675    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 676    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
 677    FeatureScalarStores, FeatureInv2PiInlineImm,
 678    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
 679    FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
 680    FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
 681    FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32
 682   ]
 683 >;
 684
 685 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
 686   "gfx9",
 687   [FeatureFP64, FeatureLocalMemorySize65536,
 688    FeatureWavefrontSize64, FeatureFlatAddressSpace,
 689    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 690    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
 691    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
 692    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 693    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 694    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 695    FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
 696    FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
 697    FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,
 698    FeatureFastDenormalF32
 699   ]
 700 >;
 701
 702 def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
 703   "gfx10",
 704   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 705    FeatureFlatAddressSpace,
 706    FeatureCIInsts, Feature16BitInsts,
 707    FeatureSMemRealTime, FeatureInv2PiInlineImm,
 708    FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
 709    FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 710    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 711    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 712    FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
 713    FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
 714    FeatureVOP3Literal, FeatureDPP8,
 715    FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
 716    FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16
 717   ]
 718 >;
 719
 720 class FeatureSet<list<SubtargetFeature> Features_> {
 721   list<SubtargetFeature> Features = Features_;
 722 }
 723
 724 def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
 725    FeatureFastFMAF32,
 726    HalfRate64Ops,
 727    FeatureLDSBankCount32,
 728    FeatureDoesNotSupportXNACK,
 729    FeatureCodeObjectV3]>;
 730
 731 def FeatureISAVersion6_0_1 : FeatureSet<
 732   [FeatureSouthernIslands,
 733    FeatureLDSBankCount32,
 734    FeatureDoesNotSupportXNACK,
 735    FeatureCodeObjectV3]>;
 736
 737 def FeatureISAVersion7_0_0 : FeatureSet<
 738   [FeatureSeaIslands,
 739    FeatureLDSBankCount32,
 740    FeatureDoesNotSupportXNACK,
 741    FeatureCodeObjectV3]>;
 742
 743 def FeatureISAVersion7_0_1 : FeatureSet<
 744   [FeatureSeaIslands,
 745    HalfRate64Ops,
 746    FeatureLDSBankCount32,
 747    FeatureFastFMAF32,
 748    FeatureDoesNotSupportXNACK,
 749    FeatureCodeObjectV3]>;
 750
 751 def FeatureISAVersion7_0_2 : FeatureSet<
 752   [FeatureSeaIslands,
 753    FeatureLDSBankCount16,
 754    FeatureFastFMAF32,
 755    FeatureDoesNotSupportXNACK,
 756    FeatureCodeObjectV3]>;
 757
 758 def FeatureISAVersion7_0_3 : FeatureSet<
 759   [FeatureSeaIslands,
 760    FeatureLDSBankCount16,
 761    FeatureDoesNotSupportXNACK,
 762    FeatureCodeObjectV3]>;
 763
 764 def FeatureISAVersion7_0_4 : FeatureSet<
 765   [FeatureSeaIslands,
 766    FeatureLDSBankCount32,
 767    FeatureDoesNotSupportXNACK,
 768    FeatureCodeObjectV3]>;
 769
 770 def FeatureISAVersion8_0_1 : FeatureSet<
 771   [FeatureVolcanicIslands,
 772    FeatureFastFMAF32,
 773    HalfRate64Ops,
 774    FeatureLDSBankCount32,
 775    FeatureXNACK,
 776    FeatureUnpackedD16VMem,
 777    FeatureCodeObjectV3]>;
 778
 779 def FeatureISAVersion8_0_2 : FeatureSet<
 780   [FeatureVolcanicIslands,
 781    FeatureLDSBankCount32,
 782    FeatureSGPRInitBug,
 783    FeatureUnpackedD16VMem,
 784    FeatureDoesNotSupportXNACK,
 785    FeatureCodeObjectV3]>;
 786
 787 def FeatureISAVersion8_0_3 : FeatureSet<
 788   [FeatureVolcanicIslands,
 789    FeatureLDSBankCount32,
 790    FeatureUnpackedD16VMem,
 791    FeatureDoesNotSupportXNACK,
 792    FeatureCodeObjectV3]>;
 793
 794 def FeatureISAVersion8_1_0 : FeatureSet<
 795   [FeatureVolcanicIslands,
 796    FeatureLDSBankCount16,
 797    FeatureXNACK,
 798    FeatureCodeObjectV3]>;
 799
 800 def FeatureISAVersion9_0_0 : FeatureSet<
 801   [FeatureGFX9,
 802    FeatureMadMixInsts,
 803    FeatureLDSBankCount32,
 804    FeatureCodeObjectV3,
 805    FeatureDoesNotSupportXNACK,
 806    FeatureDoesNotSupportSRAMECC]>;
 807
 808 def FeatureISAVersion9_0_2 : FeatureSet<
 809   [FeatureGFX9,
 810    FeatureMadMixInsts,
 811    FeatureLDSBankCount32,
 812    FeatureXNACK,
 813    FeatureDoesNotSupportSRAMECC,
 814    FeatureCodeObjectV3]>;
 815
 816 def FeatureISAVersion9_0_4 : FeatureSet<
 817   [FeatureGFX9,
 818    FeatureLDSBankCount32,
 819    FeatureFmaMixInsts,
 820    FeatureDoesNotSupportXNACK,
 821    FeatureDoesNotSupportSRAMECC,
 822    FeatureCodeObjectV3]>;
 823
 824 def FeatureISAVersion9_0_6 : FeatureSet<
 825   [FeatureGFX9,
 826    HalfRate64Ops,
 827    FeatureFmaMixInsts,
 828    FeatureLDSBankCount32,
 829    FeatureDLInsts,
 830    FeatureDot1Insts,
 831    FeatureDot2Insts,
 832    FeatureDoesNotSupportXNACK,
 833    FeatureCodeObjectV3]>;
 834
 835 def FeatureISAVersion9_0_8 : FeatureSet<
 836   [FeatureGFX9,
 837    HalfRate64Ops,
 838    FeatureFmaMixInsts,
 839    FeatureLDSBankCount32,
 840    FeatureDLInsts,
 841    FeatureDot1Insts,
 842    FeatureDot2Insts,
 843    FeatureDot3Insts,
 844    FeatureDot4Insts,
 845    FeatureDot5Insts,
 846    FeatureDot6Insts,
 847    FeatureMAIInsts,
 848    FeaturePkFmacF16Inst,
 849    FeatureAtomicFaddInsts,
 850    FeatureSRAMECC,
 851    FeatureMFMAInlineLiteralBug,
 852    FeatureCodeObjectV3]>;
 853
 854 def FeatureISAVersion9_0_9 : FeatureSet<
 855   [FeatureGFX9,
 856    FeatureMadMixInsts,
 857    FeatureLDSBankCount32,
 858    FeatureXNACK,
 859    FeatureCodeObjectV3]>;
 860
 861 // TODO: Organize more features into groups.
 862 def FeatureGroup {
 863   // Bugs present on gfx10.1.
 864   list<SubtargetFeature> GFX10_1_Bugs = [
 865     FeatureVcmpxPermlaneHazard,
 866     FeatureVMEMtoScalarWriteHazard,
 867     FeatureSMEMtoVectorWriteHazard,
 868     FeatureInstFwdPrefetchBug,
 869     FeatureVcmpxExecWARHazard,
 870     FeatureLdsBranchVmemWARHazard,
 871     FeatureNSAtoVMEMBug,
 872     FeatureOffset3fBug,
 873     FeatureFlatSegmentOffsetBug
 874    ];
 875 }
 876
 877 def FeatureISAVersion10_1_0 : FeatureSet<
 878   !listconcat(FeatureGroup.GFX10_1_Bugs,
 879     [FeatureGFX10,
 880      FeatureLDSBankCount32,
 881      FeatureDLInsts,
 882      FeatureNSAEncoding,
 883      FeatureWavefrontSize32,
 884      FeatureScalarStores,
 885      FeatureScalarAtomics,
 886      FeatureScalarFlatScratchInsts,
 887      FeatureGetWaveIdInst,
 888      FeatureSMemTimeInst,
 889      FeatureMadMacF32Insts,
 890      FeatureDsSrc2Insts,
 891      FeatureLdsMisalignedBug,
 892      FeatureDoesNotSupportXNACK,
 893      FeatureCodeObjectV3])>;
 894
 895 def FeatureISAVersion10_1_1 : FeatureSet<
 896   !listconcat(FeatureGroup.GFX10_1_Bugs,
 897     [FeatureGFX10,
 898      FeatureLDSBankCount32,
 899      FeatureDLInsts,
 900      FeatureDot1Insts,
 901      FeatureDot2Insts,
 902      FeatureDot5Insts,
 903      FeatureDot6Insts,
 904      FeatureNSAEncoding,
 905      FeatureWavefrontSize32,
 906      FeatureScalarStores,
 907      FeatureScalarAtomics,
 908      FeatureScalarFlatScratchInsts,
 909      FeatureGetWaveIdInst,
 910      FeatureSMemTimeInst,
 911      FeatureMadMacF32Insts,
 912      FeatureDsSrc2Insts,
 913      FeatureDoesNotSupportXNACK,
 914      FeatureCodeObjectV3])>;
 915
 916 def FeatureISAVersion10_1_2 : FeatureSet<
 917   !listconcat(FeatureGroup.GFX10_1_Bugs,
 918     [FeatureGFX10,
 919      FeatureLDSBankCount32,
 920      FeatureDLInsts,
 921      FeatureDot1Insts,
 922      FeatureDot2Insts,
 923      FeatureDot5Insts,
 924      FeatureDot6Insts,
 925      FeatureNSAEncoding,
 926      FeatureWavefrontSize32,
 927      FeatureScalarStores,
 928      FeatureScalarAtomics,
 929      FeatureScalarFlatScratchInsts,
 930      FeatureGetWaveIdInst,
 931      FeatureSMemTimeInst,
 932      FeatureMadMacF32Insts,
 933      FeatureDsSrc2Insts,
 934      FeatureLdsMisalignedBug,
 935      FeatureDoesNotSupportXNACK,
 936      FeatureCodeObjectV3])>;
 937
 938 def FeatureISAVersion10_3_0 : FeatureSet<
 939   [FeatureGFX10,
 940    FeatureGFX10_BEncoding,
 941    FeatureGFX10_3Insts,
 942    FeatureLDSBankCount32,
 943    FeatureDLInsts,
 944    FeatureDot1Insts,
 945    FeatureDot2Insts,
 946    FeatureDot5Insts,
 947    FeatureDot6Insts,
 948    FeatureNSAEncoding,
 949    FeatureWavefrontSize32,
 950    FeatureDoesNotSupportXNACK,
 951    FeatureCodeObjectV3]>;
 952
 953 //===----------------------------------------------------------------------===//
 954
 955 def AMDGPUInstrInfo : InstrInfo {
 956   let guessInstructionProperties = 1;
 957   let noNamedPositionallyEncodedOperands = 1;
 958 }
 959
 960 def AMDGPUAsmParser : AsmParser {
 961   // Some of the R600 registers have the same name, so this crashes.
 962   // For example T0_XYZW and T0_XY both have the asm name T0.
 963   let ShouldEmitMatchRegisterName = 0;
 964 }
 965
 966 def AMDGPUAsmWriter : AsmWriter {
 967   int PassSubtarget = 1;
 968 }
 969
 970 def AMDGPUAsmVariants {
 971   string Default = "Default";
 972   int Default_ID = 0;
 973   string VOP3 = "VOP3";
 974   int VOP3_ID = 1;
 975   string SDWA = "SDWA";
 976   int SDWA_ID = 2;
 977   string SDWA9 = "SDWA9";
 978   int SDWA9_ID = 3;
 979   string DPP = "DPP";
 980   int DPP_ID = 4;
 981   string Disable = "Disable";
 982   int Disable_ID = 5;
 983 }
 984
 985 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
 986   let Variant = AMDGPUAsmVariants.Default_ID;
 987   let Name = AMDGPUAsmVariants.Default;
 988 }
 989
 990 def VOP3AsmParserVariant : AsmParserVariant {
 991   let Variant = AMDGPUAsmVariants.VOP3_ID;
 992   let Name = AMDGPUAsmVariants.VOP3;
 993 }
 994
 995 def SDWAAsmParserVariant : AsmParserVariant {
 996   let Variant = AMDGPUAsmVariants.SDWA_ID;
 997   let Name = AMDGPUAsmVariants.SDWA;
 998 }
 999
1000 def SDWA9AsmParserVariant : AsmParserVariant {
1001   let Variant = AMDGPUAsmVariants.SDWA9_ID;
1002   let Name = AMDGPUAsmVariants.SDWA9;
1003 }
1004
1005
1006 def DPPAsmParserVariant : AsmParserVariant {
1007   let Variant = AMDGPUAsmVariants.DPP_ID;
1008   let Name = AMDGPUAsmVariants.DPP;
1009 }
1010
1011 def AMDGPU : Target {
1012   // Pull in Instruction Info:
1013   let InstructionSet = AMDGPUInstrInfo;
1014   let AssemblyParsers = [AMDGPUAsmParser];
1015   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1016                                 VOP3AsmParserVariant,
1017                                 SDWAAsmParserVariant,
1018                                 SDWA9AsmParserVariant,
1019                                 DPPAsmParserVariant];
1020   let AssemblyWriters = [AMDGPUAsmWriter];
1021   let AllowRegisterRenaming = 1;
1022 }
1023
1024 // Dummy Instruction itineraries for pseudo instructions
1025 def ALU_NULL : FuncUnit;
1026 def NullALU : InstrItinClass;
1027
1028 //===----------------------------------------------------------------------===//
1029 // Predicate helper class
1030 //===----------------------------------------------------------------------===//
1031
1032 def isGFX6 :
1033   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1034   AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1035
1036 def isGFX6GFX7 :
1037   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1038             "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1039   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1040
1041 def isGFX6GFX7GFX10 :
1042   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1043             "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1044             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1045   AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1046
1047 def isGFX7Only :
1048   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1049   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1050
1051 def isGFX7GFX10 :
1052   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1053             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1054   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1055
1056 def isGFX7GFX8GFX9 :
1057   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1058             "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1059             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1060   AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1061
1062 def isGFX6GFX7GFX8GFX9 :
1063   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1064             "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1065             "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1066             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1067   AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1068
1069 def isGFX7Plus :
1070   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1071   AssemblerPredicate<(all_of FeatureCIInsts)>;
1072
1073 def isGFX8Plus :
1074   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1075   AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1076
1077 def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1078                            "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1079   AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1080
1081 def isGFX9Plus :
1082   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1083   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1084
1085 def isGFX9Only : Predicate <
1086   "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1087   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1088
1089 def isGFX8GFX9 :
1090   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1091             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1092   AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1093
1094 def isGFX10Plus :
1095   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1096   AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1097
1098 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1099   AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1100
1101 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1102   AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1103 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1104   AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1105 def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1106   AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1107 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1108   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1109
1110 def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1111   AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1112
1113 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1114   AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1115 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1116   AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1117
1118 def D16PreservesUnusedBits :
1119   Predicate<"Subtarget->d16PreservesUnusedBits()">,
1120   AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1121
1122 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1123 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1124
1125 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1126   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1127
1128 def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1129   AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1130
1131 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1132   AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1133
1134 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1135
1136 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1137   AssemblerPredicate<(all_of Feature16BitInsts)>;
1138 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1139   AssemblerPredicate<(all_of FeatureVOP3P)>;
1140
1141 def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1142 def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1143
1144 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1145   AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1146
1147 def HasSDWA9 :
1148   Predicate<"Subtarget->hasSDWA()">,
1149   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1150
1151 def HasSDWA10 :
1152   Predicate<"Subtarget->hasSDWA()">,
1153   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1154
1155 def HasDPP : Predicate<"Subtarget->hasDPP()">,
1156   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1157
1158 def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1159   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1160
1161 def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1162   AssemblerPredicate<(all_of FeatureR128A16)>;
1163
1164 def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1165   AssemblerPredicate<(all_of FeatureGFX10A16)>;
1166
1167 def HasG16 : Predicate<"Subtarget->hasG16()">,
1168   AssemblerPredicate<(all_of FeatureG16)>;
1169
1170 def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1171   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1172
1173 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1174   AssemblerPredicate<(all_of FeatureIntClamp)>;
1175
1176 def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1177   AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1178
1179 def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1180   AssemblerPredicate<(all_of FeatureScalarStores)>;
1181
1182 def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1183   AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1184
1185 def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1186   AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1187
1188 def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1189   AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1190
1191 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1192 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1193 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1194                       AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1195 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1196                 AssemblerPredicate<(all_of FeatureMovrel)>;
1197
1198 def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1199   AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1200
1201 def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1202   AssemblerPredicate<(all_of FeatureDLInsts)>;
1203
1204 def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1205   AssemblerPredicate<(all_of FeatureDot1Insts)>;
1206
1207 def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1208   AssemblerPredicate<(all_of FeatureDot2Insts)>;
1209
1210 def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1211   AssemblerPredicate<(all_of FeatureDot3Insts)>;
1212
1213 def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1214   AssemblerPredicate<(all_of FeatureDot4Insts)>;
1215
1216 def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1217   AssemblerPredicate<(all_of FeatureDot5Insts)>;
1218
1219 def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1220   AssemblerPredicate<(all_of FeatureDot6Insts)>;
1221
1222 def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1223   AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1224
1225 def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1226   AssemblerPredicate<(all_of FeatureMAIInsts)>;
1227
1228 def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1229   AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1230
1231 def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">;
1232
1233 def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1234   AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1235
1236 def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1237   AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1238
1239 def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1240   AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1241
1242 def HasNoMadMacF32Insts : Predicate<"!Subtarget->hasMadMacF32Insts()">,
1243   AssemblerPredicate<(all_of (not FeatureMadMacF32Insts))>;
1244
1245 def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1246   AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1247
1248 def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1249   AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1250
1251 def EnableLateCFGStructurize : Predicate<
1252   "EnableLateStructurizeCFG">;
1253
1254 // Include AMDGPU TD files
1255 include "SISchedule.td"
1256 include "GCNProcessors.td"
1257 include "AMDGPUInstrInfo.td"
1258 include "SIRegisterInfo.td"
1259 include "AMDGPURegisterBanks.td"
1260 include "AMDGPUInstructions.td"
1261 include "SIInstrInfo.td"
1262 include "AMDGPUCallingConv.td"
1263 include "AMDGPUSearchableTables.td"