1 //==- AMDGPUArgumentrUsageInfo.h - Function Arg Usage Info -------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
12 #include "llvm/ADT/DenseMap.h"
13 #include "llvm/CodeGen/Register.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Support/LowLevelTypeImpl.h"
21 class TargetRegisterClass;
22 class TargetRegisterInfo;
24 struct ArgDescriptor {
26 friend struct AMDGPUFunctionArgInfo;
27 friend class AMDGPUArgumentUsageInfo;
34 // Bitmask to locate argument within the register.
41 constexpr ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u,
42 bool IsStack = false, bool IsSet = false)
43 : Reg(Val), Mask(Mask), IsStack(IsStack), IsSet(IsSet) {}
45 static constexpr ArgDescriptor createRegister(Register Reg,
46 unsigned Mask = ~0u) {
47 return ArgDescriptor(Reg, Mask, false, true);
50 static constexpr ArgDescriptor createStack(unsigned Offset,
51 unsigned Mask = ~0u) {
52 return ArgDescriptor(Offset, Mask, true, true);
55 static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg,
57 return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet);
64 explicit operator bool() const {
68 bool isRegister() const {
72 Register getRegister() const {
77 unsigned getStackOffset() const {
82 unsigned getMask() const {
86 bool isMasked() const {
90 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const;
93 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) {
98 struct AMDGPUFunctionArgInfo {
101 PRIVATE_SEGMENT_BUFFER = 0,
104 KERNARG_SEGMENT_PTR = 3,
106 FLAT_SCRATCH_INIT = 5,
110 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
111 IMPLICIT_BUFFER_PTR = 15,
112 IMPLICIT_ARG_PTR = 16,
118 FIRST_VGPR_VALUE = WORKITEM_ID_X
121 // Kernel input registers setup for the HSA ABI in allocation order.
123 // User SGPRs in kernels
124 // XXX - Can these require argument spills?
125 ArgDescriptor PrivateSegmentBuffer;
126 ArgDescriptor DispatchPtr;
127 ArgDescriptor QueuePtr;
128 ArgDescriptor KernargSegmentPtr;
129 ArgDescriptor DispatchID;
130 ArgDescriptor FlatScratchInit;
131 ArgDescriptor PrivateSegmentSize;
133 // System SGPRs in kernels.
134 ArgDescriptor WorkGroupIDX;
135 ArgDescriptor WorkGroupIDY;
136 ArgDescriptor WorkGroupIDZ;
137 ArgDescriptor WorkGroupInfo;
138 ArgDescriptor PrivateSegmentWaveByteOffset;
140 // Pointer with offset from kernargsegmentptr to where special ABI arguments
141 // are passed to callable functions.
142 ArgDescriptor ImplicitArgPtr;
144 // Input registers for non-HSA ABI
145 ArgDescriptor ImplicitBufferPtr;
147 // VGPRs inputs. These are always v0, v1 and v2 for entry functions.
148 ArgDescriptor WorkItemIDX;
149 ArgDescriptor WorkItemIDY;
150 ArgDescriptor WorkItemIDZ;
152 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
153 getPreloadedValue(PreloadedValue Value) const;
155 static constexpr AMDGPUFunctionArgInfo fixedABILayout();
158 class AMDGPUArgumentUsageInfo : public ImmutablePass {
160 DenseMap<const Function *, AMDGPUFunctionArgInfo> ArgInfoMap;
165 static const AMDGPUFunctionArgInfo ExternFunctionInfo;
166 static const AMDGPUFunctionArgInfo FixedABIFunctionInfo;
168 AMDGPUArgumentUsageInfo() : ImmutablePass(ID) { }
170 void getAnalysisUsage(AnalysisUsage &AU) const override {
171 AU.setPreservesAll();
174 bool doInitialization(Module &M) override;
175 bool doFinalization(Module &M) override;
177 void print(raw_ostream &OS, const Module *M = nullptr) const override;
179 void setFuncArgInfo(const Function &F, const AMDGPUFunctionArgInfo &ArgInfo) {
180 ArgInfoMap[&F] = ArgInfo;
183 const AMDGPUFunctionArgInfo &lookupFuncArgInfo(const Function &F) const;
186 } // end namespace llvm