1 //==- AMDGPUArgumentrUsageInfo.h - Function Arg Usage Info -------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
12 #include "llvm/ADT/DenseMap.h"
13 #include "llvm/CodeGen/Register.h"
14 #include "llvm/IR/Function.h"
15 #include "llvm/Pass.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 struct ArgDescriptor {
28 friend struct AMDGPUFunctionArgInfo;
29 friend class AMDGPUArgumentUsageInfo;
36 // Bitmask to locate argument within the register.
43 ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u,
44 bool IsStack = false, bool IsSet = false)
45 : Reg(Val), Mask(Mask), IsStack(IsStack), IsSet(IsSet) {}
47 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) {
48 return ArgDescriptor(Reg, Mask, false, true);
51 static ArgDescriptor createStack(unsigned Offset, unsigned Mask = ~0u) {
52 return ArgDescriptor(Offset, Mask, true, true);
55 static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) {
56 return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet);
63 explicit operator bool() const {
67 bool isRegister() const {
71 Register getRegister() const {
76 unsigned getStackOffset() const {
81 unsigned getMask() const {
85 bool isMasked() const {
89 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const;
92 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) {
97 struct AMDGPUFunctionArgInfo {
100 PRIVATE_SEGMENT_BUFFER = 0,
103 KERNARG_SEGMENT_PTR = 3,
105 FLAT_SCRATCH_INIT = 5,
109 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
110 IMPLICIT_BUFFER_PTR = 15,
111 IMPLICIT_ARG_PTR = 16,
117 FIRST_VGPR_VALUE = WORKITEM_ID_X
120 // Kernel input registers setup for the HSA ABI in allocation order.
122 // User SGPRs in kernels
123 // XXX - Can these require argument spills?
124 ArgDescriptor PrivateSegmentBuffer;
125 ArgDescriptor DispatchPtr;
126 ArgDescriptor QueuePtr;
127 ArgDescriptor KernargSegmentPtr;
128 ArgDescriptor DispatchID;
129 ArgDescriptor FlatScratchInit;
130 ArgDescriptor PrivateSegmentSize;
132 // System SGPRs in kernels.
133 ArgDescriptor WorkGroupIDX;
134 ArgDescriptor WorkGroupIDY;
135 ArgDescriptor WorkGroupIDZ;
136 ArgDescriptor WorkGroupInfo;
137 ArgDescriptor PrivateSegmentWaveByteOffset;
139 // Pointer with offset from kernargsegmentptr to where special ABI arguments
140 // are passed to callable functions.
141 ArgDescriptor ImplicitArgPtr;
143 // Input registers for non-HSA ABI
144 ArgDescriptor ImplicitBufferPtr = 0;
146 // VGPRs inputs. These are always v0, v1 and v2 for entry functions.
147 ArgDescriptor WorkItemIDX;
148 ArgDescriptor WorkItemIDY;
149 ArgDescriptor WorkItemIDZ;
151 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
152 getPreloadedValue(PreloadedValue Value) const;
155 class AMDGPUArgumentUsageInfo : public ImmutablePass {
157 static const AMDGPUFunctionArgInfo ExternFunctionInfo;
158 DenseMap<const Function *, AMDGPUFunctionArgInfo> ArgInfoMap;
163 AMDGPUArgumentUsageInfo() : ImmutablePass(ID) { }
165 void getAnalysisUsage(AnalysisUsage &AU) const override {
166 AU.setPreservesAll();
169 bool doInitialization(Module &M) override;
170 bool doFinalization(Module &M) override;
172 void print(raw_ostream &OS, const Module *M = nullptr) const override;
174 void setFuncArgInfo(const Function &F, const AMDGPUFunctionArgInfo &ArgInfo) {
175 ArgInfoMap[&F] = ArgInfo;
178 const AMDGPUFunctionArgInfo &lookupFuncArgInfo(const Function &F) const {
179 auto I = ArgInfoMap.find(&F);
180 if (I == ArgInfoMap.end()) {
181 assert(F.isDeclaration());
182 return ExternFunctionInfo;
189 } // end namespace llvm