1 //===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for the AMD Radeon GPUs.
11 //===----------------------------------------------------------------------===//
13 // Inversion of CCIfInReg
14 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
15 class CCIfExtend<CCAction A>
16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
18 // Calling convention for SI
19 def CC_SI : CallingConv<[
21 CCIfInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
22 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
23 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
24 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
25 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
26 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
27 SGPR40, SGPR41, SGPR42, SGPR43, SGPR44, SGPR45, SGPR46, SGPR47,
28 SGPR48, SGPR49, SGPR50, SGPR51, SGPR52, SGPR53, SGPR54, SGPR55,
29 SGPR56, SGPR57, SGPR58, SGPR59, SGPR60, SGPR61, SGPR62, SGPR63,
30 SGPR64, SGPR65, SGPR66, SGPR67, SGPR68, SGPR69, SGPR70, SGPR71,
31 SGPR72, SGPR73, SGPR74, SGPR75, SGPR76, SGPR77, SGPR78, SGPR79,
32 SGPR80, SGPR81, SGPR82, SGPR83, SGPR84, SGPR85, SGPR86, SGPR87,
33 SGPR88, SGPR89, SGPR90, SGPR91, SGPR92, SGPR93, SGPR94, SGPR95,
34 SGPR96, SGPR97, SGPR98, SGPR99, SGPR100, SGPR101, SGPR102, SGPR103,
38 // We have no way of referring to the generated register tuples
39 // here, so use a custom function.
40 CCIfInReg<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>,
41 CCIfByVal<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>,
43 // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
44 CCIfNotInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
45 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
46 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
47 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
48 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
49 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
50 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
51 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
52 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
53 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
54 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
55 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
56 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
57 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
58 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
59 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
60 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
61 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
65 def RetCC_SI_Shader : CallingConv<[
66 CCIfType<[i32] , CCAssignToReg<[
67 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
68 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
69 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
70 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
71 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
72 SGPR40, SGPR41, SGPR42, SGPR43, SGPR44, SGPR45, SGPR46, SGPR47,
73 SGPR48, SGPR49, SGPR50, SGPR51, SGPR52, SGPR53, SGPR54, SGPR55,
74 SGPR56, SGPR57, SGPR58, SGPR59, SGPR60, SGPR61, SGPR62, SGPR63,
75 SGPR64, SGPR65, SGPR66, SGPR67, SGPR68, SGPR69, SGPR70, SGPR71,
76 SGPR72, SGPR73, SGPR74, SGPR75, SGPR76, SGPR77, SGPR78, SGPR79,
77 SGPR80, SGPR81, SGPR82, SGPR83, SGPR84, SGPR85, SGPR86, SGPR87,
78 SGPR88, SGPR89, SGPR90, SGPR91, SGPR92, SGPR93, SGPR94, SGPR95,
79 SGPR96, SGPR97, SGPR98, SGPR99, SGPR100, SGPR101, SGPR102, SGPR103,
83 // 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
84 CCIfType<[f32, f16, v2f16] , CCAssignToReg<[
85 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
86 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
87 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
88 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
89 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
90 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
91 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
92 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
93 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
94 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
95 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
96 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
97 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
98 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
99 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
100 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
101 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
105 def CSR_AMDGPU_VGPRs_24_255 : CalleeSavedRegs<
106 (sequence "VGPR%u", 24, 255)
109 def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs<
110 (sequence "VGPR%u", 32, 255)
113 def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
114 (sequence "SGPR%u", 32, 105)
117 // Just to get the regmask, not for calling convention purposes.
118 def CSR_AMDGPU_AllVGPRs : CalleeSavedRegs<
119 (sequence "VGPR%u", 0, 255)
122 // Just to get the regmask, not for calling convention purposes.
123 def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs<
124 (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
127 def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
128 (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_105)
131 // Calling convention for leaf functions
132 def CC_AMDGPU_Func : CallingConv<[
133 CCIfByVal<CCPassByVal<4, 4>>,
134 CCIfType<[i1], CCPromoteToType<i32>>,
135 CCIfType<[i1, i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
136 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
137 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
138 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
139 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
140 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
141 CCIfType<[i64, f64, v2i32, v2f32, v3i32, v3f32, v4i32, v4f32, v5i32, v5f32, v8i32, v8f32, v16i32, v16f32, v2i64, v2f64, v4i16, v4f16], CCCustom<"allocateVGPRTuple">>,
142 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
143 CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,
144 CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
145 CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,
146 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
147 CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
148 CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
151 // Calling convention for leaf functions
152 def RetCC_AMDGPU_Func : CallingConv<[
153 CCIfType<[i1], CCPromoteToType<i32>>,
154 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
155 CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
156 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
157 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
158 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
159 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
160 CCIfType<[i64, f64, v2i32, v2f32, v4i32, v4f32, v8i32, v8f32, v16i32, v16f32, v2i64, v2f64, v4i16, v4f16], CCCustom<"allocateVGPRTuple">>
163 def CC_AMDGPU : CallingConv<[
164 CCIf<"static_cast<const GCNSubtarget&>"
165 "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
166 "AMDGPUSubtarget::SOUTHERN_ISLANDS",
167 CCDelegateTo<CC_SI>>,
168 CCIf<"static_cast<const GCNSubtarget&>"
169 "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
170 "AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C",
171 CCDelegateTo<CC_AMDGPU_Func>>