contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

   1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the InstructionSelector class for
  10 /// AMDGPU.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
  14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
  15
  16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  17 #include "llvm/IR/InstrTypes.h"
  18
  19 namespace {
  20 #define GET_GLOBALISEL_PREDICATE_BITSET
  21 #define AMDGPUSubtarget GCNSubtarget
  22 #include "AMDGPUGenGlobalISel.inc"
  23 #undef GET_GLOBALISEL_PREDICATE_BITSET
  24 #undef AMDGPUSubtarget
  25 }
  26
  27 namespace llvm {
  28
  29 namespace AMDGPU {
  30 struct ImageDimIntrinsicInfo;
  31 }
  32
  33 class AMDGPURegisterBankInfo;
  34 class AMDGPUTargetMachine;
  35 class BlockFrequencyInfo;
  36 class ProfileSummaryInfo;
  37 class GCNSubtarget;
  38 class MachineInstr;
  39 class MachineIRBuilder;
  40 class MachineOperand;
  41 class MachineRegisterInfo;
  42 class RegisterBank;
  43 class SIInstrInfo;
  44 class SIRegisterInfo;
  45 class TargetRegisterClass;
  46
  47 class AMDGPUInstructionSelector final : public InstructionSelector {
  48 private:
  49   MachineRegisterInfo *MRI;
  50   const GCNSubtarget *Subtarget;
  51
  52 public:
  53   AMDGPUInstructionSelector(const GCNSubtarget &STI,
  54                             const AMDGPURegisterBankInfo &RBI,
  55                             const AMDGPUTargetMachine &TM);
  56
  57   bool select(MachineInstr &I) override;
  58   static const char *getName();
  59
  60   void setupMF(MachineFunction &MF, GISelKnownBits *KB,
  61                CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI,
  62                BlockFrequencyInfo *BFI) override;
  63
  64 private:
  65   struct GEPInfo {
  66     SmallVector<unsigned, 2> SgprParts;
  67     SmallVector<unsigned, 2> VgprParts;
  68     int64_t Imm = 0;
  69   };
  70
  71   bool isSGPR(Register Reg) const;
  72
  73   bool isInstrUniform(const MachineInstr &MI) const;
  74   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
  75
  76   const RegisterBank *getArtifactRegBank(
  77     Register Reg, const MachineRegisterInfo &MRI,
  78     const TargetRegisterInfo &TRI) const;
  79
  80   /// tblgen-erated 'select' implementation.
  81   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
  82
  83   MachineOperand getSubOperand64(MachineOperand &MO,
  84                                  const TargetRegisterClass &SubRC,
  85                                  unsigned SubIdx) const;
  86
  87   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
  88   bool selectCOPY(MachineInstr &I) const;
  89   bool selectPHI(MachineInstr &I) const;
  90   bool selectG_TRUNC(MachineInstr &I) const;
  91   bool selectG_SZA_EXT(MachineInstr &I) const;
  92   bool selectG_CONSTANT(MachineInstr &I) const;
  93   bool selectG_FNEG(MachineInstr &I) const;
  94   bool selectG_FABS(MachineInstr &I) const;
  95   bool selectG_AND_OR_XOR(MachineInstr &I) const;
  96   bool selectG_ADD_SUB(MachineInstr &I) const;
  97   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
  98   bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
  99   bool selectG_EXTRACT(MachineInstr &I) const;
 100   bool selectG_MERGE_VALUES(MachineInstr &I) const;
 101   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
 102   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
 103   bool selectG_PTR_ADD(MachineInstr &I) const;
 104   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
 105   bool selectG_INSERT(MachineInstr &I) const;
 106   bool selectG_SBFX_UBFX(MachineInstr &I) const;
 107
 108   bool selectInterpP1F16(MachineInstr &MI) const;
 109   bool selectWritelane(MachineInstr &MI) const;
 110   bool selectDivScale(MachineInstr &MI) const;
 111   bool selectIntrinsicIcmp(MachineInstr &MI) const;
 112   bool selectBallot(MachineInstr &I) const;
 113   bool selectRelocConstant(MachineInstr &I) const;
 114   bool selectGroupStaticSize(MachineInstr &I) const;
 115   bool selectReturnAddress(MachineInstr &I) const;
 116   bool selectG_INTRINSIC(MachineInstr &I) const;
 117
 118   bool selectEndCfIntrinsic(MachineInstr &MI) const;
 119   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
 120   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
 121   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
 122   bool selectSBarrier(MachineInstr &MI) const;
 123
 124   bool selectImageIntrinsic(MachineInstr &MI,
 125                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
 126   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
 127   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
 128   bool selectG_ICMP(MachineInstr &I) const;
 129   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
 130   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
 131                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
 132
 133   void initM0(MachineInstr &I) const;
 134   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
 135   bool selectG_SELECT(MachineInstr &I) const;
 136   bool selectG_BRCOND(MachineInstr &I) const;
 137   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
 138   bool selectG_PTRMASK(MachineInstr &I) const;
 139   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
 140   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
 141   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
 142   bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
 143   bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
 144                               MachineOperand &DataOp) const;
 145   bool selectBufferLoadLds(MachineInstr &MI) const;
 146   bool selectGlobalLoadLds(MachineInstr &MI) const;
 147   bool selectBVHIntrinsic(MachineInstr &I) const;
 148   bool selectSMFMACIntrin(MachineInstr &I) const;
 149   bool selectWaveAddress(MachineInstr &I) const;
 150
 151   std::pair<Register, unsigned>
 152   selectVOP3ModsImpl(MachineOperand &Root, bool AllowAbs = true,
 153                      bool OpSel = false, bool ForceVGPR = false) const;
 154
 155   InstructionSelector::ComplexRendererFns
 156   selectVCSRC(MachineOperand &Root) const;
 157
 158   InstructionSelector::ComplexRendererFns
 159   selectVSRC0(MachineOperand &Root) const;
 160
 161   InstructionSelector::ComplexRendererFns
 162   selectVOP3Mods0(MachineOperand &Root) const;
 163   InstructionSelector::ComplexRendererFns
 164   selectVOP3BMods0(MachineOperand &Root) const;
 165   InstructionSelector::ComplexRendererFns
 166   selectVOP3OMods(MachineOperand &Root) const;
 167   InstructionSelector::ComplexRendererFns
 168   selectVOP3Mods(MachineOperand &Root) const;
 169   InstructionSelector::ComplexRendererFns
 170   selectVOP3BMods(MachineOperand &Root) const;
 171
 172   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
 173
 174   InstructionSelector::ComplexRendererFns
 175   selectVOP3Mods_nnan(MachineOperand &Root) const;
 176
 177   std::pair<Register, unsigned>
 178   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
 179                       bool IsDOT = false) const;
 180
 181   InstructionSelector::ComplexRendererFns
 182   selectVOP3PMods(MachineOperand &Root) const;
 183
 184   InstructionSelector::ComplexRendererFns
 185   selectVOP3PModsDOT(MachineOperand &Root) const;
 186
 187   InstructionSelector::ComplexRendererFns
 188   selectDotIUVOP3PMods(MachineOperand &Root) const;
 189
 190   InstructionSelector::ComplexRendererFns
 191   selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
 192
 193   InstructionSelector::ComplexRendererFns
 194   selectVOP3OpSelMods(MachineOperand &Root) const;
 195
 196   InstructionSelector::ComplexRendererFns
 197   selectVINTERPMods(MachineOperand &Root) const;
 198   InstructionSelector::ComplexRendererFns
 199   selectVINTERPModsHi(MachineOperand &Root) const;
 200
 201   bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
 202                         int64_t *Offset) const;
 203   InstructionSelector::ComplexRendererFns
 204   selectSmrdImm(MachineOperand &Root) const;
 205   InstructionSelector::ComplexRendererFns
 206   selectSmrdImm32(MachineOperand &Root) const;
 207   InstructionSelector::ComplexRendererFns
 208   selectSmrdSgpr(MachineOperand &Root) const;
 209   InstructionSelector::ComplexRendererFns
 210   selectSmrdSgprImm(MachineOperand &Root) const;
 211
 212   std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
 213                                                 uint64_t FlatVariant) const;
 214
 215   InstructionSelector::ComplexRendererFns
 216   selectFlatOffset(MachineOperand &Root) const;
 217   InstructionSelector::ComplexRendererFns
 218   selectGlobalOffset(MachineOperand &Root) const;
 219   InstructionSelector::ComplexRendererFns
 220   selectScratchOffset(MachineOperand &Root) const;
 221
 222   InstructionSelector::ComplexRendererFns
 223   selectGlobalSAddr(MachineOperand &Root) const;
 224
 225   InstructionSelector::ComplexRendererFns
 226   selectScratchSAddr(MachineOperand &Root) const;
 227   bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
 228                                      uint64_t ImmOffset) const;
 229   InstructionSelector::ComplexRendererFns
 230   selectScratchSVAddr(MachineOperand &Root) const;
 231
 232   InstructionSelector::ComplexRendererFns
 233   selectMUBUFScratchOffen(MachineOperand &Root) const;
 234   InstructionSelector::ComplexRendererFns
 235   selectMUBUFScratchOffset(MachineOperand &Root) const;
 236
 237   bool isDSOffsetLegal(Register Base, int64_t Offset) const;
 238   bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
 239                         unsigned Size) const;
 240
 241   std::pair<Register, unsigned>
 242   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
 243   InstructionSelector::ComplexRendererFns
 244   selectDS1Addr1Offset(MachineOperand &Root) const;
 245
 246   InstructionSelector::ComplexRendererFns
 247   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
 248
 249   InstructionSelector::ComplexRendererFns
 250   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
 251
 252   std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
 253                                                        unsigned size) const;
 254   InstructionSelector::ComplexRendererFns
 255   selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
 256
 257   std::pair<Register, int64_t>
 258   getPtrBaseWithConstantOffset(Register Root,
 259                                const MachineRegisterInfo &MRI) const;
 260
 261   // Parse out a chain of up to two g_ptr_add instructions.
 262   // g_ptr_add (n0, _)
 263   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
 264   struct MUBUFAddressData {
 265     Register N0, N2, N3;
 266     int64_t Offset = 0;
 267   };
 268
 269   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
 270
 271   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
 272                                Register &SOffset, int64_t &ImmOffset) const;
 273
 274   MUBUFAddressData parseMUBUFAddress(Register Src) const;
 275
 276   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
 277                              Register &RSrcReg, Register &SOffset,
 278                              int64_t &Offset) const;
 279
 280   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
 281                              Register &SOffset, int64_t &Offset) const;
 282
 283   InstructionSelector::ComplexRendererFns
 284   selectMUBUFAddr64(MachineOperand &Root) const;
 285
 286   InstructionSelector::ComplexRendererFns
 287   selectMUBUFOffset(MachineOperand &Root) const;
 288
 289   InstructionSelector::ComplexRendererFns
 290   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
 291
 292   InstructionSelector::ComplexRendererFns
 293   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
 294
 295   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
 296   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
 297
 298   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
 299                         int OpIdx = -1) const;
 300
 301   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
 302                        int OpIdx) const;
 303
 304   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
 305                        int OpIdx) const;
 306
 307   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
 308                         int OpIdx) const;
 309
 310   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
 311                        int OpIdx) const;
 312   void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
 313                          int OpIdx) const;
 314   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
 315                         int OpIdx) const;
 316   void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
 317                     int OpIdx) const;
 318
 319   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
 320                         int OpIdx) const;
 321
 322   bool isInlineImmediate16(int64_t Imm) const;
 323   bool isInlineImmediate32(int64_t Imm) const;
 324   bool isInlineImmediate64(int64_t Imm) const;
 325   bool isInlineImmediate(const APFloat &Imm) const;
 326
 327   // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
 328   // shift amount operand's `ShAmtBits` bits is unneeded.
 329   bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
 330
 331   const SIInstrInfo &TII;
 332   const SIRegisterInfo &TRI;
 333   const AMDGPURegisterBankInfo &RBI;
 334   const AMDGPUTargetMachine &TM;
 335   const GCNSubtarget &STI;
 336   bool EnableLateStructurizeCFG;
 337 #define GET_GLOBALISEL_PREDICATES_DECL
 338 #define AMDGPUSubtarget GCNSubtarget
 339 #include "AMDGPUGenGlobalISel.inc"
 340 #undef GET_GLOBALISEL_PREDICATES_DECL
 341 #undef AMDGPUSubtarget
 342
 343 #define GET_GLOBALISEL_TEMPORARIES_DECL
 344 #include "AMDGPUGenGlobalISel.inc"
 345 #undef GET_GLOBALISEL_TEMPORARIES_DECL
 346 };
 347
 348 } // End llvm namespace.
 349 #endif