1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares the targeting of the InstructionSelector class for
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
34 class AMDGPUInstrInfo;
35 class AMDGPURegisterBankInfo;
38 class MachineIRBuilder;
40 class MachineRegisterInfo;
43 class SIMachineFunctionInfo;
46 class AMDGPUInstructionSelector : public InstructionSelector {
48 MachineRegisterInfo *MRI;
51 AMDGPUInstructionSelector(const GCNSubtarget &STI,
52 const AMDGPURegisterBankInfo &RBI,
53 const AMDGPUTargetMachine &TM);
55 bool select(MachineInstr &I) override;
56 static const char *getName();
58 void setupMF(MachineFunction &MF, GISelKnownBits &KB,
59 CodeGenCoverage &CoverageInfo) override;
63 const MachineInstr &GEP;
64 SmallVector<unsigned, 2> SgprParts;
65 SmallVector<unsigned, 2> VgprParts;
67 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
70 bool isInstrUniform(const MachineInstr &MI) const;
71 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
73 const RegisterBank *getArtifactRegBank(
74 Register Reg, const MachineRegisterInfo &MRI,
75 const TargetRegisterInfo &TRI) const;
77 /// tblgen-erated 'select' implementation.
78 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
80 MachineOperand getSubOperand64(MachineOperand &MO,
81 const TargetRegisterClass &SubRC,
82 unsigned SubIdx) const;
83 bool selectCOPY(MachineInstr &I) const;
84 bool selectPHI(MachineInstr &I) const;
85 bool selectG_TRUNC(MachineInstr &I) const;
86 bool selectG_SZA_EXT(MachineInstr &I) const;
87 bool selectG_CONSTANT(MachineInstr &I) const;
88 bool selectG_AND_OR_XOR(MachineInstr &I) const;
89 bool selectG_ADD_SUB(MachineInstr &I) const;
90 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
91 bool selectG_EXTRACT(MachineInstr &I) const;
92 bool selectG_MERGE_VALUES(MachineInstr &I) const;
93 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
94 bool selectG_PTR_ADD(MachineInstr &I) const;
95 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
96 bool selectG_INSERT(MachineInstr &I) const;
97 bool selectG_INTRINSIC(MachineInstr &I) const;
99 std::tuple<Register, unsigned, unsigned>
100 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
102 bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
103 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
105 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
106 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
107 bool selectG_ICMP(MachineInstr &I) const;
108 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
109 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
110 SmallVectorImpl<GEPInfo> &AddrInfo) const;
111 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
113 void initM0(MachineInstr &I) const;
114 bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
115 bool selectG_STORE(MachineInstr &I) const;
116 bool selectG_SELECT(MachineInstr &I) const;
117 bool selectG_BRCOND(MachineInstr &I) const;
118 bool selectG_FRAME_INDEX(MachineInstr &I) const;
119 bool selectG_PTR_MASK(MachineInstr &I) const;
120 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
122 std::pair<Register, unsigned>
123 selectVOP3ModsImpl(Register Src) const;
125 InstructionSelector::ComplexRendererFns
126 selectVCSRC(MachineOperand &Root) const;
128 InstructionSelector::ComplexRendererFns
129 selectVSRC0(MachineOperand &Root) const;
131 InstructionSelector::ComplexRendererFns
132 selectVOP3Mods0(MachineOperand &Root) const;
133 InstructionSelector::ComplexRendererFns
134 selectVOP3OMods(MachineOperand &Root) const;
135 InstructionSelector::ComplexRendererFns
136 selectVOP3Mods(MachineOperand &Root) const;
137 InstructionSelector::ComplexRendererFns
138 selectVOP3Mods_nnan(MachineOperand &Root) const;
140 InstructionSelector::ComplexRendererFns
141 selectVOP3OpSelMods0(MachineOperand &Root) const;
142 InstructionSelector::ComplexRendererFns
143 selectVOP3OpSelMods(MachineOperand &Root) const;
145 InstructionSelector::ComplexRendererFns
146 selectSmrdImm(MachineOperand &Root) const;
147 InstructionSelector::ComplexRendererFns
148 selectSmrdImm32(MachineOperand &Root) const;
149 InstructionSelector::ComplexRendererFns
150 selectSmrdSgpr(MachineOperand &Root) const;
152 template <bool Signed>
153 InstructionSelector::ComplexRendererFns
154 selectFlatOffsetImpl(MachineOperand &Root) const;
155 InstructionSelector::ComplexRendererFns
156 selectFlatOffset(MachineOperand &Root) const;
158 InstructionSelector::ComplexRendererFns
159 selectFlatOffsetSigned(MachineOperand &Root) const;
161 InstructionSelector::ComplexRendererFns
162 selectMUBUFScratchOffen(MachineOperand &Root) const;
163 InstructionSelector::ComplexRendererFns
164 selectMUBUFScratchOffset(MachineOperand &Root) const;
166 bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
167 const MachineOperand &Base,
168 int64_t Offset, unsigned OffsetBits) const;
170 InstructionSelector::ComplexRendererFns
171 selectDS1Addr1Offset(MachineOperand &Root) const;
173 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
174 int OpIdx = -1) const;
176 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
179 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
182 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
185 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
188 bool isInlineImmediate16(int64_t Imm) const;
189 bool isInlineImmediate32(int64_t Imm) const;
190 bool isInlineImmediate64(int64_t Imm) const;
191 bool isInlineImmediate(const APFloat &Imm) const;
193 const SIInstrInfo &TII;
194 const SIRegisterInfo &TRI;
195 const AMDGPURegisterBankInfo &RBI;
196 const AMDGPUTargetMachine &TM;
197 const GCNSubtarget &STI;
198 bool EnableLateStructurizeCFG;
199 #define GET_GLOBALISEL_PREDICATES_DECL
200 #define AMDGPUSubtarget GCNSubtarget
201 #include "AMDGPUGenGlobalISel.inc"
202 #undef GET_GLOBALISEL_PREDICATES_DECL
203 #undef AMDGPUSubtarget
205 #define GET_GLOBALISEL_TEMPORARIES_DECL
206 #include "AMDGPUGenGlobalISel.inc"
207 #undef GET_GLOBALISEL_TEMPORARIES_DECL
210 } // End llvm namespace.