1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares the targeting of the Machinelegalizer class for
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "SIInstrInfo.h"
23 class GCNTargetMachine;
27 /// This class provides the information for the target register banks.
28 class AMDGPULegalizerInfo : public LegalizerInfo {
29 const GCNSubtarget &ST;
32 AMDGPULegalizerInfo(const GCNSubtarget &ST,
33 const GCNTargetMachine &TM);
35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
37 GISelChangeObserver &Observer) const override;
39 Register getSegmentAperture(unsigned AddrSpace,
40 MachineRegisterInfo &MRI,
41 MachineIRBuilder &B) const;
43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
44 MachineIRBuilder &B) const;
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
46 MachineIRBuilder &B) const;
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
48 MachineIRBuilder &B) const;
49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
50 MachineIRBuilder &B) const;
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
52 MachineIRBuilder &B, bool Signed) const;
53 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
54 MachineIRBuilder &B) const;
55 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
56 MachineIRBuilder &B) const;
57 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
58 MachineIRBuilder &B) const;
59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
60 MachineIRBuilder &B) const;
62 bool buildPCRelGlobalAddress(
63 Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
64 unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
66 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
67 MachineIRBuilder &B) const;
68 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
70 GISelChangeObserver &Observer) const;
72 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
73 MachineIRBuilder &B) const;
75 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
76 MachineIRBuilder &B) const;
78 Register getLiveInRegister(MachineRegisterInfo &MRI,
79 Register Reg, LLT Ty) const;
81 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
82 const ArgDescriptor *Arg) const;
83 bool legalizePreloadedArgIntrin(
84 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
85 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
87 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
88 MachineIRBuilder &B) const;
89 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
90 MachineIRBuilder &B) const;
91 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
92 MachineIRBuilder &B) const;
93 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
94 MachineIRBuilder &B) const;
95 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
96 MachineIRBuilder &B) const;
97 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
98 MachineIRBuilder &B) const;
100 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
101 MachineIRBuilder &B) const;
102 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
103 MachineIRBuilder &B, unsigned AddrSpace) const;
105 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
107 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
108 MachineIRBuilder &B, bool IsFormat) const;
109 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
110 MachineIRBuilder &B) const override;
113 } // End llvm namespace.