1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
21 #define GET_REGBANK_DECLARATIONS
22 #include "AMDGPUGenRegisterBank.inc"
23 #undef GET_REGBANK_DECLARATIONS
29 class MachineIRBuilder;
32 class TargetRegisterInfo;
34 /// This class provides the information for the target register banks.
35 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
39 #define GET_TARGET_REGBANK_CLASS
40 #include "AMDGPUGenRegisterBank.inc"
42 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
44 const GCNSubtarget &Subtarget;
45 const SIRegisterInfo *TRI;
46 const SIInstrInfo *TII;
48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
50 bool collectWaterfallOperands(
51 SmallSet<Register, 4> &SGPROperandRegs,
53 MachineRegisterInfo &MRI,
54 ArrayRef<unsigned> OpIndices) const;
56 bool executeInWaterfallLoop(
58 iterator_range<MachineBasicBlock::iterator> Range,
59 SmallSet<Register, 4> &SGPROperandRegs,
60 MachineRegisterInfo &MRI) const;
62 bool executeInWaterfallLoop(MachineIRBuilder &B,
64 MachineRegisterInfo &MRI,
65 ArrayRef<unsigned> OpIndices) const;
66 bool executeInWaterfallLoop(MachineInstr &MI,
67 MachineRegisterInfo &MRI,
68 ArrayRef<unsigned> OpIndices) const;
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
71 unsigned OpIdx) const;
72 bool applyMappingDynStackAlloc(MachineInstr &MI,
73 const OperandsMapper &OpdMapper,
74 MachineRegisterInfo &MRI) const;
75 bool applyMappingLoad(MachineInstr &MI,
76 const OperandsMapper &OpdMapper,
77 MachineRegisterInfo &MRI) const;
79 applyMappingImage(MachineInstr &MI,
80 const OperandsMapper &OpdMapper,
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
82 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const;
84 bool applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper,
87 void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
89 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
92 std::pair<Register, unsigned>
93 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
95 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
96 MachineInstr &MI) const;
98 /// See RegisterBankInfo::applyMapping.
99 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
101 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI,
104 const RegisterBankInfo::InstructionMapping &
105 getInstrMappingForLoad(const MachineInstr &MI) const;
107 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
108 const TargetRegisterInfo &TRI,
109 unsigned Default = AMDGPU::VGPRRegBankID) const;
111 // Return a value mapping for an operand that is required to be an SGPR.
112 const ValueMapping *getSGPROpMapping(Register Reg,
113 const MachineRegisterInfo &MRI,
114 const TargetRegisterInfo &TRI) const;
116 // Return a value mapping for an operand that is required to be a VGPR.
117 const ValueMapping *getVGPROpMapping(Register Reg,
118 const MachineRegisterInfo &MRI,
119 const TargetRegisterInfo &TRI) const;
121 // Return a value mapping for an operand that is required to be a AGPR.
122 const ValueMapping *getAGPROpMapping(Register Reg,
123 const MachineRegisterInfo &MRI,
124 const TargetRegisterInfo &TRI) const;
126 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
127 /// Regs. This appropriately sets the regbank of the new registers.
128 void split64BitValueForMapping(MachineIRBuilder &B,
129 SmallVector<Register, 2> &Regs,
133 template <unsigned NumOps>
134 struct OpRegBankEntry {
135 int8_t RegBanks[NumOps];
139 template <unsigned NumOps>
141 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
142 const std::array<unsigned, NumOps> RegSrcOpIdx,
143 ArrayRef<OpRegBankEntry<NumOps>> Table) const;
145 RegisterBankInfo::InstructionMappings
146 getInstrAlternativeMappingsIntrinsic(
147 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 RegisterBankInfo::InstructionMappings
150 getInstrAlternativeMappingsIntrinsicWSideEffects(
151 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
153 bool isSALUMapping(const MachineInstr &MI) const;
155 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
156 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
157 const InstructionMapping &getDefaultMappingAllVGPR(
158 const MachineInstr &MI) const;
160 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
161 const MachineInstr &MI,
165 AMDGPURegisterBankInfo(const GCNSubtarget &STI);
167 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
168 unsigned Size) const override;
170 unsigned getBreakDownCost(const ValueMapping &ValMapping,
171 const RegisterBank *CurBank = nullptr) const override;
173 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
177 getInstrAlternativeMappings(const MachineInstr &MI) const override;
179 const InstructionMapping &
180 getInstrMapping(const MachineInstr &MI) const override;
184 bool foldExtractEltToCmpSelect(MachineInstr &MI,
185 MachineRegisterInfo &MRI,
186 const OperandsMapper &OpdMapper) const;
187 bool foldInsertEltToCmpSelect(MachineInstr &MI,
188 MachineRegisterInfo &MRI,
189 const OperandsMapper &OpdMapper) const;
191 } // End llvm namespace.