contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

   1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  15
  16 #include "llvm/ADT/SmallSet.h"
  17 #include "llvm/CodeGen/MachineBasicBlock.h"
  18 #include "llvm/CodeGen/Register.h"
  19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  20
  21 #define GET_REGBANK_DECLARATIONS
  22 #include "AMDGPUGenRegisterBank.inc"
  23 #undef GET_REGBANK_DECLARATIONS
  24
  25 namespace llvm {
  26
  27 class LLT;
  28 class GCNSubtarget;
  29 class MachineIRBuilder;
  30 class SIInstrInfo;
  31 class SIRegisterInfo;
  32 class TargetRegisterInfo;
  33
  34 /// This class provides the information for the target register banks.
  35 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
  36
  37 protected:
  38
  39 #define GET_TARGET_REGBANK_CLASS
  40 #include "AMDGPUGenRegisterBank.inc"
  41 };
  42 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
  43   const GCNSubtarget &Subtarget;
  44   const SIRegisterInfo *TRI;
  45   const SIInstrInfo *TII;
  46
  47   bool collectWaterfallOperands(
  48     SmallSet<Register, 4> &SGPROperandRegs,
  49     MachineInstr &MI,
  50     MachineRegisterInfo &MRI,
  51     ArrayRef<unsigned> OpIndices) const;
  52
  53   bool executeInWaterfallLoop(
  54     MachineIRBuilder &B,
  55     iterator_range<MachineBasicBlock::iterator> Range,
  56     SmallSet<Register, 4> &SGPROperandRegs,
  57     MachineRegisterInfo &MRI) const;
  58
  59   bool executeInWaterfallLoop(MachineIRBuilder &B,
  60                               MachineInstr &MI,
  61                               MachineRegisterInfo &MRI,
  62                               ArrayRef<unsigned> OpIndices) const;
  63   bool executeInWaterfallLoop(MachineInstr &MI,
  64                               MachineRegisterInfo &MRI,
  65                               ArrayRef<unsigned> OpIndices) const;
  66
  67   void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
  68                                     unsigned OpIdx) const;
  69   bool applyMappingWideLoad(MachineInstr &MI,
  70                             const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
  71                             MachineRegisterInfo &MRI) const;
  72   bool
  73   applyMappingImage(MachineInstr &MI,
  74                     const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
  75                     MachineRegisterInfo &MRI, int RSrcIdx) const;
  76
  77   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
  78                           Register Reg) const;
  79
  80   std::pair<Register, unsigned>
  81   splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
  82
  83   MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
  84                                      MachineInstr &MI) const;
  85
  86   /// See RegisterBankInfo::applyMapping.
  87   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
  88
  89   const RegisterBankInfo::InstructionMapping &
  90   getInstrMappingForLoad(const MachineInstr &MI) const;
  91
  92   unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
  93                         const TargetRegisterInfo &TRI,
  94                         unsigned Default = AMDGPU::VGPRRegBankID) const;
  95
  96   // Return a value mapping for an operand that is required to be an SGPR.
  97   const ValueMapping *getSGPROpMapping(Register Reg,
  98                                        const MachineRegisterInfo &MRI,
  99                                        const TargetRegisterInfo &TRI) const;
 100
 101   // Return a value mapping for an operand that is required to be a VGPR.
 102   const ValueMapping *getVGPROpMapping(Register Reg,
 103                                        const MachineRegisterInfo &MRI,
 104                                        const TargetRegisterInfo &TRI) const;
 105
 106   /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
 107   /// Regs. This appropriately sets the regbank of the new registers.
 108   void split64BitValueForMapping(MachineIRBuilder &B,
 109                                  SmallVector<Register, 2> &Regs,
 110                                  LLT HalfTy,
 111                                  Register Reg) const;
 112
 113   template <unsigned NumOps>
 114   struct OpRegBankEntry {
 115     int8_t RegBanks[NumOps];
 116     int16_t Cost;
 117   };
 118
 119   template <unsigned NumOps>
 120   InstructionMappings
 121   addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
 122                       const std::array<unsigned, NumOps> RegSrcOpIdx,
 123                       ArrayRef<OpRegBankEntry<NumOps>> Table) const;
 124
 125   RegisterBankInfo::InstructionMappings
 126   getInstrAlternativeMappingsIntrinsic(
 127       const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
 128
 129   RegisterBankInfo::InstructionMappings
 130   getInstrAlternativeMappingsIntrinsicWSideEffects(
 131       const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
 132
 133   bool isSALUMapping(const MachineInstr &MI) const;
 134   const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
 135   const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
 136   const InstructionMapping &getDefaultMappingAllVGPR(
 137     const MachineInstr &MI) const;
 138
 139   const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
 140                                             const MachineInstr &MI,
 141                                             int RsrcIdx) const;
 142
 143 public:
 144   AMDGPURegisterBankInfo(const GCNSubtarget &STI);
 145
 146   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
 147                     unsigned Size) const override;
 148
 149   unsigned getBreakDownCost(const ValueMapping &ValMapping,
 150                             const RegisterBank *CurBank = nullptr) const override;
 151
 152   const RegisterBank &
 153   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 154
 155   InstructionMappings
 156   getInstrAlternativeMappings(const MachineInstr &MI) const override;
 157
 158   const InstructionMapping &
 159   getInstrMapping(const MachineInstr &MI) const override;
 160 };
 161 } // End llvm namespace.
 162 #endif