1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
21 #define GET_REGBANK_DECLARATIONS
22 #include "AMDGPUGenRegisterBank.inc"
23 #undef GET_REGBANK_DECLARATIONS
29 class MachineIRBuilder;
32 class TargetRegisterInfo;
34 /// This class provides the information for the target register banks.
35 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
39 #define GET_TARGET_REGBANK_CLASS
40 #include "AMDGPUGenRegisterBank.inc"
42 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
44 const GCNSubtarget &Subtarget;
45 const SIRegisterInfo *TRI;
46 const SIInstrInfo *TII;
48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
50 bool collectWaterfallOperands(
51 SmallSet<Register, 4> &SGPROperandRegs,
53 MachineRegisterInfo &MRI,
54 ArrayRef<unsigned> OpIndices) const;
56 bool executeInWaterfallLoop(
58 iterator_range<MachineBasicBlock::iterator> Range,
59 SmallSet<Register, 4> &SGPROperandRegs,
60 MachineRegisterInfo &MRI) const;
62 bool executeInWaterfallLoop(MachineIRBuilder &B,
64 MachineRegisterInfo &MRI,
65 ArrayRef<unsigned> OpIndices) const;
66 bool executeInWaterfallLoop(MachineInstr &MI,
67 MachineRegisterInfo &MRI,
68 ArrayRef<unsigned> OpIndices) const;
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
71 unsigned OpIdx) const;
72 bool applyMappingWideLoad(MachineInstr &MI,
73 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
74 MachineRegisterInfo &MRI) const;
76 applyMappingImage(MachineInstr &MI,
77 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
78 MachineRegisterInfo &MRI, int RSrcIdx) const;
80 void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
82 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
85 std::pair<Register, unsigned>
86 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
88 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
89 MachineInstr &MI) const;
91 /// See RegisterBankInfo::applyMapping.
92 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
94 const RegisterBankInfo::InstructionMapping &
95 getInstrMappingForLoad(const MachineInstr &MI) const;
97 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
98 const TargetRegisterInfo &TRI,
99 unsigned Default = AMDGPU::VGPRRegBankID) const;
101 // Return a value mapping for an operand that is required to be an SGPR.
102 const ValueMapping *getSGPROpMapping(Register Reg,
103 const MachineRegisterInfo &MRI,
104 const TargetRegisterInfo &TRI) const;
106 // Return a value mapping for an operand that is required to be a VGPR.
107 const ValueMapping *getVGPROpMapping(Register Reg,
108 const MachineRegisterInfo &MRI,
109 const TargetRegisterInfo &TRI) const;
111 // Return a value mapping for an operand that is required to be a AGPR.
112 const ValueMapping *getAGPROpMapping(Register Reg,
113 const MachineRegisterInfo &MRI,
114 const TargetRegisterInfo &TRI) const;
116 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
117 /// Regs. This appropriately sets the regbank of the new registers.
118 void split64BitValueForMapping(MachineIRBuilder &B,
119 SmallVector<Register, 2> &Regs,
123 template <unsigned NumOps>
124 struct OpRegBankEntry {
125 int8_t RegBanks[NumOps];
129 template <unsigned NumOps>
131 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
132 const std::array<unsigned, NumOps> RegSrcOpIdx,
133 ArrayRef<OpRegBankEntry<NumOps>> Table) const;
135 RegisterBankInfo::InstructionMappings
136 getInstrAlternativeMappingsIntrinsic(
137 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
139 RegisterBankInfo::InstructionMappings
140 getInstrAlternativeMappingsIntrinsicWSideEffects(
141 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
143 bool isSALUMapping(const MachineInstr &MI) const;
145 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
146 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
147 const InstructionMapping &getDefaultMappingAllVGPR(
148 const MachineInstr &MI) const;
150 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
151 const MachineInstr &MI,
155 AMDGPURegisterBankInfo(const GCNSubtarget &STI);
157 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
158 unsigned Size) const override;
160 unsigned getBreakDownCost(const ValueMapping &ValMapping,
161 const RegisterBank *CurBank = nullptr) const override;
163 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
167 getInstrAlternativeMappings(const MachineInstr &MI) const override;
169 const InstructionMapping &
170 getInstrMapping(const MachineInstr &MI) const override;
172 } // End llvm namespace.