1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information needed to emit code for R600 and SI GPUs.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
60 static cl::opt<bool> EnableR600StructurizeCFG(
61 "r600-ir-structurize",
62 cl::desc("Use StructurizeCFG IR pass"),
65 static cl::opt<bool> EnableSROA(
67 cl::desc("Run SROA after promote alloca pass"),
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73 cl::desc("Run early if-conversion"),
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78 cl::desc("Run pre-RA exec mask optimizations"),
81 static cl::opt<bool> EnableR600IfConvert(
83 cl::desc("Use if conversion pass"),
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89 "amdgpu-load-store-vectorizer",
90 cl::desc("Enable load store vectorizer"),
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96 "amdgpu-scalarize-global-loads",
97 cl::desc("Enable global load scalarization"),
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103 "amdgpu-internalize-symbols",
104 cl::desc("Enable elimination of non-kernel functions and unused globals"),
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110 "amdgpu-early-inline-all",
111 cl::desc("Inline all functions early"),
115 static cl::opt<bool> EnableSDWAPeephole(
116 "amdgpu-sdwa-peephole",
117 cl::desc("Enable SDWA peepholer"),
120 static cl::opt<bool> EnableDPPCombine(
121 "amdgpu-dpp-combine",
122 cl::desc("Enable DPP combiner"),
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127 cl::desc("Enable AMDGPU Alias Analysis"),
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132 "amdgpu-late-structurize",
133 cl::desc("Enable late CFG structurization"),
134 cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138 "amdgpu-function-calls",
139 cl::desc("Enable AMDGPU function call support"),
140 cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145 "amdgpu-fixed-function-abi",
146 cl::desc("Enable all implicit function arguments"),
147 cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153 "amdgpu-simplify-libcall",
154 cl::desc("Enable amdgpu library simplifications"),
158 static cl::opt<bool> EnableLowerKernelArguments(
159 "amdgpu-ir-lower-kernel-arguments",
160 cl::desc("Lower kernel argument loads in IR pass"),
164 static cl::opt<bool> EnableRegReassign(
165 "amdgpu-reassign-regs",
166 cl::desc("Enable register reassign optimizations on gfx10+"),
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172 "amdgpu-atomic-optimizations",
173 cl::desc("Enable atomic optimizations"),
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179 "amdgpu-mode-register",
180 cl::desc("Enable mode register pass"),
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
186 EnableDCEInRA("amdgpu-dce-in-ra",
187 cl::init(true), cl::Hidden,
188 cl::desc("Enable machine DCE inside regalloc"));
190 static cl::opt<bool> EnableScalarIRPasses(
191 "amdgpu-scalar-ir-passes",
192 cl::desc("Enable scalar IR passes"),
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197 "amdgpu-enable-structurizer-workarounds",
198 cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202 // Register the target
203 RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204 RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
206 PassRegistry *PR = PassRegistry::getPassRegistry();
207 initializeR600ClauseMergePassPass(*PR);
208 initializeR600ControlFlowFinalizerPass(*PR);
209 initializeR600PacketizerPass(*PR);
210 initializeR600ExpandSpecialInstrsPassPass(*PR);
211 initializeR600VectorRegMergerPass(*PR);
212 initializeGlobalISel(*PR);
213 initializeAMDGPUDAGToDAGISelPass(*PR);
214 initializeGCNDPPCombinePass(*PR);
215 initializeSILowerI1CopiesPass(*PR);
216 initializeSILowerSGPRSpillsPass(*PR);
217 initializeSIFixSGPRCopiesPass(*PR);
218 initializeSIFixVGPRCopiesPass(*PR);
219 initializeSIFixupVectorISelPass(*PR);
220 initializeSIFoldOperandsPass(*PR);
221 initializeSIPeepholeSDWAPass(*PR);
222 initializeSIShrinkInstructionsPass(*PR);
223 initializeSIOptimizeExecMaskingPreRAPass(*PR);
224 initializeSILoadStoreOptimizerPass(*PR);
225 initializeAMDGPUFixFunctionBitcastsPass(*PR);
226 initializeAMDGPUAlwaysInlinePass(*PR);
227 initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
228 initializeAMDGPUAnnotateUniformValuesPass(*PR);
229 initializeAMDGPUArgumentUsageInfoPass(*PR);
230 initializeAMDGPUAtomicOptimizerPass(*PR);
231 initializeAMDGPULowerKernelArgumentsPass(*PR);
232 initializeAMDGPULowerKernelAttributesPass(*PR);
233 initializeAMDGPULowerIntrinsicsPass(*PR);
234 initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
235 initializeAMDGPUPostLegalizerCombinerPass(*PR);
236 initializeAMDGPUPreLegalizerCombinerPass(*PR);
237 initializeAMDGPUPromoteAllocaPass(*PR);
238 initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239 initializeAMDGPUCodeGenPreparePass(*PR);
240 initializeAMDGPUPropagateAttributesEarlyPass(*PR);
241 initializeAMDGPUPropagateAttributesLatePass(*PR);
242 initializeAMDGPURewriteOutArgumentsPass(*PR);
243 initializeAMDGPUUnifyMetadataPass(*PR);
244 initializeSIAnnotateControlFlowPass(*PR);
245 initializeSIInsertHardClausesPass(*PR);
246 initializeSIInsertWaitcntsPass(*PR);
247 initializeSIModeRegisterPass(*PR);
248 initializeSIWholeQuadModePass(*PR);
249 initializeSILowerControlFlowPass(*PR);
250 initializeSIRemoveShortExecBranchesPass(*PR);
251 initializeSIPreEmitPeepholePass(*PR);
252 initializeSIInsertSkipsPass(*PR);
253 initializeSIMemoryLegalizerPass(*PR);
254 initializeSIOptimizeExecMaskingPass(*PR);
255 initializeSIPreAllocateWWMRegsPass(*PR);
256 initializeSIFormMemoryClausesPass(*PR);
257 initializeSIPostRABundlerPass(*PR);
258 initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
259 initializeAMDGPUAAWrapperPassPass(*PR);
260 initializeAMDGPUExternalAAWrapperPass(*PR);
261 initializeAMDGPUUseNativeCallsPass(*PR);
262 initializeAMDGPUSimplifyLibCallsPass(*PR);
263 initializeAMDGPUInlinerPass(*PR);
264 initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265 initializeGCNRegBankReassignPass(*PR);
266 initializeGCNNSAReassignPass(*PR);
267 initializeSIAddIMGInitPass(*PR);
270 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
271 return std::make_unique<AMDGPUTargetObjectFile>();
274 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
275 return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
278 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
279 return new SIScheduleDAGMI(C);
282 static ScheduleDAGInstrs *
283 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
284 ScheduleDAGMILive *DAG =
285 new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
286 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
288 DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
289 DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
293 static ScheduleDAGInstrs *
294 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
295 auto DAG = new GCNIterativeScheduler(C,
296 GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
297 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
298 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
302 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
303 return new GCNIterativeScheduler(C,
304 GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
307 static ScheduleDAGInstrs *
308 createIterativeILPMachineScheduler(MachineSchedContext *C) {
309 auto DAG = new GCNIterativeScheduler(C,
310 GCNIterativeScheduler::SCHEDULE_ILP);
311 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
312 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
313 DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
317 static MachineSchedRegistry
318 R600SchedRegistry("r600", "Run R600's custom scheduler",
319 createR600MachineScheduler);
321 static MachineSchedRegistry
322 SISchedRegistry("si", "Run SI's custom scheduler",
323 createSIMachineScheduler);
325 static MachineSchedRegistry
326 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
327 "Run GCN scheduler to maximize occupancy",
328 createGCNMaxOccupancyMachineScheduler);
330 static MachineSchedRegistry
331 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
332 "Run GCN scheduler to maximize occupancy (experimental)",
333 createIterativeGCNMaxOccupancyMachineScheduler);
335 static MachineSchedRegistry
336 GCNMinRegSchedRegistry("gcn-minreg",
337 "Run GCN iterative scheduler for minimal register usage (experimental)",
338 createMinRegScheduler);
340 static MachineSchedRegistry
341 GCNILPSchedRegistry("gcn-ilp",
342 "Run GCN iterative scheduler for ILP scheduling (experimental)",
343 createIterativeILPMachineScheduler);
345 static StringRef computeDataLayout(const Triple &TT) {
346 if (TT.getArch() == Triple::r600) {
348 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
349 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
352 // 32-bit private, local, and region pointers. 64-bit global, constant and
353 // flat, non-integral buffer fat pointers.
354 return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
355 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
356 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
361 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
365 // Need to default to a target with flat support for HSA.
366 if (TT.getArch() == Triple::amdgcn)
367 return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
372 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
373 // The AMDGPU toolchain only supports generating shared objects, so we
374 // must always use PIC.
378 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
379 StringRef CPU, StringRef FS,
380 TargetOptions Options,
381 Optional<Reloc::Model> RM,
382 Optional<CodeModel::Model> CM,
383 CodeGenOpt::Level OptLevel)
384 : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
385 FS, Options, getEffectiveRelocModel(RM),
386 getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
387 TLOF(createTLOF(getTargetTriple())) {
389 if (TT.getArch() == Triple::amdgcn) {
390 if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
391 MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
392 else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
393 MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
397 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
398 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
399 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
401 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
403 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
404 Attribute GPUAttr = F.getFnAttribute("target-cpu");
405 return GPUAttr.hasAttribute(Attribute::None) ?
406 getTargetCPU() : GPUAttr.getValueAsString();
409 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
410 Attribute FSAttr = F.getFnAttribute("target-features");
412 return FSAttr.hasAttribute(Attribute::None) ?
413 getTargetFeatureString() :
414 FSAttr.getValueAsString();
417 /// Predicate for Internalize pass.
418 static bool mustPreserveGV(const GlobalValue &GV) {
419 if (const Function *F = dyn_cast<Function>(&GV))
420 return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
422 return !GV.use_empty();
425 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
426 Builder.DivergentTarget = true;
428 bool EnableOpt = getOptLevel() > CodeGenOpt::None;
429 bool Internalize = InternalizeSymbols;
430 bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
431 bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
432 bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
434 if (EnableFunctionCalls) {
435 delete Builder.Inliner;
436 Builder.Inliner = createAMDGPUFunctionInliningPass();
439 Builder.addExtension(
440 PassManagerBuilder::EP_ModuleOptimizerEarly,
441 [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
442 legacy::PassManagerBase &PM) {
444 PM.add(createAMDGPUAAWrapperPass());
445 PM.add(createAMDGPUExternalAAWrapperPass());
447 PM.add(createAMDGPUUnifyMetadataPass());
448 PM.add(createAMDGPUPrintfRuntimeBinding());
450 PM.add(createInternalizePass(mustPreserveGV));
451 PM.add(createAMDGPUPropagateAttributesLatePass(this));
453 PM.add(createGlobalDCEPass());
455 PM.add(createAMDGPUAlwaysInlinePass(false));
458 Builder.addExtension(
459 PassManagerBuilder::EP_EarlyAsPossible,
460 [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
461 legacy::PassManagerBase &PM) {
463 PM.add(createAMDGPUAAWrapperPass());
464 PM.add(createAMDGPUExternalAAWrapperPass());
466 PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
467 PM.add(llvm::createAMDGPUUseNativeCallsPass());
469 PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
472 Builder.addExtension(
473 PassManagerBuilder::EP_CGSCCOptimizerLate,
474 [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
475 // Add infer address spaces pass to the opt pipeline after inlining
476 // but before SROA to increase SROA opportunities.
477 PM.add(createInferAddressSpacesPass());
479 // This should run after inlining to have any chance of doing anything,
480 // and before other cleanup optimizations.
481 PM.add(createAMDGPULowerKernelAttributesPass());
483 // Promote alloca to vector before SROA and loop unroll. If we manage
484 // to eliminate allocas before unroll we may choose to unroll less.
486 PM.add(createAMDGPUPromoteAllocaToVector());
490 //===----------------------------------------------------------------------===//
491 // R600 Target Machine (R600 -> Cayman)
492 //===----------------------------------------------------------------------===//
494 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
495 StringRef CPU, StringRef FS,
496 TargetOptions Options,
497 Optional<Reloc::Model> RM,
498 Optional<CodeModel::Model> CM,
499 CodeGenOpt::Level OL, bool JIT)
500 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
501 setRequiresStructuredCFG(true);
503 // Override the default since calls aren't supported for r600.
504 if (EnableFunctionCalls &&
505 EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
506 EnableFunctionCalls = false;
509 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
510 const Function &F) const {
511 StringRef GPU = getGPUName(F);
512 StringRef FS = getFeatureString(F);
514 SmallString<128> SubtargetKey(GPU);
515 SubtargetKey.append(FS);
517 auto &I = SubtargetMap[SubtargetKey];
519 // This needs to be done before we create a new subtarget since any
520 // creation will depend on the TM and the code generation flags on the
521 // function that reside in TargetOptions.
522 resetTargetOptions(F);
523 I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
530 R600TargetMachine::getTargetTransformInfo(const Function &F) {
531 return TargetTransformInfo(R600TTIImpl(this, F));
534 //===----------------------------------------------------------------------===//
535 // GCN Target Machine (SI+)
536 //===----------------------------------------------------------------------===//
538 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
539 StringRef CPU, StringRef FS,
540 TargetOptions Options,
541 Optional<Reloc::Model> RM,
542 Optional<CodeModel::Model> CM,
543 CodeGenOpt::Level OL, bool JIT)
544 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
546 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
547 StringRef GPU = getGPUName(F);
548 StringRef FS = getFeatureString(F);
550 SmallString<128> SubtargetKey(GPU);
551 SubtargetKey.append(FS);
553 auto &I = SubtargetMap[SubtargetKey];
555 // This needs to be done before we create a new subtarget since any
556 // creation will depend on the TM and the code generation flags on the
557 // function that reside in TargetOptions.
558 resetTargetOptions(F);
559 I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
562 I->setScalarizeGlobalBehavior(ScalarizeGlobal);
568 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
569 return TargetTransformInfo(GCNTTIImpl(this, F));
572 //===----------------------------------------------------------------------===//
574 //===----------------------------------------------------------------------===//
578 class AMDGPUPassConfig : public TargetPassConfig {
580 AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
581 : TargetPassConfig(TM, PM) {
582 // Exceptions and StackMaps are not supported, so these passes will never do
584 disablePass(&StackMapLivenessID);
585 disablePass(&FuncletLayoutID);
588 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
589 return getTM<AMDGPUTargetMachine>();
593 createMachineScheduler(MachineSchedContext *C) const override {
594 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
595 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
596 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
600 void addEarlyCSEOrGVNPass();
601 void addStraightLineScalarOptimizationPasses();
602 void addIRPasses() override;
603 void addCodeGenPrepare() override;
604 bool addPreISel() override;
605 bool addInstSelector() override;
606 bool addGCPasses() override;
608 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
611 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
612 return getStandardCSEConfigForOpt(TM->getOptLevel());
615 class R600PassConfig final : public AMDGPUPassConfig {
617 R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
618 : AMDGPUPassConfig(TM, PM) {}
620 ScheduleDAGInstrs *createMachineScheduler(
621 MachineSchedContext *C) const override {
622 return createR600MachineScheduler(C);
625 bool addPreISel() override;
626 bool addInstSelector() override;
627 void addPreRegAlloc() override;
628 void addPreSched2() override;
629 void addPreEmitPass() override;
632 class GCNPassConfig final : public AMDGPUPassConfig {
634 GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
635 : AMDGPUPassConfig(TM, PM) {
636 // It is necessary to know the register usage of the entire call graph. We
637 // allow calls without EnableAMDGPUFunctionCalls if they are marked
638 // noinline, so this is always required.
639 setRequiresCodeGenSCCOrder(true);
642 GCNTargetMachine &getGCNTargetMachine() const {
643 return getTM<GCNTargetMachine>();
647 createMachineScheduler(MachineSchedContext *C) const override;
649 bool addPreISel() override;
650 void addMachineSSAOptimization() override;
651 bool addILPOpts() override;
652 bool addInstSelector() override;
653 bool addIRTranslator() override;
654 void addPreLegalizeMachineIR() override;
655 bool addLegalizeMachineIR() override;
656 void addPreRegBankSelect() override;
657 bool addRegBankSelect() override;
658 bool addGlobalInstructionSelect() override;
659 void addFastRegAlloc() override;
660 void addOptimizedRegAlloc() override;
661 void addPreRegAlloc() override;
662 bool addPreRewrite() override;
663 void addPostRegAlloc() override;
664 void addPreSched2() override;
665 void addPreEmitPass() override;
668 } // end anonymous namespace
670 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
671 if (getOptLevel() == CodeGenOpt::Aggressive)
672 addPass(createGVNPass());
674 addPass(createEarlyCSEPass());
677 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
678 addPass(createLICMPass());
679 addPass(createSeparateConstOffsetFromGEPPass());
680 addPass(createSpeculativeExecutionPass());
681 // ReassociateGEPs exposes more opportunites for SLSR. See
682 // the example in reassociate-geps-and-slsr.ll.
683 addPass(createStraightLineStrengthReducePass());
684 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
685 // EarlyCSE can reuse.
686 addEarlyCSEOrGVNPass();
687 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
688 addPass(createNaryReassociatePass());
689 // NaryReassociate on GEPs creates redundant common expressions, so run
690 // EarlyCSE after it.
691 addPass(createEarlyCSEPass());
694 void AMDGPUPassConfig::addIRPasses() {
695 const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
697 // There is no reason to run these.
698 disablePass(&StackMapLivenessID);
699 disablePass(&FuncletLayoutID);
700 disablePass(&PatchableFunctionID);
702 addPass(createAMDGPUPrintfRuntimeBinding());
704 // This must occur before inlining, as the inliner will not look through
706 addPass(createAMDGPUFixFunctionBitcastsPass());
708 // A call to propagate attributes pass in the backend in case opt was not run.
709 addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
711 addPass(createAtomicExpandPass());
714 addPass(createAMDGPULowerIntrinsicsPass());
716 // Function calls are not supported, so make sure we inline everything.
717 addPass(createAMDGPUAlwaysInlinePass());
718 addPass(createAlwaysInlinerLegacyPass());
719 // We need to add the barrier noop pass, otherwise adding the function
720 // inlining pass will cause all of the PassConfigs passes to be run
721 // one function at a time, which means if we have a nodule with two
722 // functions, then we will generate code for the first function
723 // without ever running any passes on the second.
724 addPass(createBarrierNoopPass());
726 // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
727 if (TM.getTargetTriple().getArch() == Triple::r600)
728 addPass(createR600OpenCLImageTypeLoweringPass());
730 // Replace OpenCL enqueued block function pointers with global variables.
731 addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
733 if (TM.getOptLevel() > CodeGenOpt::None) {
734 addPass(createInferAddressSpacesPass());
735 addPass(createAMDGPUPromoteAlloca());
738 addPass(createSROAPass());
740 if (EnableScalarIRPasses)
741 addStraightLineScalarOptimizationPasses();
743 if (EnableAMDGPUAliasAnalysis) {
744 addPass(createAMDGPUAAWrapperPass());
745 addPass(createExternalAAWrapperPass([](Pass &P, Function &,
747 if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
748 AAR.addAAResult(WrapperPass->getResult());
753 if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
754 // TODO: May want to move later or split into an early and late one.
755 addPass(createAMDGPUCodeGenPreparePass());
758 TargetPassConfig::addIRPasses();
760 // EarlyCSE is not always strong enough to clean up what LSR produces. For
761 // example, GVN can combine
768 // %0 = shl nsw %a, 2
771 // but EarlyCSE can do neither of them.
772 if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
773 addEarlyCSEOrGVNPass();
776 void AMDGPUPassConfig::addCodeGenPrepare() {
777 if (TM->getTargetTriple().getArch() == Triple::amdgcn)
778 addPass(createAMDGPUAnnotateKernelFeaturesPass());
780 if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
781 EnableLowerKernelArguments)
782 addPass(createAMDGPULowerKernelArgumentsPass());
784 addPass(&AMDGPUPerfHintAnalysisID);
786 TargetPassConfig::addCodeGenPrepare();
788 if (EnableLoadStoreVectorizer)
789 addPass(createLoadStoreVectorizerPass());
791 // LowerSwitch pass may introduce unreachable blocks that can
792 // cause unexpected behavior for subsequent passes. Placing it
793 // here seems better that these blocks would get cleaned up by
794 // UnreachableBlockElim inserted next in the pass flow.
795 addPass(createLowerSwitchPass());
798 bool AMDGPUPassConfig::addPreISel() {
799 addPass(createFlattenCFGPass());
803 bool AMDGPUPassConfig::addInstSelector() {
804 // Defer the verifier until FinalizeISel.
805 addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
809 bool AMDGPUPassConfig::addGCPasses() {
810 // Do nothing. GC is not supported.
814 //===----------------------------------------------------------------------===//
816 //===----------------------------------------------------------------------===//
818 bool R600PassConfig::addPreISel() {
819 AMDGPUPassConfig::addPreISel();
821 if (EnableR600StructurizeCFG)
822 addPass(createStructurizeCFGPass());
826 bool R600PassConfig::addInstSelector() {
827 addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
831 void R600PassConfig::addPreRegAlloc() {
832 addPass(createR600VectorRegMerger());
835 void R600PassConfig::addPreSched2() {
836 addPass(createR600EmitClauseMarkers(), false);
837 if (EnableR600IfConvert)
838 addPass(&IfConverterID, false);
839 addPass(createR600ClauseMergePass(), false);
842 void R600PassConfig::addPreEmitPass() {
843 addPass(createAMDGPUCFGStructurizerPass(), false);
844 addPass(createR600ExpandSpecialInstrsPass(), false);
845 addPass(&FinalizeMachineBundlesID, false);
846 addPass(createR600Packetizer(), false);
847 addPass(createR600ControlFlowFinalizer(), false);
850 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
851 return new R600PassConfig(*this, PM);
854 //===----------------------------------------------------------------------===//
856 //===----------------------------------------------------------------------===//
858 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
859 MachineSchedContext *C) const {
860 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
861 if (ST.enableSIScheduler())
862 return createSIMachineScheduler(C);
863 return createGCNMaxOccupancyMachineScheduler(C);
866 bool GCNPassConfig::addPreISel() {
867 AMDGPUPassConfig::addPreISel();
869 if (EnableAtomicOptimizations) {
870 addPass(createAMDGPUAtomicOptimizerPass());
873 // FIXME: We need to run a pass to propagate the attributes when calls are
876 // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
877 // regions formed by them.
878 addPass(&AMDGPUUnifyDivergentExitNodesID);
879 if (!LateCFGStructurize) {
880 if (EnableStructurizerWorkarounds) {
881 addPass(createFixIrreduciblePass());
882 addPass(createUnifyLoopExitsPass());
884 addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
886 addPass(createSinkingPass());
887 addPass(createAMDGPUAnnotateUniformValues());
888 if (!LateCFGStructurize) {
889 addPass(createSIAnnotateControlFlowPass());
891 addPass(createLCSSAPass());
896 void GCNPassConfig::addMachineSSAOptimization() {
897 TargetPassConfig::addMachineSSAOptimization();
899 // We want to fold operands after PeepholeOptimizer has run (or as part of
900 // it), because it will eliminate extra copies making it easier to fold the
901 // real source operand. We want to eliminate dead instructions after, so that
902 // we see fewer uses of the copies. We then need to clean up the dead
903 // instructions leftover after the operands are folded as well.
905 // XXX - Can we get away without running DeadMachineInstructionElim again?
906 addPass(&SIFoldOperandsID);
907 if (EnableDPPCombine)
908 addPass(&GCNDPPCombineID);
909 addPass(&DeadMachineInstructionElimID);
910 addPass(&SILoadStoreOptimizerID);
911 if (EnableSDWAPeephole) {
912 addPass(&SIPeepholeSDWAID);
913 addPass(&EarlyMachineLICMID);
914 addPass(&MachineCSEID);
915 addPass(&SIFoldOperandsID);
916 addPass(&DeadMachineInstructionElimID);
918 addPass(createSIShrinkInstructionsPass());
921 bool GCNPassConfig::addILPOpts() {
922 if (EnableEarlyIfConversion)
923 addPass(&EarlyIfConverterID);
925 TargetPassConfig::addILPOpts();
929 bool GCNPassConfig::addInstSelector() {
930 AMDGPUPassConfig::addInstSelector();
931 addPass(&SIFixSGPRCopiesID);
932 addPass(createSILowerI1CopiesPass());
933 // TODO: We have to add FinalizeISel
934 // to expand V_ADD/SUB_U64_PSEUDO before SIFixupVectorISel
935 // that expects V_ADD/SUB -> A_ADDC/SUBB pairs expanded.
936 // Will be removed as soon as SIFixupVectorISel is changed
937 // to work with V_ADD/SUB_U64_PSEUDO instead.
938 addPass(&FinalizeISelID);
939 addPass(createSIFixupVectorISelPass());
940 addPass(createSIAddIMGInitPass());
944 bool GCNPassConfig::addIRTranslator() {
945 addPass(new IRTranslator());
949 void GCNPassConfig::addPreLegalizeMachineIR() {
950 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
951 addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
952 addPass(new Localizer());
955 bool GCNPassConfig::addLegalizeMachineIR() {
956 addPass(new Legalizer());
960 void GCNPassConfig::addPreRegBankSelect() {
961 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
962 addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
965 bool GCNPassConfig::addRegBankSelect() {
966 addPass(new RegBankSelect());
970 bool GCNPassConfig::addGlobalInstructionSelect() {
971 addPass(new InstructionSelect());
975 void GCNPassConfig::addPreRegAlloc() {
976 if (LateCFGStructurize) {
977 addPass(createAMDGPUMachineCFGStructurizerPass());
979 addPass(createSIWholeQuadModePass());
982 void GCNPassConfig::addFastRegAlloc() {
983 // FIXME: We have to disable the verifier here because of PHIElimination +
984 // TwoAddressInstructions disabling it.
986 // This must be run immediately after phi elimination and before
987 // TwoAddressInstructions, otherwise the processing of the tied operand of
988 // SI_ELSE will introduce a copy of the tied operand source after the else.
989 insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
991 // This must be run just after RegisterCoalescing.
992 insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
994 TargetPassConfig::addFastRegAlloc();
997 void GCNPassConfig::addOptimizedRegAlloc() {
998 if (OptExecMaskPreRA)
999 insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1000 insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1002 // This must be run immediately after phi elimination and before
1003 // TwoAddressInstructions, otherwise the processing of the tied operand of
1004 // SI_ELSE will introduce a copy of the tied operand source after the else.
1005 insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1007 // This must be run just after RegisterCoalescing.
1008 insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1011 insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1013 TargetPassConfig::addOptimizedRegAlloc();
1016 bool GCNPassConfig::addPreRewrite() {
1017 if (EnableRegReassign) {
1018 addPass(&GCNNSAReassignID);
1019 addPass(&GCNRegBankReassignID);
1024 void GCNPassConfig::addPostRegAlloc() {
1025 addPass(&SIFixVGPRCopiesID);
1026 if (getOptLevel() > CodeGenOpt::None)
1027 addPass(&SIOptimizeExecMaskingID);
1028 TargetPassConfig::addPostRegAlloc();
1030 // Equivalent of PEI for SGPRs.
1031 addPass(&SILowerSGPRSpillsID);
1034 void GCNPassConfig::addPreSched2() {
1035 addPass(&SIPostRABundlerID);
1038 void GCNPassConfig::addPreEmitPass() {
1039 addPass(createSIMemoryLegalizerPass());
1040 addPass(createSIInsertWaitcntsPass());
1041 addPass(createSIShrinkInstructionsPass());
1042 addPass(createSIModeRegisterPass());
1044 // The hazard recognizer that runs as part of the post-ra scheduler does not
1045 // guarantee to be able handle all hazards correctly. This is because if there
1046 // are multiple scheduling regions in a basic block, the regions are scheduled
1047 // bottom up, so when we begin to schedule a region we don't know what
1048 // instructions were emitted directly before it.
1050 // Here we add a stand-alone hazard recognizer pass which can handle all
1053 // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1054 // be better for it to emit S_NOP <N> when possible.
1055 addPass(&PostRAHazardRecognizerID);
1056 if (getOptLevel() > CodeGenOpt::None)
1057 addPass(&SIInsertHardClausesID);
1059 addPass(&SIRemoveShortExecBranchesID);
1060 addPass(&SIInsertSkipsPassID);
1061 addPass(&SIPreEmitPeepholeID);
1062 addPass(&BranchRelaxationPassID);
1065 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1066 return new GCNPassConfig(*this, PM);
1069 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1070 return new yaml::SIMachineFunctionInfo();
1073 yaml::MachineFunctionInfo *
1074 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1075 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1076 return new yaml::SIMachineFunctionInfo(*MFI,
1077 *MF.getSubtarget().getRegisterInfo());
1080 bool GCNTargetMachine::parseMachineFunctionInfo(
1081 const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1082 SMDiagnostic &Error, SMRange &SourceRange) const {
1083 const yaml::SIMachineFunctionInfo &YamlMFI =
1084 reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1085 MachineFunction &MF = PFS.MF;
1086 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1088 MFI->initializeBaseYamlFields(YamlMFI);
1090 auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1092 if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1093 SourceRange = RegName.SourceRange;
1101 auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1102 // Create a diagnostic for a the register string literal.
1103 const MemoryBuffer &Buffer =
1104 *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1105 Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1106 RegName.Value.size(), SourceMgr::DK_Error,
1107 "incorrect register class for field", RegName.Value,
1109 SourceRange = RegName.SourceRange;
1113 if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1114 parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1115 parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1118 if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1119 !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1120 return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1123 if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1124 !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1125 return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1128 if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1129 !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1130 return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1133 auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1134 const TargetRegisterClass &RC,
1135 ArgDescriptor &Arg, unsigned UserSGPRs,
1136 unsigned SystemSGPRs) {
1137 // Skip parsing if it's not present.
1141 if (A->IsRegister) {
1143 if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1144 SourceRange = A->RegisterName.SourceRange;
1147 if (!RC.contains(Reg))
1148 return diagnoseRegisterClass(A->RegisterName);
1149 Arg = ArgDescriptor::createRegister(Reg);
1151 Arg = ArgDescriptor::createStack(A->StackOffset);
1152 // Check and apply the optional mask.
1154 Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1156 MFI->NumUserSGPRs += UserSGPRs;
1157 MFI->NumSystemSGPRs += SystemSGPRs;
1161 if (YamlMFI.ArgInfo &&
1162 (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1163 AMDGPU::SGPR_128RegClass,
1164 MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1165 parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1166 AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1168 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1169 MFI->ArgInfo.QueuePtr, 2, 0) ||
1170 parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1171 AMDGPU::SReg_64RegClass,
1172 MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1173 parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1174 AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1176 parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1177 AMDGPU::SReg_64RegClass,
1178 MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1179 parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1180 AMDGPU::SGPR_32RegClass,
1181 MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1182 parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1183 AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1185 parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1186 AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1188 parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1189 AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1191 parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1192 AMDGPU::SGPR_32RegClass,
1193 MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1194 parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1195 AMDGPU::SGPR_32RegClass,
1196 MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1197 parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1198 AMDGPU::SReg_64RegClass,
1199 MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1200 parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1201 AMDGPU::SReg_64RegClass,
1202 MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1203 parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1204 AMDGPU::VGPR_32RegClass,
1205 MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1206 parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1207 AMDGPU::VGPR_32RegClass,
1208 MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1209 parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1210 AMDGPU::VGPR_32RegClass,
1211 MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1214 MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1215 MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1216 MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1217 MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1218 MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1219 MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;