1 //===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // MIMG-specific encoding families to distinguish between semantically
10 // equivalent machine instructions with different encoding.
12 // - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8)
13 // - MIMGEncGfx8: encoding introduced with gfx8 for atomics
14 // - MIMGEncGfx10Default: gfx default (non-NSA) encoding
15 // - MIMGEncGfx10NSA: gfx10 NSA encoding
18 def MIMGEncGfx6 : MIMGEncoding;
19 def MIMGEncGfx8 : MIMGEncoding;
20 def MIMGEncGfx10Default : MIMGEncoding;
21 def MIMGEncGfx10NSA : MIMGEncoding;
23 def MIMGEncoding : GenericEnum {
24 let FilterClass = "MIMGEncoding";
27 // Represent an ISA-level opcode, independent of the encoding and the
29 class MIMGBaseOpcode : PredicateControl {
30 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
33 bit AtomicX2 = 0; // (f)cmpswap
36 bits<8> NumExtraArgs = 0;
40 bit LodOrClampOrMip = 0;
44 def MIMGBaseOpcode : GenericEnum {
45 let FilterClass = "MIMGBaseOpcode";
48 def MIMGBaseOpcodesTable : GenericTable {
49 let FilterClass = "MIMGBaseOpcode";
50 let CppTypeName = "MIMGBaseOpcodeInfo";
51 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
52 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates",
53 "LodOrClampOrMip", "HasD16"];
54 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode;
56 let PrimaryKey = ["BaseOpcode"];
57 let PrimaryKeyName = "getMIMGBaseOpcodeInfo";
60 def MIMGDim : GenericEnum {
61 let FilterClass = "AMDGPUDimProps";
64 def MIMGDimInfoTable : GenericTable {
65 let FilterClass = "AMDGPUDimProps";
66 let CppTypeName = "MIMGDimInfo";
67 let Fields = ["Dim", "NumCoords", "NumGradients", "DA", "Encoding", "AsmSuffix"];
68 GenericEnum TypeOf_Dim = MIMGDim;
70 let PrimaryKey = ["Dim"];
71 let PrimaryKeyName = "getMIMGDimInfo";
74 def getMIMGDimInfoByEncoding : SearchIndex {
75 let Table = MIMGDimInfoTable;
76 let Key = ["Encoding"];
79 def getMIMGDimInfoByAsmSuffix : SearchIndex {
80 let Table = MIMGDimInfoTable;
81 let Key = ["AsmSuffix"];
84 class mimg <bits<8> si_gfx10, bits<8> vi = si_gfx10> {
85 field bits<8> SI_GFX10 = si_gfx10;
86 field bits<8> VI = vi;
89 class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> {
91 MIMGBaseOpcode LZ = lz;
94 def MIMGLZMappingTable : GenericTable {
95 let FilterClass = "MIMGLZMapping";
96 let CppTypeName = "MIMGLZMappingInfo";
97 let Fields = ["L", "LZ"];
98 GenericEnum TypeOf_L = MIMGBaseOpcode;
99 GenericEnum TypeOf_LZ = MIMGBaseOpcode;
101 let PrimaryKey = ["L"];
102 let PrimaryKeyName = "getMIMGLZMappingInfo";
105 class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> {
106 MIMGBaseOpcode MIP = mip;
107 MIMGBaseOpcode NONMIP = nonmip;
110 def MIMGMIPMappingTable : GenericTable {
111 let FilterClass = "MIMGMIPMapping";
112 let CppTypeName = "MIMGMIPMappingInfo";
113 let Fields = ["MIP", "NONMIP"];
114 GenericEnum TypeOf_MIP = MIMGBaseOpcode;
115 GenericEnum TypeOf_NONMIP = MIMGBaseOpcode;
117 let PrimaryKey = ["MIP"];
118 let PrimaryKeyName = "getMIMGMIPMappingInfo";
121 class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> {
122 MIMGBaseOpcode G = g;
123 MIMGBaseOpcode G16 = g16;
126 def MIMGG16MappingTable : GenericTable {
127 let FilterClass = "MIMGG16Mapping";
128 let CppTypeName = "MIMGG16MappingInfo";
129 let Fields = ["G", "G16"];
130 GenericEnum TypeOf_G = MIMGBaseOpcode;
131 GenericEnum TypeOf_G16 = MIMGBaseOpcode;
133 let PrimaryKey = ["G"];
134 let PrimaryKeyName = "getMIMGG16MappingInfo";
137 class MIMG_Base <dag outs, string dns = "">
138 : InstSI <outs, (ins), "", []> {
146 let SchedRW = [WriteVMEM];
147 let UseNamedOperandTable = 1;
148 let hasSideEffects = 0; // XXX ????
150 let DecoderNamespace = dns;
151 let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
154 class MIMG <dag outs, string dns = "">
155 : MIMG_Base <outs, dns> {
157 let hasPostISelHook = 1;
158 let AsmMatchConverter = "cvtMIMG";
160 Instruction Opcode = !cast<Instruction>(NAME);
161 MIMGBaseOpcode BaseOpcode;
162 MIMGEncoding MIMGEncoding;
167 def MIMGInfoTable : GenericTable {
168 let FilterClass = "MIMG";
169 let CppTypeName = "MIMGInfo";
170 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
171 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode;
172 GenericEnum TypeOf_MIMGEncoding = MIMGEncoding;
174 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
175 let PrimaryKeyName = "getMIMGOpcodeHelper";
178 def getMIMGInfo : SearchIndex {
179 let Table = MIMGInfoTable;
180 let Key = ["Opcode"];
183 // This is a separate class so that TableGen memoizes the computations.
184 class MIMGNSAHelper<int num_addrs> {
185 list<string> AddrAsmNames =
186 !foldl([]<string>, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], lhs, i,
187 !if(!lt(i, num_addrs), !listconcat(lhs, ["vaddr"#!size(lhs)]), lhs));
188 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames);
189 string AddrAsm = "[" # !foldl("$" # !head(AddrAsmNames), !tail(AddrAsmNames), lhs, rhs,
190 lhs # ", $" # rhs) # "]";
192 int NSA = !if(!le(num_addrs, 1), ?,
193 !if(!le(num_addrs, 5), 1,
194 !if(!le(num_addrs, 9), 2,
195 !if(!le(num_addrs, 13), 3, ?))));
198 // Base class of all pre-gfx10 MIMG instructions.
199 class MIMG_gfx6789<bits<8> op, dag outs, string dns = "">
200 : MIMG<outs, dns>, MIMGe_gfx6789<op> {
201 let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
202 let AssemblerPredicate = isGFX6GFX7GFX8GFX9;
204 let MIMGEncoding = MIMGEncGfx6;
206 let d16 = !if(BaseOpcode.HasD16, ?, 0);
209 // Base class of all non-NSA gfx10 MIMG instructions.
210 class MIMG_gfx10<int op, dag outs, string dns = "">
211 : MIMG<outs, dns>, MIMGe_gfx10<op> {
212 let SubtargetPredicate = isGFX10Plus;
213 let AssemblerPredicate = isGFX10Plus;
215 let MIMGEncoding = MIMGEncGfx10Default;
217 let d16 = !if(BaseOpcode.HasD16, ?, 0);
221 // Base class for all NSA MIMG instructions. Note that 1-dword addresses always
222 // use non-NSA variants.
223 class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns="">
224 : MIMG<outs, dns>, MIMGe_gfx10<op> {
225 let SubtargetPredicate = isGFX10Plus;
226 let AssemblerPredicate = isGFX10Plus;
228 let MIMGEncoding = MIMGEncGfx10NSA;
230 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>;
231 dag AddrIns = nsah.AddrIns;
232 string AddrAsm = nsah.AddrAsm;
234 let d16 = !if(BaseOpcode.HasD16, ?, 0);
238 class MIMG_NoSampler_Helper <bits<8> op, string asm,
239 RegisterClass dst_rc,
240 RegisterClass addr_rc,
242 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> {
243 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
244 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
245 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
246 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
247 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
248 #!if(BaseOpcode.HasD16, "$d16", "");
251 class MIMG_NoSampler_gfx10<int op, string opcode,
252 RegisterClass DataRC, RegisterClass AddrRC,
254 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> {
255 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
256 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
257 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
258 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
259 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
260 #!if(BaseOpcode.HasD16, "$d16", "");
263 class MIMG_NoSampler_nsa_gfx10<int op, string opcode,
264 RegisterClass DataRC, int num_addrs,
266 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> {
267 let InOperandList = !con(AddrIns,
268 (ins SReg_256:$srsrc, DMask:$dmask,
269 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
270 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
271 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
272 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
273 #!if(BaseOpcode.HasD16, "$d16", "");
276 multiclass MIMG_NoSampler_Src_Helper <bits<8> op, string asm,
277 RegisterClass dst_rc,
280 let VAddrDwords = 1 in {
281 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
282 !if(enableDisasm, "AMDGPU", "")>;
283 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
284 !if(enableDisasm, "AMDGPU", "")>;
287 let VAddrDwords = 2 in {
288 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>;
289 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>;
290 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>;
293 let VAddrDwords = 3 in {
294 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>;
295 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>;
296 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>;
299 let VAddrDwords = 4 in {
300 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>;
301 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
302 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
303 !if(enableDisasm, "AMDGPU", "")>;
308 multiclass MIMG_NoSampler <bits<8> op, string asm, bit has_d16, bit mip = 0,
310 def "" : MIMGBaseOpcode {
311 let Coordinates = !if(isResInfo, 0, 1);
312 let LodOrClampOrMip = mip;
313 let HasD16 = has_d16;
316 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
317 mayLoad = !if(isResInfo, 0, 1) in {
318 let VDataDwords = 1 in
319 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
320 let VDataDwords = 2 in
321 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0>;
322 let VDataDwords = 3 in
323 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0>;
324 let VDataDwords = 4 in
325 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0>;
326 let VDataDwords = 5 in
327 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0>;
331 class MIMG_Store_Helper <bits<8> op, string asm,
332 RegisterClass data_rc,
333 RegisterClass addr_rc,
335 : MIMG_gfx6789<op, (outs), dns> {
336 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
337 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
338 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
339 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
340 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
341 #!if(BaseOpcode.HasD16, "$d16", "");
344 class MIMG_Store_gfx10<int op, string opcode,
345 RegisterClass DataRC, RegisterClass AddrRC,
347 : MIMG_gfx10<op, (outs), dns> {
348 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
349 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
350 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
351 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
352 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
353 #!if(BaseOpcode.HasD16, "$d16", "");
356 class MIMG_Store_nsa_gfx10<int op, string opcode,
357 RegisterClass DataRC, int num_addrs,
359 : MIMG_nsa_gfx10<op, (outs), num_addrs, dns> {
360 let InOperandList = !con((ins DataRC:$vdata),
362 (ins SReg_256:$srsrc, DMask:$dmask,
363 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
364 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
365 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
366 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
367 #!if(BaseOpcode.HasD16, "$d16", "");
370 multiclass MIMG_Store_Addr_Helper <int op, string asm,
371 RegisterClass data_rc,
373 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0,
374 DisableWQM = 1, ssamp = 0 in {
375 let VAddrDwords = 1 in {
376 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
377 !if(enableDisasm, "AMDGPU", "")>;
378 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32,
379 !if(enableDisasm, "AMDGPU", "")>;
381 let VAddrDwords = 2 in {
382 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>;
383 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>;
384 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>;
386 let VAddrDwords = 3 in {
387 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>;
388 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>;
389 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>;
391 let VAddrDwords = 4 in {
392 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>;
393 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>;
394 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4,
395 !if(enableDisasm, "AMDGPU", "")>;
400 multiclass MIMG_Store <bits<8> op, string asm, bit has_d16, bit mip = 0> {
401 def "" : MIMGBaseOpcode {
403 let LodOrClampOrMip = mip;
404 let HasD16 = has_d16;
407 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
408 let VDataDwords = 1 in
409 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
410 let VDataDwords = 2 in
411 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>;
412 let VDataDwords = 3 in
413 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>;
414 let VDataDwords = 4 in
415 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>;
419 class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
420 RegisterClass addr_rc, string dns="">
421 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
422 let Constraints = "$vdst = $vdata";
423 let AsmMatchConverter = "cvtMIMGAtomic";
425 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
426 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
427 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
428 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da";
431 class MIMG_Atomic_si<mimg op, string asm, RegisterClass data_rc,
432 RegisterClass addr_rc, bit enableDasm = 0>
433 : MIMG_Atomic_gfx6789_base<op.SI_GFX10, asm, data_rc, addr_rc,
434 !if(enableDasm, "GFX6GFX7", "")> {
435 let AssemblerPredicate = isGFX6GFX7;
438 class MIMG_Atomic_vi<mimg op, string asm, RegisterClass data_rc,
439 RegisterClass addr_rc, bit enableDasm = 0>
440 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> {
441 let AssemblerPredicate = isGFX8GFX9;
442 let MIMGEncoding = MIMGEncGfx8;
445 class MIMG_Atomic_gfx10<mimg op, string opcode,
446 RegisterClass DataRC, RegisterClass AddrRC,
447 bit enableDisasm = 0>
448 : MIMG_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst),
449 !if(enableDisasm, "AMDGPU", "")> {
450 let Constraints = "$vdst = $vdata";
451 let AsmMatchConverter = "cvtMIMGAtomic";
453 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
454 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
455 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe);
456 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe";
459 class MIMG_Atomic_nsa_gfx10<mimg op, string opcode,
460 RegisterClass DataRC, int num_addrs,
461 bit enableDisasm = 0>
462 : MIMG_nsa_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), num_addrs,
463 !if(enableDisasm, "AMDGPU", "")> {
464 let Constraints = "$vdst = $vdata";
465 let AsmMatchConverter = "cvtMIMGAtomic";
467 let InOperandList = !con((ins DataRC:$vdata),
469 (ins SReg_256:$srsrc, DMask:$dmask,
470 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
471 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe));
472 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe";
475 multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm,
476 RegisterClass data_rc,
477 bit enableDasm = 0> {
478 let hasSideEffects = 1, // FIXME: remove this
479 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1,
481 let VAddrDwords = 1 in {
482 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>;
483 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>;
484 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>;
486 let VAddrDwords = 2 in {
487 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>;
488 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>;
489 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>;
490 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>;
492 let VAddrDwords = 3 in {
493 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>;
494 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>;
495 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>;
496 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>;
498 let VAddrDwords = 4 in {
499 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>;
500 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>;
501 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>;
502 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>;
507 multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics
508 def "" : MIMGBaseOpcode {
510 let AtomicX2 = isCmpSwap;
513 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
514 // _V* variants have different dst size, but the size is encoded implicitly,
515 // using dmask and tfe. Only 32-bit variant is registered with disassembler.
516 // Other variants are reconstructed by disassembler using dmask and tfe.
517 let VDataDwords = !if(isCmpSwap, 2, 1) in
518 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1>;
519 let VDataDwords = !if(isCmpSwap, 4, 2) in
520 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64)>;
524 class MIMG_Sampler_Helper <bits<8> op, string asm, RegisterClass dst_rc,
525 RegisterClass src_rc, string dns="">
526 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> {
527 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
528 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
529 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
530 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
531 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da"
532 #!if(BaseOpcode.HasD16, "$d16", "");
535 class MIMG_Sampler_gfx10<int op, string opcode,
536 RegisterClass DataRC, RegisterClass AddrRC,
538 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> {
539 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp,
540 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
541 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
542 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
543 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm"
544 #"$dlc$glc$slc$r128$a16$tfe$lwe"
545 #!if(BaseOpcode.HasD16, "$d16", "");
548 class MIMG_Sampler_nsa_gfx10<int op, string opcode,
549 RegisterClass DataRC, int num_addrs,
551 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> {
552 let InOperandList = !con(AddrIns,
553 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask,
554 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
555 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
556 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
557 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm"
558 #"$dlc$glc$slc$r128$a16$tfe$lwe"
559 #!if(BaseOpcode.HasD16, "$d16", "");
562 class MIMGAddrSize<int dw, bit enable_disasm> {
565 RegisterClass RegClass = !if(!le(NumWords, 0), ?,
566 !if(!eq(NumWords, 1), VGPR_32,
567 !if(!eq(NumWords, 2), VReg_64,
568 !if(!eq(NumWords, 3), VReg_96,
569 !if(!eq(NumWords, 4), VReg_128,
570 !if(!le(NumWords, 8), VReg_256,
571 !if(!le(NumWords, 16), VReg_512, ?)))))));
573 // Whether the instruction variant with this vaddr size should be enabled for
574 // the auto-generated disassembler.
575 bit Disassemble = enable_disasm;
578 // Return whether x is in lst.
579 class isIntInList<int x, list<int> lst> {
580 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y)));
583 // Return whether a value inside the range [min, max] (endpoints inclusive)
584 // is in the given list.
585 class isRangeInList<int min, int max, list<int> lst> {
586 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max))));
589 class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> {
590 list<MIMGAddrSize> List = lst;
594 class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
595 // List of all possible numbers of address words, taking all combinations of
596 // A16 and image dimension into account (note: no MSAA, since this is for
597 // sample/gather ops).
598 list<int> AllNumAddrWords =
599 !foreach(dw, !if(sample.Gradients,
600 !if(!eq(sample.LodOrClamp, ""),
601 [2, 3, 4, 5, 6, 7, 9],
602 [2, 3, 4, 5, 7, 8, 10]),
603 !if(!eq(sample.LodOrClamp, ""),
606 !add(dw, !size(sample.ExtraAddrArgs)));
608 // Generate machine instructions based on possible register classes for the
609 // required numbers of address words. The disassembler defaults to the
610 // smallest register class.
611 list<MIMGAddrSize> MachineInstrs =
612 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw,
613 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret,
615 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]),
616 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords
619 // For NSA, generate machine instructions for all possible numbers of words
620 // except 1 (which is already covered by the non-NSA case).
621 // The disassembler defaults to the largest number of arguments among the
622 // variants with the same number of NSA words, and custom code then derives
623 // the exact variant based on the sample variant and the image dimension.
624 list<MIMGAddrSize> NSAInstrs =
625 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group,
627 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw,
628 !if(isIntInList<dw, AllNumAddrWords>.ret,
629 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]),
633 multiclass MIMG_Sampler_Src_Helper <bits<8> op, string asm,
634 AMDGPUSampleVariant sample, RegisterClass dst_rc,
635 bit enableDisasm = 0> {
636 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in {
637 let VAddrDwords = addr.NumWords in {
638 def _V # addr.NumWords
639 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
640 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
641 def _V # addr.NumWords # _gfx10
642 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass,
643 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
647 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in {
648 let VAddrDwords = addr.NumWords in {
649 def _V # addr.NumWords # _nsa_gfx10
650 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords,
651 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
656 class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample>
659 let NumExtraArgs = !size(sample.ExtraAddrArgs);
660 let Gradients = sample.Gradients;
661 let LodOrClampOrMip = !ne(sample.LodOrClamp, "");
664 multiclass MIMG_Sampler <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
665 bit isG16 = 0, bit isGetLod = 0,
666 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", "")> {
667 def "" : MIMG_Sampler_BaseOpcode<sample> {
668 let HasD16 = !if(isGetLod, 0, 1);
672 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
673 mayLoad = !if(isGetLod, 0, 1) in {
674 let VDataDwords = 1 in
675 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1>;
676 let VDataDwords = 2 in
677 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>;
678 let VDataDwords = 3 in
679 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96>;
680 let VDataDwords = 4 in
681 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128>;
682 let VDataDwords = 5 in
683 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>;
687 multiclass MIMG_Sampler_WQM <bits<8> op, AMDGPUSampleVariant sample>
688 : MIMG_Sampler<op, sample, 1>;
690 multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
691 string asm = "image_gather4"#sample.LowerCaseMod> {
692 def "" : MIMG_Sampler_BaseOpcode<sample> {
697 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
698 Gather4 = 1, hasPostISelHook = 0 in {
699 let VDataDwords = 2 in
700 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */
701 let VDataDwords = 4 in
702 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>;
703 let VDataDwords = 5 in
704 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>;
708 multiclass MIMG_Gather_WQM <bits<8> op, AMDGPUSampleVariant sample>
709 : MIMG_Gather<op, sample, 1>;
711 //===----------------------------------------------------------------------===//
713 //===----------------------------------------------------------------------===//
714 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>;
715 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>;
716 defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>;
717 defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>;
718 defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>;
719 defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>;
720 defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>;
721 defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>;
722 defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>;
723 defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>;
725 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>;
727 defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
728 defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>;
729 defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
730 defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">;
731 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI
732 defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">;
733 defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">;
734 defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">;
735 defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">;
736 defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">;
737 defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
738 defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
739 defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
740 defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
741 //let FPAtomic = 1 in {
742 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI
743 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
744 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
745 //} // End let FPAtomic = 1
746 defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>;
747 defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>;
748 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>;
749 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>;
750 defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <0x000000a2, AMDGPUSample_d, 0, 1>;
751 defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <0x000000a3, AMDGPUSample_d_cl, 0, 1>;
752 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>;
753 defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>;
754 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>;
755 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>;
756 defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>;
757 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>;
758 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>;
759 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>;
760 defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <0x000000aa, AMDGPUSample_c_d, 0, 1>;
761 defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <0x000000ab, AMDGPUSample_c_d_cl, 0, 1>;
762 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>;
763 defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>;
764 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>;
765 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>;
766 defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>;
767 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>;
768 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>;
769 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>;
770 defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <0x000000b2, AMDGPUSample_d_o, 0, 1>;
771 defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <0x000000b3, AMDGPUSample_d_cl_o, 0, 1>;
772 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>;
773 defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>;
774 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>;
775 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>;
776 defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>;
777 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>;
778 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>;
779 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>;
780 defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <0x000000ba, AMDGPUSample_c_d_o, 0, 1>;
781 defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <0x000000bb, AMDGPUSample_c_d_cl_o, 0, 1>;
782 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>;
783 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>;
784 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>;
785 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>;
786 defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>;
787 defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>;
788 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>;
789 defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>;
790 defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>;
791 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>;
792 defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>;
793 defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>;
794 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>;
795 defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>;
796 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>;
797 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>;
798 defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>;
799 defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>;
800 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>;
801 defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>;
802 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>;
803 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>;
804 defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>;
805 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>;
806 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>;
807 defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>;
808 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>;
809 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>;
811 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 0, 1, "image_get_lod">;
813 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>;
814 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>;
815 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>;
816 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>;
817 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>;
818 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>;
819 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>;
820 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>;
821 defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <0x000000e8, AMDGPUSample_cd, 0, 1>;
822 defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <0x000000e9, AMDGPUSample_cd_cl, 0, 1>;
823 defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <0x000000ea, AMDGPUSample_c_cd, 0, 1>;
824 defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <0x000000eb, AMDGPUSample_c_cd_cl, 0, 1>;
825 defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <0x000000ec, AMDGPUSample_cd_o, 0, 1>;
826 defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <0x000000ed, AMDGPUSample_cd_cl_o, 0, 1>;
827 defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <0x000000ee, AMDGPUSample_c_cd_o, 0, 1>;
828 defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <0x000000ef, AMDGPUSample_c_cd_cl_o, 0, 1>;
829 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
830 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
832 let SubtargetPredicate = HasGFX10_BEncoding in
833 defm IMAGE_MSAA_LOAD : MIMG_NoSampler <0x00000080, "image_msaa_load", 1>;
835 /********** ========================================= **********/
836 /********** Table of dimension-aware image intrinsics **********/
837 /********** ========================================= **********/
839 class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> {
841 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod));
842 AMDGPUDimProps Dim = I.P.Dim;
845 def ImageDimIntrinsicTable : GenericTable {
846 let FilterClass = "ImageDimIntrinsicInfo";
847 let Fields = ["Intr", "BaseOpcode", "Dim"];
848 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode;
849 GenericEnum TypeOf_Dim = MIMGDim;
851 let PrimaryKey = ["Intr"];
852 let PrimaryKeyName = "getImageDimIntrinsicInfo";
853 let PrimaryKeyEarlyOut = 1;
856 def getImageDimInstrinsicByBaseOpcode : SearchIndex {
857 let Table = ImageDimIntrinsicTable;
858 let Key = ["BaseOpcode", "Dim"];
861 foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
862 AMDGPUImageDimAtomicIntrinsics) in {
863 def : ImageDimIntrinsicInfo<intr>;
866 // L to LZ Optimization Mapping
867 def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>;
868 def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>;
869 def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>;
870 def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>;
871 def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>;
872 def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>;
873 def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>;
874 def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>;
876 // MIP to NONMIP Optimization Mapping
877 def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>;
878 def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>;
880 // G to G16 Optimization Mapping
881 def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>;
882 def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>;
883 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>;
884 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>;
885 def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>;
886 def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>;
887 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>;
888 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>;
889 def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>;
890 def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>;
891 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>;
892 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>;
893 def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>;
894 def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>;
895 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>;
896 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>;