1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Custom DAG lowering for R600
12 //===----------------------------------------------------------------------===//
14 #include "R600ISelLowering.h"
15 #include "AMDGPUFrameLowering.h"
16 #include "AMDGPUSubtarget.h"
17 #include "R600Defines.h"
18 #include "R600FrameLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/APInt.h"
25 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/DAGCombine.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/IntrinsicsR600.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include "llvm/Support/MathExtras.h"
54 #include "R600GenCallingConv.inc"
56 R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
57 const R600Subtarget &STI)
58 : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
59 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
61 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
62 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass);
63 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass);
66 setBooleanContents(ZeroOrNegativeOneBooleanContent);
67 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
69 computeRegisterProperties(Subtarget->getRegisterInfo());
71 // Legalize loads and stores to the private address space.
72 setOperationAction(ISD::LOAD, MVT::i32, Custom);
73 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
76 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
77 // spaces, so it is custom lowered to handle those where it isn't.
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
85 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
87 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
88 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
89 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
92 // Workaround for LegalizeDAG asserting on expansion of i1 vector loads.
93 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
94 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
97 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
101 setOperationAction(ISD::STORE, MVT::i8, Custom);
102 setOperationAction(ISD::STORE, MVT::i32, Custom);
103 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
104 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
106 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
107 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
108 // We need to include these since trunc STORES to PRIVATE need
109 // special handling to accommodate RMW
110 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
111 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom);
112 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Custom);
113 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom);
114 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom);
115 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
116 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
117 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom);
118 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Custom);
119 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom);
121 // Workaround for LegalizeDAG asserting on expansion of i1 vector stores.
122 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand);
123 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
125 // Set condition code actions
126 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
127 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
128 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
129 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
131 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
134 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
136 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
137 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
139 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
140 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
141 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
144 setOperationAction(ISD::FCOS, MVT::f32, Custom);
145 setOperationAction(ISD::FSIN, MVT::f32, Custom);
147 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
148 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
150 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
151 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
152 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
154 setOperationAction(ISD::FSUB, MVT::f32, Expand);
156 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
157 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
158 setOperationAction(ISD::FRINT, MVT::f64, Custom);
159 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
161 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
162 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
164 setOperationAction(ISD::SETCC, MVT::i32, Expand);
165 setOperationAction(ISD::SETCC, MVT::f32, Expand);
166 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
167 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
168 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
169 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
171 setOperationAction(ISD::SELECT, MVT::i32, Expand);
172 setOperationAction(ISD::SELECT, MVT::f32, Expand);
173 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
174 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
176 // ADD, SUB overflow.
177 // TODO: turn these into Legal?
178 if (Subtarget->hasCARRY())
179 setOperationAction(ISD::UADDO, MVT::i32, Custom);
181 if (Subtarget->hasBORROW())
182 setOperationAction(ISD::USUBO, MVT::i32, Custom);
184 // Expand sign extension of vectors
185 if (!Subtarget->hasBFE())
186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
191 if (!Subtarget->hasBFE())
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
196 if (!Subtarget->hasBFE())
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
205 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
207 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
209 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
210 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
211 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
214 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
215 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
216 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
217 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
219 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
220 // to be Legal/Custom in order to avoid library calls.
221 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
222 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
223 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
225 if (!Subtarget->hasFMA()) {
226 setOperationAction(ISD::FMA, MVT::f32, Expand);
227 setOperationAction(ISD::FMA, MVT::f64, Expand);
230 // FIXME: May need no denormals check
231 setOperationAction(ISD::FMAD, MVT::f32, Legal);
233 if (!Subtarget->hasBFI()) {
234 // fcopysign can be done in a single instruction with BFI.
235 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
236 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
239 if (!Subtarget->hasBCNT(32))
240 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
242 if (!Subtarget->hasBCNT(64))
243 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
245 if (Subtarget->hasFFBH())
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
248 if (Subtarget->hasFFBL())
249 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
251 // FIXME: This was moved from AMDGPUTargetLowering, I'm not sure if we
253 if (Subtarget->hasBFE())
254 setHasExtractBitsInsn(true);
256 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
258 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
259 for (MVT VT : ScalarIntVTs) {
260 setOperationAction(ISD::ADDC, VT, Expand);
261 setOperationAction(ISD::SUBC, VT, Expand);
262 setOperationAction(ISD::ADDE, VT, Expand);
263 setOperationAction(ISD::SUBE, VT, Expand);
266 // LLVM will expand these to atomic_cmp_swap(0)
267 // and atomic_swap, respectively.
268 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
269 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
271 // We need to custom lower some of the intrinsics
272 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
273 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
275 setSchedulingPreference(Sched::Source);
277 setTargetDAGCombine(ISD::FP_ROUND);
278 setTargetDAGCombine(ISD::FP_TO_SINT);
279 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
280 setTargetDAGCombine(ISD::SELECT_CC);
281 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
282 setTargetDAGCombine(ISD::LOAD);
285 static inline bool isEOP(MachineBasicBlock::iterator I) {
286 if (std::next(I) == I->getParent()->end())
288 return std::next(I)->getOpcode() == R600::RETURN;
292 R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
293 MachineBasicBlock *BB) const {
294 MachineFunction *MF = BB->getParent();
295 MachineRegisterInfo &MRI = MF->getRegInfo();
296 MachineBasicBlock::iterator I = MI;
297 const R600InstrInfo *TII = Subtarget->getInstrInfo();
299 switch (MI.getOpcode()) {
301 // Replace LDS_*_RET instruction that don't have any uses with the
302 // equivalent LDS_*_NORET instruction.
303 if (TII->isLDSRetInstr(MI.getOpcode())) {
304 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
305 assert(DstIdx != -1);
306 MachineInstrBuilder NewMI;
307 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
308 // LDS_1A2D support and remove this special case.
309 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
310 MI.getOpcode() == R600::LDS_CMPST_RET)
313 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
314 TII->get(R600::getLDSNoRetOp(MI.getOpcode())));
315 for (unsigned i = 1, e = MI.getNumOperands(); i < e; ++i) {
316 NewMI.add(MI.getOperand(i));
319 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
323 case R600::FABS_R600: {
324 MachineInstr *NewMI = TII->buildDefaultInstruction(
325 *BB, I, R600::MOV, MI.getOperand(0).getReg(),
326 MI.getOperand(1).getReg());
327 TII->addFlag(*NewMI, 0, MO_FLAG_ABS);
331 case R600::FNEG_R600: {
332 MachineInstr *NewMI = TII->buildDefaultInstruction(
333 *BB, I, R600::MOV, MI.getOperand(0).getReg(),
334 MI.getOperand(1).getReg());
335 TII->addFlag(*NewMI, 0, MO_FLAG_NEG);
339 case R600::MASK_WRITE: {
340 Register maskedRegister = MI.getOperand(0).getReg();
341 assert(Register::isVirtualRegister(maskedRegister));
342 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
343 TII->addFlag(*defInstr, 0, MO_FLAG_MASK);
347 case R600::MOV_IMM_F32:
348 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1)
355 case R600::MOV_IMM_I32:
356 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(),
357 MI.getOperand(1).getImm());
360 case R600::MOV_IMM_GLOBAL_ADDR: {
361 //TODO: Perhaps combine this instruction with the next if possible
362 auto MIB = TII->buildDefaultInstruction(
363 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X);
364 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal);
365 //TODO: Ugh this is rather ugly
366 MIB->getOperand(Idx) = MI.getOperand(1);
370 case R600::CONST_COPY: {
371 MachineInstr *NewMI = TII->buildDefaultInstruction(
372 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST);
373 TII->setImmOperand(*NewMI, R600::OpName::src0_sel,
374 MI.getOperand(1).getImm());
378 case R600::RAT_WRITE_CACHELESS_32_eg:
379 case R600::RAT_WRITE_CACHELESS_64_eg:
380 case R600::RAT_WRITE_CACHELESS_128_eg:
381 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
382 .add(MI.getOperand(0))
383 .add(MI.getOperand(1))
384 .addImm(isEOP(I)); // Set End of program bit
387 case R600::RAT_STORE_TYPED_eg:
388 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
389 .add(MI.getOperand(0))
390 .add(MI.getOperand(1))
391 .add(MI.getOperand(2))
392 .addImm(isEOP(I)); // Set End of program bit
396 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP))
397 .add(MI.getOperand(0));
400 case R600::BRANCH_COND_f32: {
401 MachineInstr *NewMI =
402 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
404 .add(MI.getOperand(1))
405 .addImm(R600::PRED_SETNE)
407 TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
408 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
409 .add(MI.getOperand(0))
410 .addReg(R600::PREDICATE_BIT, RegState::Kill);
414 case R600::BRANCH_COND_i32: {
415 MachineInstr *NewMI =
416 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
418 .add(MI.getOperand(1))
419 .addImm(R600::PRED_SETNE_INT)
421 TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
422 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
423 .add(MI.getOperand(0))
424 .addReg(R600::PREDICATE_BIT, RegState::Kill);
428 case R600::EG_ExportSwz:
429 case R600::R600_ExportSwz: {
430 // Instruction is left unmodified if its not the last one of its type
431 bool isLastInstructionOfItsType = true;
432 unsigned InstExportType = MI.getOperand(1).getImm();
433 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
434 EndBlock = BB->end(); NextExportInst != EndBlock;
435 NextExportInst = std::next(NextExportInst)) {
436 if (NextExportInst->getOpcode() == R600::EG_ExportSwz ||
437 NextExportInst->getOpcode() == R600::R600_ExportSwz) {
438 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
440 if (CurrentInstExportType == InstExportType) {
441 isLastInstructionOfItsType = false;
447 if (!EOP && !isLastInstructionOfItsType)
449 unsigned CfInst = (MI.getOpcode() == R600::EG_ExportSwz) ? 84 : 40;
450 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
451 .add(MI.getOperand(0))
452 .add(MI.getOperand(1))
453 .add(MI.getOperand(2))
454 .add(MI.getOperand(3))
455 .add(MI.getOperand(4))
456 .add(MI.getOperand(5))
457 .add(MI.getOperand(6))
467 MI.eraseFromParent();
471 //===----------------------------------------------------------------------===//
472 // Custom DAG Lowering Operations
473 //===----------------------------------------------------------------------===//
475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
476 MachineFunction &MF = DAG.getMachineFunction();
477 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
478 switch (Op.getOpcode()) {
479 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
480 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
482 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
484 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
485 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
486 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
488 case ISD::FSIN: return LowerTrig(Op, DAG);
489 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
490 case ISD::STORE: return LowerSTORE(Op, DAG);
492 SDValue Result = LowerLOAD(Op, DAG);
493 assert((!Result.getNode() ||
494 Result.getNode()->getNumValues() == 2) &&
495 "Load should return a value and a chain");
499 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
500 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
501 case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
502 case ISD::INTRINSIC_VOID: {
503 SDValue Chain = Op.getOperand(0);
504 unsigned IntrinsicID =
505 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
506 switch (IntrinsicID) {
507 case Intrinsic::r600_store_swizzle: {
509 const SDValue Args[8] = {
511 Op.getOperand(2), // Export Value
512 Op.getOperand(3), // ArrayBase
513 Op.getOperand(4), // Type
514 DAG.getConstant(0, DL, MVT::i32), // SWZ_X
515 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
516 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
517 DAG.getConstant(3, DL, MVT::i32) // SWZ_W
519 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
522 // default for switch(IntrinsicID)
525 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
528 case ISD::INTRINSIC_WO_CHAIN: {
529 unsigned IntrinsicID =
530 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
531 EVT VT = Op.getValueType();
533 switch (IntrinsicID) {
534 case Intrinsic::r600_tex:
535 case Intrinsic::r600_texc: {
537 switch (IntrinsicID) {
538 case Intrinsic::r600_tex:
541 case Intrinsic::r600_texc:
545 llvm_unreachable("unhandled texture operation");
548 SDValue TexArgs[19] = {
549 DAG.getConstant(TextureOp, DL, MVT::i32),
551 DAG.getConstant(0, DL, MVT::i32),
552 DAG.getConstant(1, DL, MVT::i32),
553 DAG.getConstant(2, DL, MVT::i32),
554 DAG.getConstant(3, DL, MVT::i32),
558 DAG.getConstant(0, DL, MVT::i32),
559 DAG.getConstant(1, DL, MVT::i32),
560 DAG.getConstant(2, DL, MVT::i32),
561 DAG.getConstant(3, DL, MVT::i32),
569 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
571 case Intrinsic::r600_dot4: {
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
574 DAG.getConstant(0, DL, MVT::i32)),
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
576 DAG.getConstant(0, DL, MVT::i32)),
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
578 DAG.getConstant(1, DL, MVT::i32)),
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
580 DAG.getConstant(1, DL, MVT::i32)),
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
582 DAG.getConstant(2, DL, MVT::i32)),
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
584 DAG.getConstant(2, DL, MVT::i32)),
585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
586 DAG.getConstant(3, DL, MVT::i32)),
587 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
588 DAG.getConstant(3, DL, MVT::i32))
590 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
593 case Intrinsic::r600_implicitarg_ptr: {
594 MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS);
595 uint32_t ByteOffset = getImplicitParameterOffset(MF, FIRST_IMPLICIT);
596 return DAG.getConstant(ByteOffset, DL, PtrVT);
598 case Intrinsic::r600_read_ngroups_x:
599 return LowerImplicitParameter(DAG, VT, DL, 0);
600 case Intrinsic::r600_read_ngroups_y:
601 return LowerImplicitParameter(DAG, VT, DL, 1);
602 case Intrinsic::r600_read_ngroups_z:
603 return LowerImplicitParameter(DAG, VT, DL, 2);
604 case Intrinsic::r600_read_global_size_x:
605 return LowerImplicitParameter(DAG, VT, DL, 3);
606 case Intrinsic::r600_read_global_size_y:
607 return LowerImplicitParameter(DAG, VT, DL, 4);
608 case Intrinsic::r600_read_global_size_z:
609 return LowerImplicitParameter(DAG, VT, DL, 5);
610 case Intrinsic::r600_read_local_size_x:
611 return LowerImplicitParameter(DAG, VT, DL, 6);
612 case Intrinsic::r600_read_local_size_y:
613 return LowerImplicitParameter(DAG, VT, DL, 7);
614 case Intrinsic::r600_read_local_size_z:
615 return LowerImplicitParameter(DAG, VT, DL, 8);
617 case Intrinsic::r600_read_tgid_x:
618 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
620 case Intrinsic::r600_read_tgid_y:
621 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
623 case Intrinsic::r600_read_tgid_z:
624 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
626 case Intrinsic::r600_read_tidig_x:
627 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
629 case Intrinsic::r600_read_tidig_y:
630 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
632 case Intrinsic::r600_read_tidig_z:
633 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
636 case Intrinsic::r600_recipsqrt_ieee:
637 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
639 case Intrinsic::r600_recipsqrt_clamped:
640 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
645 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
648 } // end switch(Op.getOpcode())
652 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
653 SmallVectorImpl<SDValue> &Results,
654 SelectionDAG &DAG) const {
655 switch (N->getOpcode()) {
657 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
659 case ISD::FP_TO_UINT:
660 if (N->getValueType(0) == MVT::i1) {
661 Results.push_back(lowerFP_TO_UINT(N->getOperand(0), DAG));
664 // Since we don't care about out of bounds values we can use FP_TO_SINT for
665 // uints too. The DAGLegalizer code for uint considers some extra cases
666 // which are not necessary here.
668 case ISD::FP_TO_SINT: {
669 if (N->getValueType(0) == MVT::i1) {
670 Results.push_back(lowerFP_TO_SINT(N->getOperand(0), DAG));
675 if (expandFP_TO_SINT(N, Result, DAG))
676 Results.push_back(Result);
680 SDValue Op = SDValue(N, 1);
681 SDValue RES = LowerSDIVREM(Op, DAG);
682 Results.push_back(RES);
683 Results.push_back(RES.getValue(1));
687 SDValue Op = SDValue(N, 0);
688 LowerUDIVREM64(Op, DAG, Results);
694 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
695 SDValue Vector) const {
697 EVT VecVT = Vector.getValueType();
698 EVT EltVT = VecVT.getVectorElementType();
699 SmallVector<SDValue, 8> Args;
701 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
702 Args.push_back(DAG.getNode(
703 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
704 DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout()))));
707 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
710 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
711 SelectionDAG &DAG) const {
713 SDValue Vector = Op.getOperand(0);
714 SDValue Index = Op.getOperand(1);
716 if (isa<ConstantSDNode>(Index) ||
717 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
720 Vector = vectorToVerticalVector(DAG, Vector);
721 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
725 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
726 SelectionDAG &DAG) const {
728 SDValue Vector = Op.getOperand(0);
729 SDValue Value = Op.getOperand(1);
730 SDValue Index = Op.getOperand(2);
732 if (isa<ConstantSDNode>(Index) ||
733 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
736 Vector = vectorToVerticalVector(DAG, Vector);
737 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
738 Vector, Value, Index);
739 return vectorToVerticalVector(DAG, Insert);
742 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
744 SelectionDAG &DAG) const {
745 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
746 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
747 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
749 const DataLayout &DL = DAG.getDataLayout();
750 const GlobalValue *GV = GSD->getGlobal();
751 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
753 SDValue GA = DAG.getTargetGlobalAddress(GV, SDLoc(GSD), ConstPtrVT);
754 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(GSD), ConstPtrVT, GA);
757 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
758 // On hw >= R700, COS/SIN input must be between -1. and 1.
759 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
760 EVT VT = Op.getValueType();
761 SDValue Arg = Op.getOperand(0);
764 // TODO: Should this propagate fast-math-flags?
765 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
766 DAG.getNode(ISD::FADD, DL, VT,
767 DAG.getNode(ISD::FMUL, DL, VT, Arg,
768 DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
769 DAG.getConstantFP(0.5, DL, MVT::f32)));
771 switch (Op.getOpcode()) {
773 TrigNode = AMDGPUISD::COS_HW;
776 TrigNode = AMDGPUISD::SIN_HW;
779 llvm_unreachable("Wrong trig opcode");
781 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
782 DAG.getNode(ISD::FADD, DL, VT, FractPart,
783 DAG.getConstantFP(-0.5, DL, MVT::f32)));
784 if (Gen >= AMDGPUSubtarget::R700)
786 // On R600 hw, COS/SIN input must be between -Pi and Pi.
787 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
788 DAG.getConstantFP(numbers::pif, DL, MVT::f32));
791 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
793 EVT VT = Op.getValueType();
795 SDValue Lo = Op.getOperand(0);
796 SDValue Hi = Op.getOperand(1);
797 SDValue Shift = Op.getOperand(2);
798 SDValue Zero = DAG.getConstant(0, DL, VT);
799 SDValue One = DAG.getConstant(1, DL, VT);
801 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
802 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
803 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
804 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
806 // The dance around Width1 is necessary for 0 special case.
807 // Without it the CompShift might be 32, producing incorrect results in
808 // Overflow. So we do the shift in two steps, the alternative is to
809 // add a conditional to filter the special case.
811 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
812 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
814 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
815 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
816 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
818 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
819 SDValue LoBig = Zero;
821 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
822 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
824 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
827 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
829 EVT VT = Op.getValueType();
831 SDValue Lo = Op.getOperand(0);
832 SDValue Hi = Op.getOperand(1);
833 SDValue Shift = Op.getOperand(2);
834 SDValue Zero = DAG.getConstant(0, DL, VT);
835 SDValue One = DAG.getConstant(1, DL, VT);
837 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
839 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
840 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
841 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
842 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
844 // The dance around Width1 is necessary for 0 special case.
845 // Without it the CompShift might be 32, producing incorrect results in
846 // Overflow. So we do the shift in two steps, the alternative is to
847 // add a conditional to filter the special case.
849 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
850 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
852 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
853 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
854 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
856 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
857 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
859 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
860 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
862 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
865 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
866 unsigned mainop, unsigned ovf) const {
868 EVT VT = Op.getValueType();
870 SDValue Lo = Op.getOperand(0);
871 SDValue Hi = Op.getOperand(1);
873 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
875 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
876 DAG.getValueType(MVT::i1));
878 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
880 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
883 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
889 Op, DAG.getConstantFP(1.0f, DL, MVT::f32),
890 DAG.getCondCode(ISD::SETEQ));
893 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
899 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32),
900 DAG.getCondCode(ISD::SETEQ));
903 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
905 unsigned DwordOffset) const {
906 unsigned ByteOffset = DwordOffset * 4;
907 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
908 AMDGPUAS::PARAM_I_ADDRESS);
910 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
911 assert(isInt<16>(ByteOffset));
913 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
914 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
915 MachinePointerInfo(ConstantPointerNull::get(PtrType)));
918 bool R600TargetLowering::isZero(SDValue Op) const {
919 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
920 return Cst->isNullValue();
921 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
922 return CstFP->isZero();
928 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
929 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
930 return CFP->isExactlyValue(1.0);
932 return isAllOnesConstant(Op);
935 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
936 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
937 return CFP->getValueAPF().isZero();
939 return isNullConstant(Op);
942 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
944 EVT VT = Op.getValueType();
946 SDValue LHS = Op.getOperand(0);
947 SDValue RHS = Op.getOperand(1);
948 SDValue True = Op.getOperand(2);
949 SDValue False = Op.getOperand(3);
950 SDValue CC = Op.getOperand(4);
953 if (VT == MVT::f32) {
954 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
955 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
960 // LHS and RHS are guaranteed to be the same value type
961 EVT CompareVT = LHS.getValueType();
963 // Check if we can lower this to a native operation.
965 // Try to lower to a SET* instruction:
967 // SET* can match the following patterns:
969 // select_cc f32, f32, -1, 0, cc_supported
970 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
971 // select_cc i32, i32, -1, 0, cc_supported
974 // Move hardware True/False values to the correct operand.
975 if (isHWTrueValue(False) && isHWFalseValue(True)) {
976 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
977 ISD::CondCode InverseCC = ISD::getSetCCInverse(CCOpcode, CompareVT);
978 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
979 std::swap(False, True);
980 CC = DAG.getCondCode(InverseCC);
982 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
983 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
984 std::swap(False, True);
986 CC = DAG.getCondCode(SwapInvCC);
991 if (isHWTrueValue(True) && isHWFalseValue(False) &&
992 (CompareVT == VT || VT == MVT::i32)) {
993 // This can be matched by a SET* instruction.
994 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
997 // Try to lower to a CND* instruction:
999 // CND* can match the following patterns:
1001 // select_cc f32, 0.0, f32, f32, cc_supported
1002 // select_cc f32, 0.0, i32, i32, cc_supported
1003 // select_cc i32, 0, f32, f32, cc_supported
1004 // select_cc i32, 0, i32, i32, cc_supported
1007 // Try to move the zero value to the RHS
1009 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1010 // Try swapping the operands
1011 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1012 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1013 std::swap(LHS, RHS);
1014 CC = DAG.getCondCode(CCSwapped);
1016 // Try inverting the conditon and then swapping the operands
1017 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT);
1018 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1019 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1020 std::swap(True, False);
1021 std::swap(LHS, RHS);
1022 CC = DAG.getCondCode(CCSwapped);
1029 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1030 if (CompareVT != VT) {
1031 // Bitcast True / False to the correct types. This will end up being
1032 // a nop, but it allows us to define only a single pattern in the
1033 // .TD files for each CND* instruction rather than having to have
1034 // one pattern for integer True/False and one for fp True/False
1035 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1036 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1043 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT);
1051 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1054 DAG.getCondCode(CCOpcode));
1055 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1058 // If we make it this for it means we have no native instructions to handle
1059 // this SELECT_CC, so we must lower it.
1060 SDValue HWTrue, HWFalse;
1062 if (CompareVT == MVT::f32) {
1063 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
1064 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
1065 } else if (CompareVT == MVT::i32) {
1066 HWTrue = DAG.getConstant(-1, DL, CompareVT);
1067 HWFalse = DAG.getConstant(0, DL, CompareVT);
1070 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1073 // Lower this unsupported SELECT_CC into a combination of two supported
1074 // SELECT_CC operations.
1075 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1077 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1080 DAG.getCondCode(ISD::SETNE));
1083 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1084 /// convert these pointers to a register index. Each register holds
1085 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1086 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1087 /// for indirect addressing.
1088 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1089 unsigned StackWidth,
1090 SelectionDAG &DAG) const {
1092 switch(StackWidth) {
1102 default: llvm_unreachable("Invalid stack width");
1106 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1107 DAG.getConstant(SRLPad, DL, MVT::i32));
1110 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1113 unsigned &PtrIncr) const {
1114 switch (StackWidth) {
1125 Channel = ElemIdx % 2;
1139 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
1140 SelectionDAG &DAG) const {
1142 //TODO: Who creates the i8 stores?
1143 assert(Store->isTruncatingStore()
1144 || Store->getValue().getValueType() == MVT::i8);
1145 assert(Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS);
1148 if (Store->getMemoryVT() == MVT::i8) {
1149 assert(Store->getAlignment() >= 1);
1150 Mask = DAG.getConstant(0xff, DL, MVT::i32);
1151 } else if (Store->getMemoryVT() == MVT::i16) {
1152 assert(Store->getAlignment() >= 2);
1153 Mask = DAG.getConstant(0xffff, DL, MVT::i32);
1155 llvm_unreachable("Unsupported private trunc store");
1158 SDValue OldChain = Store->getChain();
1159 bool VectorTrunc = (OldChain.getOpcode() == AMDGPUISD::DUMMY_CHAIN);
1161 SDValue Chain = VectorTrunc ? OldChain->getOperand(0) : OldChain;
1162 SDValue BasePtr = Store->getBasePtr();
1163 SDValue Offset = Store->getOffset();
1164 EVT MemVT = Store->getMemoryVT();
1166 SDValue LoadPtr = BasePtr;
1167 if (!Offset.isUndef()) {
1168 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1171 // Get dword location
1172 // TODO: this should be eliminated by the future SHR ptr, 2
1173 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1174 DAG.getConstant(0xfffffffc, DL, MVT::i32));
1177 // TODO: can we be smarter about machine pointer info?
1178 MachinePointerInfo PtrInfo(AMDGPUAS::PRIVATE_ADDRESS);
1179 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1181 Chain = Dst.getValue(1);
1183 // Get offset in dword
1184 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1185 DAG.getConstant(0x3, DL, MVT::i32));
1187 // Convert byte offset to bit shift
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1189 DAG.getConstant(3, DL, MVT::i32));
1191 // TODO: Contrary to the name of the functiom,
1192 // it also handles sub i32 non-truncating stores (like i1)
1193 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1196 // Mask the value to the right type
1197 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1199 // Shift the value in place
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1201 MaskedValue, ShiftAmt);
1203 // Shift the mask in place
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1206 // Invert the mask. NOTE: if we had native ROL instructions we could
1207 // use inverted mask
1208 DstMask = DAG.getNOT(DL, DstMask, MVT::i32);
1210 // Cleanup the target bits
1211 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1214 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1217 // TODO: Can we be smarter about MachinePointerInfo?
1218 SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo);
1220 // If we are part of expanded vector, make our neighbors depend on this store
1222 // Make all other vector elements depend on this store
1223 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore);
1224 DAG.ReplaceAllUsesOfValueWith(OldChain, Chain);
1229 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1230 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1231 unsigned AS = StoreNode->getAddressSpace();
1233 SDValue Chain = StoreNode->getChain();
1234 SDValue Ptr = StoreNode->getBasePtr();
1235 SDValue Value = StoreNode->getValue();
1237 EVT VT = Value.getValueType();
1238 EVT MemVT = StoreNode->getMemoryVT();
1239 EVT PtrVT = Ptr.getValueType();
1243 const bool TruncatingStore = StoreNode->isTruncatingStore();
1245 // Neither LOCAL nor PRIVATE can do vectors at the moment
1246 if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS ||
1249 if ((AS == AMDGPUAS::PRIVATE_ADDRESS) && TruncatingStore) {
1250 // Add an extra level of chain to isolate this vector
1251 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain);
1252 // TODO: can the chain be replaced without creating a new store?
1253 SDValue NewStore = DAG.getTruncStore(
1254 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(),
1255 MemVT, StoreNode->getAlignment(),
1256 StoreNode->getMemOperand()->getFlags(), StoreNode->getAAInfo());
1257 StoreNode = cast<StoreSDNode>(NewStore);
1260 return scalarizeVectorStore(StoreNode, DAG);
1263 unsigned Align = StoreNode->getAlignment();
1264 if (Align < MemVT.getStoreSize() &&
1265 !allowsMisalignedMemoryAccesses(
1266 MemVT, AS, Align, StoreNode->getMemOperand()->getFlags(), nullptr)) {
1267 return expandUnalignedStore(StoreNode, DAG);
1270 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr,
1271 DAG.getConstant(2, DL, PtrVT));
1273 if (AS == AMDGPUAS::GLOBAL_ADDRESS) {
1274 // It is beneficial to create MSKOR here instead of combiner to avoid
1275 // artificial dependencies introduced by RMW
1276 if (TruncatingStore) {
1277 assert(VT.bitsLE(MVT::i32));
1278 SDValue MaskConstant;
1279 if (MemVT == MVT::i8) {
1280 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1282 assert(MemVT == MVT::i16);
1283 assert(StoreNode->getAlignment() >= 2);
1284 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1287 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr,
1288 DAG.getConstant(0x00000003, DL, PtrVT));
1289 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1290 DAG.getConstant(3, DL, VT));
1292 // Put the mask in correct place
1293 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift);
1295 // Put the value bits in correct place
1296 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1297 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift);
1299 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1303 DAG.getConstant(0, DL, MVT::i32),
1304 DAG.getConstant(0, DL, MVT::i32),
1307 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src);
1308 SDValue Args[3] = { Chain, Input, DWordAddr };
1309 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1310 Op->getVTList(), Args, MemVT,
1311 StoreNode->getMemOperand());
1312 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) {
1313 // Convert pointer from byte address to dword address.
1314 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
1316 if (StoreNode->isIndexed()) {
1317 llvm_unreachable("Indexed stores not supported yet");
1319 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1325 // GLOBAL_ADDRESS has been handled above, LOCAL_ADDRESS allows all sizes
1326 if (AS != AMDGPUAS::PRIVATE_ADDRESS)
1329 if (MemVT.bitsLT(MVT::i32))
1330 return lowerPrivateTruncStore(StoreNode, DAG);
1332 // Standard i32+ store, tag it with DWORDADDR to note that the address
1334 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1335 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
1336 return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1339 // Tagged i32+ stores will be matched by patterns
1343 // return (512 + (kc_bank << 12)
1345 ConstantAddressBlock(unsigned AddressSpace) {
1346 switch (AddressSpace) {
1347 case AMDGPUAS::CONSTANT_BUFFER_0:
1349 case AMDGPUAS::CONSTANT_BUFFER_1:
1351 case AMDGPUAS::CONSTANT_BUFFER_2:
1352 return 512 + 4096 * 2;
1353 case AMDGPUAS::CONSTANT_BUFFER_3:
1354 return 512 + 4096 * 3;
1355 case AMDGPUAS::CONSTANT_BUFFER_4:
1356 return 512 + 4096 * 4;
1357 case AMDGPUAS::CONSTANT_BUFFER_5:
1358 return 512 + 4096 * 5;
1359 case AMDGPUAS::CONSTANT_BUFFER_6:
1360 return 512 + 4096 * 6;
1361 case AMDGPUAS::CONSTANT_BUFFER_7:
1362 return 512 + 4096 * 7;
1363 case AMDGPUAS::CONSTANT_BUFFER_8:
1364 return 512 + 4096 * 8;
1365 case AMDGPUAS::CONSTANT_BUFFER_9:
1366 return 512 + 4096 * 9;
1367 case AMDGPUAS::CONSTANT_BUFFER_10:
1368 return 512 + 4096 * 10;
1369 case AMDGPUAS::CONSTANT_BUFFER_11:
1370 return 512 + 4096 * 11;
1371 case AMDGPUAS::CONSTANT_BUFFER_12:
1372 return 512 + 4096 * 12;
1373 case AMDGPUAS::CONSTANT_BUFFER_13:
1374 return 512 + 4096 * 13;
1375 case AMDGPUAS::CONSTANT_BUFFER_14:
1376 return 512 + 4096 * 14;
1377 case AMDGPUAS::CONSTANT_BUFFER_15:
1378 return 512 + 4096 * 15;
1384 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1385 SelectionDAG &DAG) const {
1387 LoadSDNode *Load = cast<LoadSDNode>(Op);
1388 ISD::LoadExtType ExtType = Load->getExtensionType();
1389 EVT MemVT = Load->getMemoryVT();
1390 assert(Load->getAlignment() >= MemVT.getStoreSize());
1392 SDValue BasePtr = Load->getBasePtr();
1393 SDValue Chain = Load->getChain();
1394 SDValue Offset = Load->getOffset();
1396 SDValue LoadPtr = BasePtr;
1397 if (!Offset.isUndef()) {
1398 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1401 // Get dword location
1402 // NOTE: this should be eliminated by the future SHR ptr, 2
1403 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1404 DAG.getConstant(0xfffffffc, DL, MVT::i32));
1407 // TODO: can we be smarter about machine pointer info?
1408 MachinePointerInfo PtrInfo(AMDGPUAS::PRIVATE_ADDRESS);
1409 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1411 // Get offset within the register.
1412 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1413 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32));
1415 // Bit offset of target byte (byteIdx * 8).
1416 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1417 DAG.getConstant(3, DL, MVT::i32));
1419 // Shift to the right.
1420 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
1422 // Eliminate the upper bits by setting them to ...
1423 EVT MemEltVT = MemVT.getScalarType();
1425 if (ExtType == ISD::SEXTLOAD) { // ... ones.
1426 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1427 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1428 } else { // ... or zeros.
1429 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1434 Read.getValue(1) // This should be our output chain
1437 return DAG.getMergeValues(Ops, DL);
1440 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1441 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1442 unsigned AS = LoadNode->getAddressSpace();
1443 EVT MemVT = LoadNode->getMemoryVT();
1444 ISD::LoadExtType ExtType = LoadNode->getExtensionType();
1446 if (AS == AMDGPUAS::PRIVATE_ADDRESS &&
1447 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1448 return lowerPrivateExtLoad(Op, DAG);
1452 EVT VT = Op.getValueType();
1453 SDValue Chain = LoadNode->getChain();
1454 SDValue Ptr = LoadNode->getBasePtr();
1456 if ((LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1457 LoadNode->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1460 std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(LoadNode, DAG);
1461 return DAG.getMergeValues(Ops, DL);
1464 // This is still used for explicit load from addrspace(8)
1465 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1466 if (ConstantBlock > -1 &&
1467 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1468 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1470 if (isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1471 isa<ConstantSDNode>(Ptr)) {
1472 return constBufferLoad(LoadNode, LoadNode->getAddressSpace(), DAG);
1474 //TODO: Does this even work?
1475 // non-constant ptr can't be folded, keeps it as a v4f32 load
1476 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1477 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1478 DAG.getConstant(4, DL, MVT::i32)),
1479 DAG.getConstant(LoadNode->getAddressSpace() -
1480 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
1484 if (!VT.isVector()) {
1485 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1486 DAG.getConstant(0, DL, MVT::i32));
1489 SDValue MergedValues[2] = {
1493 return DAG.getMergeValues(MergedValues, DL);
1496 // For most operations returning SDValue() will result in the node being
1497 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1498 // need to manually expand loads that may be legal in some address spaces and
1499 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1500 // compute shaders, since the data is sign extended when it is uploaded to the
1501 // buffer. However SEXT loads from other address spaces are not supported, so
1502 // we need to expand them here.
1503 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1504 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1505 SDValue NewLoad = DAG.getExtLoad(
1506 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1507 LoadNode->getAlignment(), LoadNode->getMemOperand()->getFlags());
1508 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1509 DAG.getValueType(MemVT));
1511 SDValue MergedValues[2] = { Res, Chain };
1512 return DAG.getMergeValues(MergedValues, DL);
1515 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1519 // DWORDADDR ISD marks already shifted address
1520 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1521 assert(VT == MVT::i32);
1522 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32));
1523 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr);
1524 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand());
1529 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1530 SDValue Chain = Op.getOperand(0);
1531 SDValue Cond = Op.getOperand(1);
1532 SDValue Jump = Op.getOperand(2);
1534 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1538 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1539 SelectionDAG &DAG) const {
1540 MachineFunction &MF = DAG.getMachineFunction();
1541 const R600FrameLowering *TFL = Subtarget->getFrameLowering();
1543 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
1545 unsigned FrameIndex = FIN->getIndex();
1546 unsigned IgnoredFrameReg;
1548 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
1549 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
1553 CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1554 bool IsVarArg) const {
1556 case CallingConv::AMDGPU_KERNEL:
1557 case CallingConv::SPIR_KERNEL:
1558 case CallingConv::C:
1559 case CallingConv::Fast:
1560 case CallingConv::Cold:
1561 llvm_unreachable("kernels should not be handled here");
1562 case CallingConv::AMDGPU_VS:
1563 case CallingConv::AMDGPU_GS:
1564 case CallingConv::AMDGPU_PS:
1565 case CallingConv::AMDGPU_CS:
1566 case CallingConv::AMDGPU_HS:
1567 case CallingConv::AMDGPU_ES:
1568 case CallingConv::AMDGPU_LS:
1571 report_fatal_error("Unsupported calling convention.");
1575 /// XXX Only kernel functions are supported, so we can assume for now that
1576 /// every function is a kernel function, but in the future we should use
1577 /// separate calling conventions for kernel and non-kernel functions.
1578 SDValue R600TargetLowering::LowerFormalArguments(
1579 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1580 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1581 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1582 SmallVector<CCValAssign, 16> ArgLocs;
1583 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1585 MachineFunction &MF = DAG.getMachineFunction();
1586 SmallVector<ISD::InputArg, 8> LocalIns;
1588 if (AMDGPU::isShader(CallConv)) {
1589 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
1591 analyzeFormalArgumentsCompute(CCInfo, Ins);
1594 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1595 CCValAssign &VA = ArgLocs[i];
1596 const ISD::InputArg &In = Ins[i];
1598 EVT MemVT = VA.getLocVT();
1599 if (!VT.isVector() && MemVT.isVector()) {
1600 // Get load source type if scalarized.
1601 MemVT = MemVT.getVectorElementType();
1604 if (AMDGPU::isShader(CallConv)) {
1605 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &R600::R600_Reg128RegClass);
1606 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1607 InVals.push_back(Register);
1611 // i64 isn't a legal type, so the register type used ends up as i32, which
1612 // isn't expected here. It attempts to create this sextload, but it ends up
1613 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1616 // The first 36 bytes of the input buffer contains information about
1617 // thread group and global sizes.
1618 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1619 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1620 // FIXME: This should really check the extload type, but the handling of
1621 // extload vector parameters seems to be broken.
1623 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1624 Ext = ISD::SEXTLOAD;
1627 // Compute the offset from the value.
1628 // XXX - I think PartOffset should give you this, but it seems to give the
1629 // size of the register which isn't useful.
1631 unsigned PartOffset = VA.getLocMemOffset();
1632 unsigned Alignment = MinAlign(VT.getStoreSize(), PartOffset);
1634 MachinePointerInfo PtrInfo(AMDGPUAS::PARAM_I_ADDRESS);
1635 SDValue Arg = DAG.getLoad(
1636 ISD::UNINDEXED, Ext, VT, DL, Chain,
1637 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32),
1639 MemVT, Alignment, MachineMemOperand::MONonTemporal |
1640 MachineMemOperand::MODereferenceable |
1641 MachineMemOperand::MOInvariant);
1643 InVals.push_back(Arg);
1648 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1652 return VT.changeVectorElementTypeToInteger();
1655 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1656 const SelectionDAG &DAG) const {
1657 // Local and Private addresses do not handle vectors. Limit to i32
1658 if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS)) {
1659 return (MemVT.getSizeInBits() <= 32);
1664 bool R600TargetLowering::allowsMisalignedMemoryAccesses(
1665 EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
1666 bool *IsFast) const {
1670 if (!VT.isSimple() || VT == MVT::Other)
1673 if (VT.bitsLT(MVT::i32))
1676 // TODO: This is a rough estimate.
1680 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
1683 static SDValue CompactSwizzlableVector(
1684 SelectionDAG &DAG, SDValue VectorEntry,
1685 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1686 assert(RemapSwizzle.empty());
1688 SDLoc DL(VectorEntry);
1689 EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1691 SDValue NewBldVec[4];
1692 for (unsigned i = 0; i < 4; i++)
1693 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
1694 DAG.getIntPtrConstant(i, DL));
1696 for (unsigned i = 0; i < 4; i++) {
1697 if (NewBldVec[i].isUndef())
1698 // We mask write here to teach later passes that the ith element of this
1699 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1700 // break false dependencies and additionnaly make assembly easier to read.
1701 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1702 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1704 RemapSwizzle[i] = 4; // SEL_0
1705 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1706 } else if (C->isExactlyValue(1.0)) {
1707 RemapSwizzle[i] = 5; // SEL_1
1708 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1712 if (NewBldVec[i].isUndef())
1715 for (unsigned j = 0; j < i; j++) {
1716 if (NewBldVec[i] == NewBldVec[j]) {
1717 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1718 RemapSwizzle[i] = j;
1724 return DAG.getBuildVector(VectorEntry.getValueType(), SDLoc(VectorEntry),
1728 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1729 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1730 assert(RemapSwizzle.empty());
1732 SDLoc DL(VectorEntry);
1733 EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1735 SDValue NewBldVec[4];
1736 bool isUnmovable[4] = {false, false, false, false};
1737 for (unsigned i = 0; i < 4; i++)
1738 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
1739 DAG.getIntPtrConstant(i, DL));
1741 for (unsigned i = 0; i < 4; i++) {
1742 RemapSwizzle[i] = i;
1743 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1744 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1747 isUnmovable[Idx] = true;
1751 for (unsigned i = 0; i < 4; i++) {
1752 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1753 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1755 if (isUnmovable[Idx])
1758 std::swap(NewBldVec[Idx], NewBldVec[i]);
1759 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1764 return DAG.getBuildVector(VectorEntry.getValueType(), SDLoc(VectorEntry),
1768 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
1770 const SDLoc &DL) const {
1771 // Old -> New swizzle values
1772 DenseMap<unsigned, unsigned> SwizzleRemap;
1774 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1775 for (unsigned i = 0; i < 4; i++) {
1776 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1777 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1778 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1781 SwizzleRemap.clear();
1782 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1783 for (unsigned i = 0; i < 4; i++) {
1784 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1785 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1786 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1792 SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block,
1793 SelectionDAG &DAG) const {
1795 EVT VT = LoadNode->getValueType(0);
1796 SDValue Chain = LoadNode->getChain();
1797 SDValue Ptr = LoadNode->getBasePtr();
1798 assert (isa<ConstantSDNode>(Ptr));
1800 //TODO: Support smaller loads
1801 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode))
1804 if (LoadNode->getAlignment() < 4)
1807 int ConstantBlock = ConstantAddressBlock(Block);
1810 for (unsigned i = 0; i < 4; i++) {
1811 // We want Const position encoded with the following formula :
1812 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1813 // const_index is Ptr computed by llvm using an alignment of 16.
1814 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1815 // then div by 4 at the ISel step
1816 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1817 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1818 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1820 EVT NewVT = MVT::v4i32;
1821 unsigned NumElements = 4;
1822 if (VT.isVector()) {
1824 NumElements = VT.getVectorNumElements();
1826 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements));
1827 if (!VT.isVector()) {
1828 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1829 DAG.getConstant(0, DL, MVT::i32));
1831 SDValue MergedValues[2] = {
1835 return DAG.getMergeValues(MergedValues, DL);
1838 //===----------------------------------------------------------------------===//
1839 // Custom DAG Optimizations
1840 //===----------------------------------------------------------------------===//
1842 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1843 DAGCombinerInfo &DCI) const {
1844 SelectionDAG &DAG = DCI.DAG;
1847 switch (N->getOpcode()) {
1848 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1849 case ISD::FP_ROUND: {
1850 SDValue Arg = N->getOperand(0);
1851 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1852 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0),
1858 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1859 // (i32 select_cc f32, f32, -1, 0 cc)
1861 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1862 // this to one of the SET*_DX10 instructions.
1863 case ISD::FP_TO_SINT: {
1864 SDValue FNeg = N->getOperand(0);
1865 if (FNeg.getOpcode() != ISD::FNEG) {
1868 SDValue SelectCC = FNeg.getOperand(0);
1869 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1870 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1871 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1872 !isHWTrueValue(SelectCC.getOperand(2)) ||
1873 !isHWFalseValue(SelectCC.getOperand(3))) {
1877 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
1878 SelectCC.getOperand(0), // LHS
1879 SelectCC.getOperand(1), // RHS
1880 DAG.getConstant(-1, DL, MVT::i32), // True
1881 DAG.getConstant(0, DL, MVT::i32), // False
1882 SelectCC.getOperand(4)); // CC
1885 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1886 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1887 case ISD::INSERT_VECTOR_ELT: {
1888 SDValue InVec = N->getOperand(0);
1889 SDValue InVal = N->getOperand(1);
1890 SDValue EltNo = N->getOperand(2);
1892 // If the inserted element is an UNDEF, just use the input vector.
1893 if (InVal.isUndef())
1896 EVT VT = InVec.getValueType();
1898 // If we can't generate a legal BUILD_VECTOR, exit
1899 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1902 // Check that we know which element is being inserted
1903 if (!isa<ConstantSDNode>(EltNo))
1905 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1907 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1908 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1910 SmallVector<SDValue, 8> Ops;
1911 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1912 Ops.append(InVec.getNode()->op_begin(),
1913 InVec.getNode()->op_end());
1914 } else if (InVec.isUndef()) {
1915 unsigned NElts = VT.getVectorNumElements();
1916 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1921 // Insert the element
1922 if (Elt < Ops.size()) {
1923 // All the operands of BUILD_VECTOR must have the same type;
1924 // we enforce that here.
1925 EVT OpVT = Ops[0].getValueType();
1926 if (InVal.getValueType() != OpVT)
1927 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1928 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) :
1929 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal);
1933 // Return the new vector
1934 return DAG.getBuildVector(VT, DL, Ops);
1937 // Extract_vec (Build_vector) generated by custom lowering
1938 // also needs to be customly combined
1939 case ISD::EXTRACT_VECTOR_ELT: {
1940 SDValue Arg = N->getOperand(0);
1941 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1942 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1943 unsigned Element = Const->getZExtValue();
1944 return Arg->getOperand(Element);
1947 if (Arg.getOpcode() == ISD::BITCAST &&
1948 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
1949 (Arg.getOperand(0).getValueType().getVectorNumElements() ==
1950 Arg.getValueType().getVectorNumElements())) {
1951 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1952 unsigned Element = Const->getZExtValue();
1953 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
1954 Arg->getOperand(0).getOperand(Element));
1960 case ISD::SELECT_CC: {
1961 // Try common optimizations
1962 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI))
1965 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1966 // selectcc x, y, a, b, inv(cc)
1968 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1969 // selectcc x, y, a, b, cc
1970 SDValue LHS = N->getOperand(0);
1971 if (LHS.getOpcode() != ISD::SELECT_CC) {
1975 SDValue RHS = N->getOperand(1);
1976 SDValue True = N->getOperand(2);
1977 SDValue False = N->getOperand(3);
1978 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1980 if (LHS.getOperand(2).getNode() != True.getNode() ||
1981 LHS.getOperand(3).getNode() != False.getNode() ||
1982 RHS.getNode() != False.getNode()) {
1987 default: return SDValue();
1988 case ISD::SETNE: return LHS;
1990 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1991 LHSCC = ISD::getSetCCInverse(LHSCC, LHS.getOperand(0).getValueType());
1992 if (DCI.isBeforeLegalizeOps() ||
1993 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1994 return DAG.getSelectCC(DL,
2006 case AMDGPUISD::R600_EXPORT: {
2007 SDValue Arg = N->getOperand(1);
2008 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2011 SDValue NewArgs[8] = {
2012 N->getOperand(0), // Chain
2014 N->getOperand(2), // ArrayBase
2015 N->getOperand(3), // Type
2016 N->getOperand(4), // SWZ_X
2017 N->getOperand(5), // SWZ_Y
2018 N->getOperand(6), // SWZ_Z
2019 N->getOperand(7) // SWZ_W
2021 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
2022 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs);
2024 case AMDGPUISD::TEXTURE_FETCH: {
2025 SDValue Arg = N->getOperand(1);
2026 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2029 SDValue NewArgs[19] = {
2050 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
2051 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);
2055 LoadSDNode *LoadNode = cast<LoadSDNode>(N);
2056 SDValue Ptr = LoadNode->getBasePtr();
2057 if (LoadNode->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS &&
2058 isa<ConstantSDNode>(Ptr))
2059 return constBufferLoad(LoadNode, AMDGPUAS::CONSTANT_BUFFER_0, DAG);
2066 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2069 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
2070 SDValue &Src, SDValue &Neg, SDValue &Abs,
2071 SDValue &Sel, SDValue &Imm,
2072 SelectionDAG &DAG) const {
2073 const R600InstrInfo *TII = Subtarget->getInstrInfo();
2074 if (!Src.isMachineOpcode())
2077 switch (Src.getMachineOpcode()) {
2078 case R600::FNEG_R600:
2081 Src = Src.getOperand(0);
2082 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2084 case R600::FABS_R600:
2087 Src = Src.getOperand(0);
2088 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2090 case R600::CONST_COPY: {
2091 unsigned Opcode = ParentNode->getMachineOpcode();
2092 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2097 SDValue CstOffset = Src.getOperand(0);
2098 if (ParentNode->getValueType(0).isVector())
2101 // Gather constants values
2102 int SrcIndices[] = {
2103 TII->getOperandIdx(Opcode, R600::OpName::src0),
2104 TII->getOperandIdx(Opcode, R600::OpName::src1),
2105 TII->getOperandIdx(Opcode, R600::OpName::src2),
2106 TII->getOperandIdx(Opcode, R600::OpName::src0_X),
2107 TII->getOperandIdx(Opcode, R600::OpName::src0_Y),
2108 TII->getOperandIdx(Opcode, R600::OpName::src0_Z),
2109 TII->getOperandIdx(Opcode, R600::OpName::src0_W),
2110 TII->getOperandIdx(Opcode, R600::OpName::src1_X),
2111 TII->getOperandIdx(Opcode, R600::OpName::src1_Y),
2112 TII->getOperandIdx(Opcode, R600::OpName::src1_Z),
2113 TII->getOperandIdx(Opcode, R600::OpName::src1_W)
2115 std::vector<unsigned> Consts;
2116 for (int OtherSrcIdx : SrcIndices) {
2117 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2118 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2124 if (RegisterSDNode *Reg =
2125 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2126 if (Reg->getReg() == R600::ALU_CONST) {
2128 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2129 Consts.push_back(Cst->getZExtValue());
2134 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2135 Consts.push_back(Cst->getZExtValue());
2136 if (!TII->fitsConstReadLimitations(Consts)) {
2141 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32);
2144 case R600::MOV_IMM_GLOBAL_ADDR:
2145 // Check if the Imm slot is used. Taken from below.
2146 if (cast<ConstantSDNode>(Imm)->getZExtValue())
2148 Imm = Src.getOperand(0);
2149 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32);
2151 case R600::MOV_IMM_I32:
2152 case R600::MOV_IMM_F32: {
2153 unsigned ImmReg = R600::ALU_LITERAL_X;
2154 uint64_t ImmValue = 0;
2156 if (Src.getMachineOpcode() == R600::MOV_IMM_F32) {
2157 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2158 float FloatValue = FPC->getValueAPF().convertToFloat();
2159 if (FloatValue == 0.0) {
2160 ImmReg = R600::ZERO;
2161 } else if (FloatValue == 0.5) {
2162 ImmReg = R600::HALF;
2163 } else if (FloatValue == 1.0) {
2166 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2169 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2170 uint64_t Value = C->getZExtValue();
2172 ImmReg = R600::ZERO;
2173 } else if (Value == 1) {
2174 ImmReg = R600::ONE_INT;
2180 // Check that we aren't already using an immediate.
2181 // XXX: It's possible for an instruction to have more than one
2182 // immediate operand, but this is not supported yet.
2183 if (ImmReg == R600::ALU_LITERAL_X) {
2186 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2188 if (C->getZExtValue())
2190 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32);
2192 Src = DAG.getRegister(ImmReg, MVT::i32);
2200 /// Fold the instructions after selecting them
2201 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2202 SelectionDAG &DAG) const {
2203 const R600InstrInfo *TII = Subtarget->getInstrInfo();
2204 if (!Node->isMachineOpcode())
2207 unsigned Opcode = Node->getMachineOpcode();
2210 std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2212 if (Opcode == R600::DOT_4) {
2213 int OperandIdx[] = {
2214 TII->getOperandIdx(Opcode, R600::OpName::src0_X),
2215 TII->getOperandIdx(Opcode, R600::OpName::src0_Y),
2216 TII->getOperandIdx(Opcode, R600::OpName::src0_Z),
2217 TII->getOperandIdx(Opcode, R600::OpName::src0_W),
2218 TII->getOperandIdx(Opcode, R600::OpName::src1_X),
2219 TII->getOperandIdx(Opcode, R600::OpName::src1_Y),
2220 TII->getOperandIdx(Opcode, R600::OpName::src1_Z),
2221 TII->getOperandIdx(Opcode, R600::OpName::src1_W)
2224 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_X),
2225 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Y),
2226 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Z),
2227 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_W),
2228 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_X),
2229 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Y),
2230 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Z),
2231 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_W)
2234 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_X),
2235 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Y),
2236 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Z),
2237 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_W),
2238 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_X),
2239 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Y),
2240 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Z),
2241 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_W)
2243 for (unsigned i = 0; i < 8; i++) {
2244 if (OperandIdx[i] < 0)
2246 SDValue &Src = Ops[OperandIdx[i] - 1];
2247 SDValue &Neg = Ops[NegIdx[i] - 1];
2248 SDValue &Abs = Ops[AbsIdx[i] - 1];
2249 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2250 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2253 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2254 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2255 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2257 } else if (Opcode == R600::REG_SEQUENCE) {
2258 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2259 SDValue &Src = Ops[i];
2260 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2261 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2264 if (!TII->hasInstrModifiers(Opcode))
2266 int OperandIdx[] = {
2267 TII->getOperandIdx(Opcode, R600::OpName::src0),
2268 TII->getOperandIdx(Opcode, R600::OpName::src1),
2269 TII->getOperandIdx(Opcode, R600::OpName::src2)
2272 TII->getOperandIdx(Opcode, R600::OpName::src0_neg),
2273 TII->getOperandIdx(Opcode, R600::OpName::src1_neg),
2274 TII->getOperandIdx(Opcode, R600::OpName::src2_neg)
2277 TII->getOperandIdx(Opcode, R600::OpName::src0_abs),
2278 TII->getOperandIdx(Opcode, R600::OpName::src1_abs),
2281 for (unsigned i = 0; i < 3; i++) {
2282 if (OperandIdx[i] < 0)
2284 SDValue &Src = Ops[OperandIdx[i] - 1];
2285 SDValue &Neg = Ops[NegIdx[i] - 1];
2287 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2288 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2289 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2290 int ImmIdx = TII->getOperandIdx(Opcode, R600::OpName::literal);
2295 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2296 SDValue &Imm = Ops[ImmIdx];
2297 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2298 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);