contrib/llvm-project/llvm/lib/Target/AMDGPU/R600RegisterInfo.td

   1
   2 class R600Reg <string name, bits<16> encoding> : Register<name> {
   3   let Namespace = "AMDGPU";
   4   let HWEncoding = encoding;
   5 }
   6
   7 class R600RegWithChan <string name, bits<9> sel, string chan> :
   8     Register <name> {
   9
  10   field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
  11                                 !if(!eq(chan, "Y"), 1,
  12                                 !if(!eq(chan, "Z"), 2,
  13                                 !if(!eq(chan, "W"), 3, 0))));
  14   let HWEncoding{8-0}  = sel;
  15   let HWEncoding{10-9} = chan_encoding;
  16   let Namespace = "AMDGPU";
  17 }
  18
  19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
  20     RegisterWithSubRegs<n, subregs> {
  21   field bits<2> chan_encoding = 0;
  22   let Namespace = "AMDGPU";
  23   let SubRegIndices = [sub0, sub1, sub2, sub3];
  24   let HWEncoding{8-0} = encoding{8-0};
  25   let HWEncoding{10-9} = chan_encoding;
  26 }
  27
  28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
  29     RegisterWithSubRegs<n, subregs> {
  30   field bits<2> chan_encoding = 0;
  31   let Namespace = "AMDGPU";
  32   let SubRegIndices = [sub0, sub1];
  33   let HWEncoding = encoding;
  34   let HWEncoding{8-0} = encoding{8-0};
  35   let HWEncoding{10-9} = chan_encoding;
  36 }
  37
  38 class R600Reg_64Vertical<int lo, int hi, string chan> : R600Reg_64 <
  39   "V"#lo#hi#"_"#chan,
  40   [!cast<Register>("T"#lo#"_"#chan), !cast<Register>("T"#hi#"_"#chan)],
  41   lo
  42 >;
  43
  44 foreach Index = 0-127 in {
  45   foreach Chan = [ "X", "Y", "Z", "W" ] in {
  46     // 32-bit Temporary Registers
  47     def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
  48
  49     // Indirect addressing offset registers
  50     def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
  51                                               Index, Chan>;
  52   }
  53   // 128-bit Temporary Registers
  54   def T#Index#_XYZW : R600Reg_128 <"T"#Index#"",
  55                                    [!cast<Register>("T"#Index#"_X"),
  56                                     !cast<Register>("T"#Index#"_Y"),
  57                                     !cast<Register>("T"#Index#"_Z"),
  58                                     !cast<Register>("T"#Index#"_W")],
  59                                    Index>;
  60
  61   def T#Index#_XY : R600Reg_64 <"T"#Index#"",
  62                                    [!cast<Register>("T"#Index#"_X"),
  63                                     !cast<Register>("T"#Index#"_Y")],
  64                                    Index>;
  65 }
  66
  67 foreach Chan = [ "X", "Y", "Z", "W"] in {
  68
  69   let chan_encoding = !if(!eq(Chan, "X"), 0,
  70                       !if(!eq(Chan, "Y"), 1,
  71                       !if(!eq(Chan, "Z"), 2,
  72                       !if(!eq(Chan, "W"), 3, 0)))) in {
  73     def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,
  74                                    [!cast<Register>("T0_"#Chan),
  75                                     !cast<Register>("T1_"#Chan),
  76                                     !cast<Register>("T2_"#Chan),
  77                                     !cast<Register>("T3_"#Chan)],
  78                                     0>;
  79     def V01_#Chan : R600Reg_64Vertical<0, 1, Chan>;
  80     def V23_#Chan : R600Reg_64Vertical<2, 3, Chan>;
  81   }
  82 }
  83
  84
  85 // KCACHE_BANK0
  86 foreach Index = 159-128 in {
  87   foreach Chan = [ "X", "Y", "Z", "W" ] in {
  88     // 32-bit Temporary Registers
  89     def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#!add(Index,-128)#"]."#Chan, Index, Chan>;
  90   }
  91   // 128-bit Temporary Registers
  92   def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#!add(Index, -128)#"].XYZW",
  93                                  [!cast<Register>("KC0_"#Index#"_X"),
  94                                   !cast<Register>("KC0_"#Index#"_Y"),
  95                                   !cast<Register>("KC0_"#Index#"_Z"),
  96                                   !cast<Register>("KC0_"#Index#"_W")],
  97                                  Index>;
  98 }
  99
 100 // KCACHE_BANK1
 101 foreach Index = 191-160 in {
 102   foreach Chan = [ "X", "Y", "Z", "W" ] in {
 103     // 32-bit Temporary Registers
 104     def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#!add(Index,-160)#"]."#Chan, Index, Chan>;
 105   }
 106   // 128-bit Temporary Registers
 107   def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#!add(Index, -160)#"].XYZW",
 108                                  [!cast<Register>("KC1_"#Index#"_X"),
 109                                   !cast<Register>("KC1_"#Index#"_Y"),
 110                                   !cast<Register>("KC1_"#Index#"_Z"),
 111                                   !cast<Register>("KC1_"#Index#"_W")],
 112                                  Index>;
 113 }
 114
 115
 116 // Array Base Register holding input in FS
 117 foreach Index = 448-480 in {
 118   def ArrayBase#Index :  R600Reg<"ARRAY_BASE", Index>;
 119 }
 120
 121
 122 // Special Registers
 123
 124 def OQA : R600Reg<"OQA", 219>;
 125 def OQB : R600Reg<"OQB", 220>;
 126 def OQAP : R600Reg<"OQAP", 221>;
 127 def OQBP : R600Reg<"OQAP", 222>;
 128 def LDS_DIRECT_A : R600Reg<"LDS_DIRECT_A", 223>;
 129 def LDS_DIRECT_B : R600Reg<"LDS_DIRECT_B", 224>;
 130 def ZERO : R600Reg<"0.0", 248>;
 131 def ONE : R600Reg<"1.0", 249>;
 132 def NEG_ONE : R600Reg<"-1.0", 249>;
 133 def ONE_INT : R600Reg<"1", 250>;
 134 def HALF : R600Reg<"0.5", 252>;
 135 def NEG_HALF : R600Reg<"-0.5", 252>;
 136 def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;
 137 def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;
 138 def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;
 139 def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;
 140 def PV_X : R600RegWithChan<"PV.X", 254, "X">;
 141 def PV_Y : R600RegWithChan<"PV.Y", 254, "Y">;
 142 def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;
 143 def PV_W : R600RegWithChan<"PV.W", 254, "W">;
 144 def PS: R600Reg<"PS", 255>;
 145 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
 146 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
 147 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
 148 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 149 def AR_X : R600Reg<"AR.x", 0>;
 150 def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;
 151
 152 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
 153                           (add (sequence "ArrayBase%u", 448, 480))>;
 154 // special registers for ALU src operands
 155 // const buffer reference, SRCx_SEL contains index
 156 def ALU_CONST : R600Reg<"CBuf", 0>;
 157 // interpolation param reference, SRCx_SEL contains index
 158 def ALU_PARAM : R600Reg<"Param", 0>;
 159
 160 let isAllocatable = 0 in {
 161
 162 def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
 163
 164 // We only use Addr_[YZW] for vertical vectors.
 165 // FIXME if we add more vertical vector registers we will need to ad more
 166 // registers to these classes.
 167 def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;
 168 def R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>;
 169 def R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>;
 170
 171 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
 172   (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>;
 173
 174 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
 175                               (add (sequence "KC0_%u_X", 128, 159))>;
 176
 177 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
 178                               (add (sequence "KC0_%u_Y", 128, 159))>;
 179
 180 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
 181                               (add (sequence "KC0_%u_Z", 128, 159))>;
 182
 183 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
 184                               (add (sequence "KC0_%u_W", 128, 159))>;
 185
 186 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
 187                                    (interleave R600_KC0_X, R600_KC0_Y,
 188                                                R600_KC0_Z, R600_KC0_W)>;
 189
 190 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
 191                               (add (sequence "KC1_%u_X", 160, 191))>;
 192
 193 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
 194                               (add (sequence "KC1_%u_Y", 160, 191))>;
 195
 196 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
 197                               (add (sequence "KC1_%u_Z", 160, 191))>;
 198
 199 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
 200                               (add (sequence "KC1_%u_W", 160, 191))>;
 201
 202 def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
 203                                    (interleave R600_KC1_X, R600_KC1_Y,
 204                                                R600_KC1_Z, R600_KC1_W)>;
 205
 206 } // End isAllocatable = 0
 207
 208 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
 209                                    (add (sequence "T%u_X", 0, 127), AR_X)>;
 210
 211 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
 212                                    (add (sequence "T%u_Y", 0, 127))>;
 213
 214 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
 215                                    (add (sequence "T%u_Z", 0, 127))>;
 216
 217 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
 218                                    (add (sequence "T%u_W", 0, 127))>;
 219
 220 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
 221                                    (interleave R600_TReg32_X, R600_TReg32_Y,
 222                                                R600_TReg32_Z, R600_TReg32_W)>;
 223
 224 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
 225     R600_TReg32,
 226     R600_ArrayBase,
 227     R600_Addr,
 228     R600_KC0, R600_KC1,
 229     ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
 230     ALU_CONST, ALU_PARAM, OQAP, INDIRECT_BASE_ADDR
 231     )>;
 232
 233 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
 234     PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
 235
 236 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
 237     PREDICATE_BIT)>;
 238
 239 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
 240                                 (add (sequence "T%u_XYZW", 0, 127))> {
 241   let CopyCost = -1;
 242 }
 243
 244 def R600_Reg128Vertical : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
 245   (add V0123_W, V0123_Z, V0123_Y, V0123_X)
 246 >;
 247
 248 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,
 249                                 (add (sequence "T%u_XY", 0, 63))>;
 250
 251 def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
 252                                       (add V01_X, V01_Y, V01_Z, V01_W,
 253                                            V23_X, V23_Y, V23_Z, V23_W)>;