1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Add implicit use of exec to vector register copies.
12 //===----------------------------------------------------------------------===//
15 #include "AMDGPUSubtarget.h"
16 #include "SIInstrInfo.h"
17 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #define DEBUG_TYPE "si-fix-vgpr-copies"
26 class SIFixVGPRCopies : public MachineFunctionPass {
31 SIFixVGPRCopies() : MachineFunctionPass(ID) {
32 initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
35 bool runOnMachineFunction(MachineFunction &MF) override;
37 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
40 } // End anonymous namespace.
42 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
44 char SIFixVGPRCopies::ID = 0;
46 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
48 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
49 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
50 const SIRegisterInfo *TRI = ST.getRegisterInfo();
51 const SIInstrInfo *TII = ST.getInstrInfo();
54 for (MachineBasicBlock &MBB : MF) {
55 for (MachineInstr &MI : MBB) {
56 switch (MI.getOpcode()) {
58 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
61 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);