1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Custom DAG lowering for SI
12 //===----------------------------------------------------------------------===//
14 #if defined(_MSC_VER) || defined(__MINGW32__)
16 #define _USE_MATH_DEFINES
19 #include "SIISelLowering.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "SIDefines.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "Utils/AMDGPUBaseInfo.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/APInt.h"
31 #include "llvm/ADT/ArrayRef.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringRef.h"
36 #include "llvm/ADT/StringSwitch.h"
37 #include "llvm/ADT/Twine.h"
38 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
39 #include "llvm/CodeGen/Analysis.h"
40 #include "llvm/CodeGen/CallingConvLower.h"
41 #include "llvm/CodeGen/DAGCombine.h"
42 #include "llvm/CodeGen/ISDOpcodes.h"
43 #include "llvm/CodeGen/MachineBasicBlock.h"
44 #include "llvm/CodeGen/MachineFrameInfo.h"
45 #include "llvm/CodeGen/MachineFunction.h"
46 #include "llvm/CodeGen/MachineInstr.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineLoopInfo.h"
49 #include "llvm/CodeGen/MachineMemOperand.h"
50 #include "llvm/CodeGen/MachineModuleInfo.h"
51 #include "llvm/CodeGen/MachineOperand.h"
52 #include "llvm/CodeGen/MachineRegisterInfo.h"
53 #include "llvm/CodeGen/SelectionDAG.h"
54 #include "llvm/CodeGen/SelectionDAGNodes.h"
55 #include "llvm/CodeGen/TargetCallingConv.h"
56 #include "llvm/CodeGen/TargetRegisterInfo.h"
57 #include "llvm/CodeGen/ValueTypes.h"
58 #include "llvm/IR/Constants.h"
59 #include "llvm/IR/DataLayout.h"
60 #include "llvm/IR/DebugLoc.h"
61 #include "llvm/IR/DerivedTypes.h"
62 #include "llvm/IR/DiagnosticInfo.h"
63 #include "llvm/IR/Function.h"
64 #include "llvm/IR/GlobalValue.h"
65 #include "llvm/IR/InstrTypes.h"
66 #include "llvm/IR/Instruction.h"
67 #include "llvm/IR/Instructions.h"
68 #include "llvm/IR/IntrinsicInst.h"
69 #include "llvm/IR/Type.h"
70 #include "llvm/Support/Casting.h"
71 #include "llvm/Support/CodeGen.h"
72 #include "llvm/Support/CommandLine.h"
73 #include "llvm/Support/Compiler.h"
74 #include "llvm/Support/ErrorHandling.h"
75 #include "llvm/Support/KnownBits.h"
76 #include "llvm/Support/MachineValueType.h"
77 #include "llvm/Support/MathExtras.h"
78 #include "llvm/Target/TargetOptions.h"
89 #define DEBUG_TYPE "si-lower"
91 STATISTIC(NumTailCalls, "Number of tail calls");
93 static cl::opt<bool> DisableLoopAlignment(
94 "amdgpu-disable-loop-alignment",
95 cl::desc("Do not align and prefetch loops"),
98 static bool hasFP32Denormals(const MachineFunction &MF) {
99 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
100 return Info->getMode().FP32Denormals;
103 static bool hasFP64FP16Denormals(const MachineFunction &MF) {
104 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
105 return Info->getMode().FP64FP16Denormals;
108 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
109 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
110 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
111 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
112 return AMDGPU::SGPR0 + Reg;
115 llvm_unreachable("Cannot allocate sgpr");
118 SITargetLowering::SITargetLowering(const TargetMachine &TM,
119 const GCNSubtarget &STI)
120 : AMDGPUTargetLowering(TM, STI),
122 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
123 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
125 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
126 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
128 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
129 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
130 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
132 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
133 addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
135 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
136 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
138 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
139 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
141 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
142 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
144 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
145 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
147 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
148 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
150 if (Subtarget->has16BitInsts()) {
151 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
152 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
154 // Unless there are also VOP3P operations, not operations are really legal.
155 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
156 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
157 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
158 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
161 if (Subtarget->hasMAIInsts()) {
162 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
163 addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
166 computeRegisterProperties(Subtarget->getRegisterInfo());
168 // The boolean content concept here is too inflexible. Compares only ever
169 // really produce a 1-bit result. Any copy/extend from these will turn into a
170 // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as
171 // it's what most targets use.
172 setBooleanContents(ZeroOrOneBooleanContent);
173 setBooleanVectorContents(ZeroOrOneBooleanContent);
175 // We need to custom lower vector stores from local memory
176 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
177 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
178 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
179 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
180 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
181 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
182 setOperationAction(ISD::LOAD, MVT::i1, Custom);
183 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
185 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
186 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
187 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
188 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
189 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
190 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
191 setOperationAction(ISD::STORE, MVT::i1, Custom);
192 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
194 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
195 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
196 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
197 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
198 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
199 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
200 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
201 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
202 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
203 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
204 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
206 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
207 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
209 setOperationAction(ISD::SELECT, MVT::i1, Promote);
210 setOperationAction(ISD::SELECT, MVT::i64, Custom);
211 setOperationAction(ISD::SELECT, MVT::f64, Promote);
212 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
214 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
215 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
216 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
217 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
218 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
220 setOperationAction(ISD::SETCC, MVT::i1, Promote);
221 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
222 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
225 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
226 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
237 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
238 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
239 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
240 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
241 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
242 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
244 setOperationAction(ISD::UADDO, MVT::i32, Legal);
245 setOperationAction(ISD::USUBO, MVT::i32, Legal);
247 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
248 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
250 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
251 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
252 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
255 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
256 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
259 // We only support LOAD/STORE and vector manipulation ops for vectors
260 // with > 4 elements.
261 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
262 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
263 MVT::v32i32, MVT::v32f32 }) {
264 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
268 case ISD::BUILD_VECTOR:
270 case ISD::EXTRACT_VECTOR_ELT:
271 case ISD::INSERT_VECTOR_ELT:
272 case ISD::INSERT_SUBVECTOR:
273 case ISD::EXTRACT_SUBVECTOR:
274 case ISD::SCALAR_TO_VECTOR:
276 case ISD::CONCAT_VECTORS:
277 setOperationAction(Op, VT, Custom);
280 setOperationAction(Op, VT, Expand);
286 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
288 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
289 // is expanded to avoid having two separate loops in case the index is a VGPR.
291 // Most operations are naturally 32-bit vector operations. We only support
292 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
293 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
294 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
295 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
297 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
298 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
300 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
303 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
304 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
307 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
308 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
309 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
315 // Avoid stack access for these.
316 // TODO: Generalize to more vector types.
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
320 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
322 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
326 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
328 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
329 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
330 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
334 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
335 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
337 // Deal with vec3 vector operations when widened to vec4.
338 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
339 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
340 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
341 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
343 // Deal with vec5 vector operations when widened to vec8.
344 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
345 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
346 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
347 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
349 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
350 // and output demarshalling
351 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
352 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
354 // We can't return success/failure, only the old value,
355 // let LLVM add the comparison
356 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
359 if (Subtarget->hasFlatAddressSpace()) {
360 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
361 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
364 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
365 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
367 // On SI this is s_memtime and s_memrealtime on VI.
368 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
369 setOperationAction(ISD::TRAP, MVT::Other, Custom);
370 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
372 if (Subtarget->has16BitInsts()) {
373 setOperationAction(ISD::FPOW, MVT::f16, Promote);
374 setOperationAction(ISD::FLOG, MVT::f16, Custom);
375 setOperationAction(ISD::FEXP, MVT::f16, Custom);
376 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
379 // v_mad_f32 does not support denormals. We report it as unconditionally
380 // legal, and the context where it is formed will disallow it when fp32
381 // denormals are enabled.
382 setOperationAction(ISD::FMAD, MVT::f32, Legal);
384 if (!Subtarget->hasBFI()) {
385 // fcopysign can be done in a single instruction with BFI.
386 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
387 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
390 if (!Subtarget->hasBCNT(32))
391 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
393 if (!Subtarget->hasBCNT(64))
394 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
396 if (Subtarget->hasFFBH())
397 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
399 if (Subtarget->hasFFBL())
400 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
402 // We only really have 32-bit BFE instructions (and 16-bit on VI).
404 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
405 // effort to match them now. We want this to be false for i64 cases when the
406 // extraction isn't restricted to the upper or lower half. Ideally we would
407 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
408 // span the midpoint are probably relatively rare, so don't worry about them
410 if (Subtarget->hasBFE())
411 setHasExtractBitsInsn(true);
413 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
414 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
415 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
416 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
419 // These are really only legal for ieee_mode functions. We should be avoiding
420 // them for functions that don't have ieee_mode enabled, so just say they are
422 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
423 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
424 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
425 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
428 if (Subtarget->haveRoundOpsF64()) {
429 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
430 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
431 setOperationAction(ISD::FRINT, MVT::f64, Legal);
433 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
434 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
435 setOperationAction(ISD::FRINT, MVT::f64, Custom);
436 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
439 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
441 setOperationAction(ISD::FSIN, MVT::f32, Custom);
442 setOperationAction(ISD::FCOS, MVT::f32, Custom);
443 setOperationAction(ISD::FDIV, MVT::f32, Custom);
444 setOperationAction(ISD::FDIV, MVT::f64, Custom);
446 if (Subtarget->has16BitInsts()) {
447 setOperationAction(ISD::Constant, MVT::i16, Legal);
449 setOperationAction(ISD::SMIN, MVT::i16, Legal);
450 setOperationAction(ISD::SMAX, MVT::i16, Legal);
452 setOperationAction(ISD::UMIN, MVT::i16, Legal);
453 setOperationAction(ISD::UMAX, MVT::i16, Legal);
455 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
456 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
458 setOperationAction(ISD::ROTR, MVT::i16, Promote);
459 setOperationAction(ISD::ROTL, MVT::i16, Promote);
461 setOperationAction(ISD::SDIV, MVT::i16, Promote);
462 setOperationAction(ISD::UDIV, MVT::i16, Promote);
463 setOperationAction(ISD::SREM, MVT::i16, Promote);
464 setOperationAction(ISD::UREM, MVT::i16, Promote);
466 setOperationAction(ISD::BSWAP, MVT::i16, Promote);
467 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
469 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
470 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
471 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
473 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
475 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
477 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
479 setOperationAction(ISD::LOAD, MVT::i16, Custom);
481 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
483 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
484 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
485 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
486 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
488 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
489 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
491 // F16 - Constant Actions.
492 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
494 // F16 - Load/Store Actions.
495 setOperationAction(ISD::LOAD, MVT::f16, Promote);
496 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
497 setOperationAction(ISD::STORE, MVT::f16, Promote);
498 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
500 // F16 - VOP1 Actions.
501 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
502 setOperationAction(ISD::FCOS, MVT::f16, Promote);
503 setOperationAction(ISD::FSIN, MVT::f16, Promote);
505 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
506 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
508 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
509 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
510 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
511 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
512 setOperationAction(ISD::FROUND, MVT::f16, Custom);
514 // F16 - VOP2 Actions.
515 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
516 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
518 setOperationAction(ISD::FDIV, MVT::f16, Custom);
520 // F16 - VOP3 Actions.
521 setOperationAction(ISD::FMA, MVT::f16, Legal);
523 setOperationAction(ISD::FMAD, MVT::f16, Legal);
525 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
526 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
530 case ISD::BUILD_VECTOR:
532 case ISD::EXTRACT_VECTOR_ELT:
533 case ISD::INSERT_VECTOR_ELT:
534 case ISD::INSERT_SUBVECTOR:
535 case ISD::EXTRACT_SUBVECTOR:
536 case ISD::SCALAR_TO_VECTOR:
538 case ISD::CONCAT_VECTORS:
539 setOperationAction(Op, VT, Custom);
542 setOperationAction(Op, VT, Expand);
548 // XXX - Do these do anything? Vector constants turn into build_vector.
549 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
550 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
552 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
553 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
555 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
556 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
557 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
558 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
560 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
561 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
562 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
563 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
565 setOperationAction(ISD::AND, MVT::v2i16, Promote);
566 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
567 setOperationAction(ISD::OR, MVT::v2i16, Promote);
568 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
569 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
570 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
572 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
573 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
574 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
575 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
577 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
578 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
579 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
580 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
582 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
583 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
584 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
585 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
587 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
588 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
589 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
591 if (!Subtarget->hasVOP3PInsts()) {
592 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
593 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
596 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
597 // This isn't really legal, but this avoids the legalizer unrolling it (and
598 // allows matching fneg (fabs x) patterns)
599 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
601 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
602 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
603 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
604 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
606 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
607 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
609 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
610 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
613 if (Subtarget->hasVOP3PInsts()) {
614 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
615 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
616 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
617 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
618 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
619 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
620 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
621 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
622 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
623 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
625 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
626 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
629 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
630 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
632 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
634 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
635 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
637 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
638 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
640 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
641 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
642 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
643 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
644 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
645 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
647 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
648 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
649 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
650 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
652 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
653 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
656 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
657 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
659 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
660 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
661 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
663 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
664 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
665 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
668 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
669 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
671 if (Subtarget->has16BitInsts()) {
672 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
673 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
674 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
675 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
677 // Legalization hack.
678 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
679 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
681 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
682 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
685 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
686 setOperationAction(ISD::SELECT, VT, Custom);
689 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
690 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
691 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
692 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
693 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
694 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
695 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
697 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
698 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
699 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
700 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
701 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
702 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
704 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
705 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
707 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
708 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
709 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
710 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
711 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
712 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
713 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
714 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
716 setTargetDAGCombine(ISD::ADD);
717 setTargetDAGCombine(ISD::ADDCARRY);
718 setTargetDAGCombine(ISD::SUB);
719 setTargetDAGCombine(ISD::SUBCARRY);
720 setTargetDAGCombine(ISD::FADD);
721 setTargetDAGCombine(ISD::FSUB);
722 setTargetDAGCombine(ISD::FMINNUM);
723 setTargetDAGCombine(ISD::FMAXNUM);
724 setTargetDAGCombine(ISD::FMINNUM_IEEE);
725 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
726 setTargetDAGCombine(ISD::FMA);
727 setTargetDAGCombine(ISD::SMIN);
728 setTargetDAGCombine(ISD::SMAX);
729 setTargetDAGCombine(ISD::UMIN);
730 setTargetDAGCombine(ISD::UMAX);
731 setTargetDAGCombine(ISD::SETCC);
732 setTargetDAGCombine(ISD::AND);
733 setTargetDAGCombine(ISD::OR);
734 setTargetDAGCombine(ISD::XOR);
735 setTargetDAGCombine(ISD::SINT_TO_FP);
736 setTargetDAGCombine(ISD::UINT_TO_FP);
737 setTargetDAGCombine(ISD::FCANONICALIZE);
738 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
739 setTargetDAGCombine(ISD::ZERO_EXTEND);
740 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
741 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
742 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
744 // All memory operations. Some folding on the pointer operand is done to help
745 // matching the constant offsets in the addressing modes.
746 setTargetDAGCombine(ISD::LOAD);
747 setTargetDAGCombine(ISD::STORE);
748 setTargetDAGCombine(ISD::ATOMIC_LOAD);
749 setTargetDAGCombine(ISD::ATOMIC_STORE);
750 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
751 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
752 setTargetDAGCombine(ISD::ATOMIC_SWAP);
753 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
754 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
755 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
756 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
757 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
758 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
759 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
760 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
761 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
762 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
763 setTargetDAGCombine(ISD::ATOMIC_LOAD_FADD);
765 setSchedulingPreference(Sched::RegPressure);
768 const GCNSubtarget *SITargetLowering::getSubtarget() const {
772 //===----------------------------------------------------------------------===//
773 // TargetLowering queries
774 //===----------------------------------------------------------------------===//
776 // v_mad_mix* support a conversion from f16 to f32.
778 // There is only one special case when denormals are enabled we don't currently,
779 // where this is OK to use.
780 bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
781 EVT DestVT, EVT SrcVT) const {
782 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
784 DestVT.getScalarType() == MVT::f32 &&
785 SrcVT.getScalarType() == MVT::f16 &&
786 !hasFP32Denormals(DAG.getMachineFunction());
789 bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
790 // SI has some legal vector types, but no legal vector operations. Say no
791 // shuffles are legal in order to prefer scalarizing some vector operations.
795 MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
798 if (CC == CallingConv::AMDGPU_KERNEL)
799 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
802 EVT ScalarVT = VT.getScalarType();
803 unsigned Size = ScalarVT.getSizeInBits();
805 return ScalarVT.getSimpleVT();
810 if (Size == 16 && Subtarget->has16BitInsts())
811 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
812 } else if (VT.getSizeInBits() > 32)
815 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
818 unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
821 if (CC == CallingConv::AMDGPU_KERNEL)
822 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
825 unsigned NumElts = VT.getVectorNumElements();
826 EVT ScalarVT = VT.getScalarType();
827 unsigned Size = ScalarVT.getSizeInBits();
833 return NumElts * ((Size + 31) / 32);
835 if (Size == 16 && Subtarget->has16BitInsts())
836 return (NumElts + 1) / 2;
837 } else if (VT.getSizeInBits() > 32)
838 return (VT.getSizeInBits() + 31) / 32;
840 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
843 unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
844 LLVMContext &Context, CallingConv::ID CC,
845 EVT VT, EVT &IntermediateVT,
846 unsigned &NumIntermediates, MVT &RegisterVT) const {
847 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
848 unsigned NumElts = VT.getVectorNumElements();
849 EVT ScalarVT = VT.getScalarType();
850 unsigned Size = ScalarVT.getSizeInBits();
852 RegisterVT = ScalarVT.getSimpleVT();
853 IntermediateVT = RegisterVT;
854 NumIntermediates = NumElts;
855 return NumIntermediates;
859 RegisterVT = MVT::i32;
860 IntermediateVT = RegisterVT;
861 NumIntermediates = NumElts * ((Size + 31) / 32);
862 return NumIntermediates;
865 // FIXME: We should fix the ABI to be the same on targets without 16-bit
866 // support, but unless we can properly handle 3-vectors, it will be still be
868 if (Size == 16 && Subtarget->has16BitInsts()) {
869 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
870 IntermediateVT = RegisterVT;
871 NumIntermediates = (NumElts + 1) / 2;
872 return NumIntermediates;
876 return TargetLowering::getVectorTypeBreakdownForCallingConv(
877 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
880 static MVT memVTFromAggregate(Type *Ty) {
881 // Only limited forms of aggregate type currently expected.
882 assert(Ty->isStructTy() && "Expected struct type");
885 Type *ElementType = nullptr;
887 if (Ty->getContainedType(0)->isVectorTy()) {
888 VectorType *VecComponent = cast<VectorType>(Ty->getContainedType(0));
889 ElementType = VecComponent->getElementType();
890 NumElts = VecComponent->getNumElements();
892 ElementType = Ty->getContainedType(0);
896 assert((Ty->getContainedType(1) && Ty->getContainedType(1)->isIntegerTy(32)) && "Expected int32 type");
898 // Calculate the size of the memVT type from the aggregate
899 unsigned Pow2Elts = 0;
900 unsigned ElementSize;
901 switch (ElementType->getTypeID()) {
903 llvm_unreachable("Unknown type!");
904 case Type::IntegerTyID:
905 ElementSize = cast<IntegerType>(ElementType)->getBitWidth();
910 case Type::FloatTyID:
914 unsigned AdditionalElts = ElementSize == 16 ? 2 : 1;
915 Pow2Elts = 1 << Log2_32_Ceil(NumElts + AdditionalElts);
917 return MVT::getVectorVT(MVT::getVT(ElementType, false),
921 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
924 unsigned IntrID) const {
925 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
926 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
927 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
928 (Intrinsic::ID)IntrID);
929 if (Attr.hasFnAttribute(Attribute::ReadNone))
932 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
934 if (RsrcIntr->IsImage) {
935 Info.ptrVal = MFI->getImagePSV(
936 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
937 CI.getArgOperand(RsrcIntr->RsrcArg));
940 Info.ptrVal = MFI->getBufferPSV(
941 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
942 CI.getArgOperand(RsrcIntr->RsrcArg));
945 Info.flags = MachineMemOperand::MODereferenceable;
946 if (Attr.hasFnAttribute(Attribute::ReadOnly)) {
947 Info.opc = ISD::INTRINSIC_W_CHAIN;
948 Info.memVT = MVT::getVT(CI.getType(), true);
949 if (Info.memVT == MVT::Other) {
950 // Some intrinsics return an aggregate type - special case to work out
952 Info.memVT = memVTFromAggregate(CI.getType());
954 Info.flags |= MachineMemOperand::MOLoad;
955 } else if (Attr.hasFnAttribute(Attribute::WriteOnly)) {
956 Info.opc = ISD::INTRINSIC_VOID;
957 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
958 Info.flags |= MachineMemOperand::MOStore;
961 Info.opc = ISD::INTRINSIC_W_CHAIN;
962 Info.memVT = MVT::getVT(CI.getType());
963 Info.flags = MachineMemOperand::MOLoad |
964 MachineMemOperand::MOStore |
965 MachineMemOperand::MODereferenceable;
967 // XXX - Should this be volatile without known ordering?
968 Info.flags |= MachineMemOperand::MOVolatile;
974 case Intrinsic::amdgcn_atomic_inc:
975 case Intrinsic::amdgcn_atomic_dec:
976 case Intrinsic::amdgcn_ds_ordered_add:
977 case Intrinsic::amdgcn_ds_ordered_swap:
978 case Intrinsic::amdgcn_ds_fadd:
979 case Intrinsic::amdgcn_ds_fmin:
980 case Intrinsic::amdgcn_ds_fmax: {
981 Info.opc = ISD::INTRINSIC_W_CHAIN;
982 Info.memVT = MVT::getVT(CI.getType());
983 Info.ptrVal = CI.getOperand(0);
985 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
987 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
989 Info.flags |= MachineMemOperand::MOVolatile;
993 case Intrinsic::amdgcn_buffer_atomic_fadd: {
994 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
996 Info.opc = ISD::INTRINSIC_VOID;
997 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
998 Info.ptrVal = MFI->getBufferPSV(
999 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
1000 CI.getArgOperand(1));
1002 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1004 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
1005 if (!Vol || !Vol->isZero())
1006 Info.flags |= MachineMemOperand::MOVolatile;
1010 case Intrinsic::amdgcn_global_atomic_fadd: {
1011 Info.opc = ISD::INTRINSIC_VOID;
1012 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()
1013 ->getPointerElementType());
1014 Info.ptrVal = CI.getOperand(0);
1016 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1020 case Intrinsic::amdgcn_ds_append:
1021 case Intrinsic::amdgcn_ds_consume: {
1022 Info.opc = ISD::INTRINSIC_W_CHAIN;
1023 Info.memVT = MVT::getVT(CI.getType());
1024 Info.ptrVal = CI.getOperand(0);
1026 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1028 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1030 Info.flags |= MachineMemOperand::MOVolatile;
1034 case Intrinsic::amdgcn_ds_gws_init:
1035 case Intrinsic::amdgcn_ds_gws_barrier:
1036 case Intrinsic::amdgcn_ds_gws_sema_v:
1037 case Intrinsic::amdgcn_ds_gws_sema_br:
1038 case Intrinsic::amdgcn_ds_gws_sema_p:
1039 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1040 Info.opc = ISD::INTRINSIC_VOID;
1042 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1044 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1046 // This is an abstract access, but we need to specify a type and size.
1047 Info.memVT = MVT::i32;
1049 Info.align = Align(4);
1051 Info.flags = MachineMemOperand::MOStore;
1052 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1053 Info.flags = MachineMemOperand::MOLoad;
1061 bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
1062 SmallVectorImpl<Value*> &Ops,
1063 Type *&AccessTy) const {
1064 switch (II->getIntrinsicID()) {
1065 case Intrinsic::amdgcn_atomic_inc:
1066 case Intrinsic::amdgcn_atomic_dec:
1067 case Intrinsic::amdgcn_ds_ordered_add:
1068 case Intrinsic::amdgcn_ds_ordered_swap:
1069 case Intrinsic::amdgcn_ds_fadd:
1070 case Intrinsic::amdgcn_ds_fmin:
1071 case Intrinsic::amdgcn_ds_fmax: {
1072 Value *Ptr = II->getArgOperand(0);
1073 AccessTy = II->getType();
1082 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1083 if (!Subtarget->hasFlatInstOffsets()) {
1084 // Flat instructions do not have offsets, and only have the register
1086 return AM.BaseOffs == 0 && AM.Scale == 0;
1089 return AM.Scale == 0 &&
1090 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1091 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS,
1095 bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
1096 if (Subtarget->hasFlatGlobalInsts())
1097 return AM.Scale == 0 &&
1098 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1099 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS,
1102 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1103 // Assume the we will use FLAT for all global memory accesses
1105 // FIXME: This assumption is currently wrong. On VI we still use
1106 // MUBUF instructions for the r + i addressing mode. As currently
1107 // implemented, the MUBUF instructions only work on buffer < 4GB.
1108 // It may be possible to support > 4GB buffers with MUBUF instructions,
1109 // by setting the stride value in the resource descriptor which would
1110 // increase the size limit to (stride * 4GB). However, this is risky,
1111 // because it has never been validated.
1112 return isLegalFlatAddressingMode(AM);
1115 return isLegalMUBUFAddressingMode(AM);
1118 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1119 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1120 // additionally can do r + r + i with addr64. 32-bit has more addressing
1121 // mode options. Depending on the resource constant, it can also do
1122 // (i64 r0) + (i32 r1) * (i14 i).
1124 // Private arrays end up using a scratch buffer most of the time, so also
1125 // assume those use MUBUF instructions. Scratch loads / stores are currently
1126 // implemented as mubuf instructions with offen bit set, so slightly
1127 // different than the normal addr64.
1128 if (!isUInt<12>(AM.BaseOffs))
1131 // FIXME: Since we can split immediate into soffset and immediate offset,
1132 // would it make sense to allow any immediate?
1135 case 0: // r + i or just i, depending on HasBaseReg.
1138 return true; // We have r + r or r + i.
1140 if (AM.HasBaseReg) {
1141 // Reject 2 * r + r.
1145 // Allow 2 * r as r + r
1146 // Or 2 * r + i is allowed as r + r + i.
1148 default: // Don't allow n * r
1153 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1154 const AddrMode &AM, Type *Ty,
1155 unsigned AS, Instruction *I) const {
1156 // No global is ever allowed as a base.
1160 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1161 return isLegalGlobalAddressingMode(AM);
1163 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1164 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
1165 AS == AMDGPUAS::BUFFER_FAT_POINTER) {
1166 // If the offset isn't a multiple of 4, it probably isn't going to be
1167 // correctly aligned.
1168 // FIXME: Can we get the real alignment here?
1169 if (AM.BaseOffs % 4 != 0)
1170 return isLegalMUBUFAddressingMode(AM);
1172 // There are no SMRD extloads, so if we have to do a small type access we
1173 // will use a MUBUF load.
1174 // FIXME?: We also need to do this if unaligned, but we don't know the
1176 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1177 return isLegalGlobalAddressingMode(AM);
1179 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1180 // SMRD instructions have an 8-bit, dword offset on SI.
1181 if (!isUInt<8>(AM.BaseOffs / 4))
1183 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1184 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1185 // in 8-bits, it can use a smaller encoding.
1186 if (!isUInt<32>(AM.BaseOffs / 4))
1188 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1189 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1190 if (!isUInt<20>(AM.BaseOffs))
1193 llvm_unreachable("unhandled generation");
1195 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1198 if (AM.Scale == 1 && AM.HasBaseReg)
1203 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1204 return isLegalMUBUFAddressingMode(AM);
1205 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1206 AS == AMDGPUAS::REGION_ADDRESS) {
1207 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1209 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1210 // an 8-bit dword offset but we don't know the alignment here.
1211 if (!isUInt<16>(AM.BaseOffs))
1214 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1217 if (AM.Scale == 1 && AM.HasBaseReg)
1221 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1222 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1223 // For an unknown address space, this usually means that this is for some
1224 // reason being used for pure arithmetic, and not based on some addressing
1225 // computation. We don't have instructions that compute pointers with any
1226 // addressing modes, so treat them as having no offset like flat
1228 return isLegalFlatAddressingMode(AM);
1230 llvm_unreachable("unhandled address space");
1234 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1235 const SelectionDAG &DAG) const {
1236 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1237 return (MemVT.getSizeInBits() <= 4 * 32);
1238 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1239 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1240 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1241 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1242 return (MemVT.getSizeInBits() <= 2 * 32);
1247 bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
1248 unsigned Size, unsigned AddrSpace, unsigned Align,
1249 MachineMemOperand::Flags Flags, bool *IsFast) const {
1253 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1254 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1255 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
1256 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
1257 // with adjacent offsets.
1258 bool AlignedBy4 = (Align % 4 == 0);
1260 *IsFast = AlignedBy4;
1265 // FIXME: We have to be conservative here and assume that flat operations
1266 // will access scratch. If we had access to the IR function, then we
1267 // could determine if any private memory was used in the function.
1268 if (!Subtarget->hasUnalignedScratchAccess() &&
1269 (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
1270 AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
1271 bool AlignedBy4 = Align >= 4;
1273 *IsFast = AlignedBy4;
1278 if (Subtarget->hasUnalignedBufferAccess()) {
1279 // If we have an uniform constant load, it still requires using a slow
1280 // buffer instruction if unaligned.
1282 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1283 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1284 (Align % 4 == 0) : true;
1290 // Smaller than dword value must be aligned.
1294 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1295 // byte-address are ignored, thus forcing Dword alignment.
1296 // This applies to private, global, and constant memory.
1300 return Size >= 32 && Align >= 4;
1303 bool SITargetLowering::allowsMisalignedMemoryAccesses(
1304 EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
1305 bool *IsFast) const {
1309 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1310 // which isn't a simple VT.
1311 // Until MVT is extended to handle this, simply check for the size and
1312 // rely on the condition below: allow accesses if the size is a multiple of 4.
1313 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1314 VT.getStoreSize() > 16)) {
1318 return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1319 Align, Flags, IsFast);
1322 EVT SITargetLowering::getOptimalMemOpType(
1323 uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
1324 bool ZeroMemset, bool MemcpyStrSrc,
1325 const AttributeList &FuncAttributes) const {
1326 // FIXME: Should account for address space here.
1328 // The default fallback uses the private pointer size as a guess for a type to
1329 // use. Make sure we switch these to 64-bit accesses.
1331 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
1334 if (Size >= 8 && DstAlign >= 4)
1341 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1342 unsigned DestAS) const {
1343 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
1346 bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1347 const MemSDNode *MemNode = cast<MemSDNode>(N);
1348 const Value *Ptr = MemNode->getMemOperand()->getValue();
1349 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1350 return I && I->getMetadata("amdgpu.noclobber");
1353 bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
1354 unsigned DestAS) const {
1355 // Flat -> private/local is a simple truncate.
1356 // Flat -> global is no-op
1357 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1360 return isNoopAddrSpaceCast(SrcAS, DestAS);
1363 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1364 const MemSDNode *MemNode = cast<MemSDNode>(N);
1366 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1369 TargetLoweringBase::LegalizeTypeAction
1370 SITargetLowering::getPreferredVectorAction(MVT VT) const {
1371 int NumElts = VT.getVectorNumElements();
1372 if (NumElts != 1 && VT.getScalarType().bitsLE(MVT::i16))
1373 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
1374 return TargetLoweringBase::getPreferredVectorAction(VT);
1377 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1379 // FIXME: Could be smarter if called for vector constants.
1383 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1384 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1389 // These operations are done with 32-bit instructions anyway.
1394 // TODO: Extensions?
1401 // SimplifySetCC uses this function to determine whether or not it should
1402 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1403 if (VT == MVT::i1 && Op == ISD::SETCC)
1406 return TargetLowering::isTypeDesirableForOp(Op, VT);
1409 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1412 uint64_t Offset) const {
1413 const DataLayout &DL = DAG.getDataLayout();
1414 MachineFunction &MF = DAG.getMachineFunction();
1415 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1417 const ArgDescriptor *InputPtrReg;
1418 const TargetRegisterClass *RC;
1420 std::tie(InputPtrReg, RC)
1421 = Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1423 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1424 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1425 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1426 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1428 return DAG.getObjectPtrOffset(SL, BasePtr, Offset);
1431 SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1432 const SDLoc &SL) const {
1433 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1435 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1438 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1439 const SDLoc &SL, SDValue Val,
1441 const ISD::InputArg *Arg) const {
1442 // First, if it is a widened vector, narrow it.
1443 if (VT.isVector() &&
1444 VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1446 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(),
1447 VT.getVectorNumElements());
1448 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1449 DAG.getConstant(0, SL, MVT::i32));
1452 // Then convert the vector elements or scalar value.
1453 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1455 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1456 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1459 if (MemVT.isFloatingPoint())
1460 Val = getFPExtOrFPTrunc(DAG, Val, SL, VT);
1462 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1464 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1469 SDValue SITargetLowering::lowerKernargMemParameter(
1470 SelectionDAG &DAG, EVT VT, EVT MemVT,
1471 const SDLoc &SL, SDValue Chain,
1472 uint64_t Offset, unsigned Align, bool Signed,
1473 const ISD::InputArg *Arg) const {
1474 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
1476 // Try to avoid using an extload by loading earlier than the argument address,
1477 // and extracting the relevant bits. The load should hopefully be merged with
1478 // the previous argument.
1479 if (MemVT.getStoreSize() < 4 && Align < 4) {
1480 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1481 int64_t AlignDownOffset = alignDown(Offset, 4);
1482 int64_t OffsetDiff = Offset - AlignDownOffset;
1484 EVT IntVT = MemVT.changeTypeToInteger();
1486 // TODO: If we passed in the base kernel offset we could have a better
1487 // alignment than 4, but we don't really need it.
1488 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1489 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, 4,
1490 MachineMemOperand::MODereferenceable |
1491 MachineMemOperand::MOInvariant);
1493 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1494 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1496 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1497 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1498 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1501 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1504 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1505 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
1506 MachineMemOperand::MODereferenceable |
1507 MachineMemOperand::MOInvariant);
1509 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1510 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1513 SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1514 const SDLoc &SL, SDValue Chain,
1515 const ISD::InputArg &Arg) const {
1516 MachineFunction &MF = DAG.getMachineFunction();
1517 MachineFrameInfo &MFI = MF.getFrameInfo();
1519 if (Arg.Flags.isByVal()) {
1520 unsigned Size = Arg.Flags.getByValSize();
1521 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1522 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1525 unsigned ArgOffset = VA.getLocMemOffset();
1526 unsigned ArgSize = VA.getValVT().getStoreSize();
1528 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1530 // Create load nodes to retrieve arguments from the stack.
1531 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1534 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1535 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1536 MVT MemVT = VA.getValVT();
1538 switch (VA.getLocInfo()) {
1541 case CCValAssign::BCvt:
1542 MemVT = VA.getLocVT();
1544 case CCValAssign::SExt:
1545 ExtType = ISD::SEXTLOAD;
1547 case CCValAssign::ZExt:
1548 ExtType = ISD::ZEXTLOAD;
1550 case CCValAssign::AExt:
1551 ExtType = ISD::EXTLOAD;
1555 ArgValue = DAG.getExtLoad(
1556 ExtType, SL, VA.getLocVT(), Chain, FIN,
1557 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1562 SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1563 const SIMachineFunctionInfo &MFI,
1565 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1566 const ArgDescriptor *Reg;
1567 const TargetRegisterClass *RC;
1569 std::tie(Reg, RC) = MFI.getPreloadedValue(PVID);
1570 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1573 static void processShaderInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1574 CallingConv::ID CallConv,
1575 ArrayRef<ISD::InputArg> Ins,
1577 FunctionType *FType,
1578 SIMachineFunctionInfo *Info) {
1579 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1580 const ISD::InputArg *Arg = &Ins[I];
1582 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&
1583 "vector type argument should have been split");
1585 // First check if it's a PS input addr.
1586 if (CallConv == CallingConv::AMDGPU_PS &&
1587 !Arg->Flags.isInReg() && PSInputNum <= 15) {
1588 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1590 // Inconveniently only the first part of the split is marked as isSplit,
1591 // so skip to the end. We only want to increment PSInputNum once for the
1592 // entire split argument.
1593 if (Arg->Flags.isSplit()) {
1594 while (!Arg->Flags.isSplitEnd()) {
1595 assert((!Arg->VT.isVector() ||
1596 Arg->VT.getScalarSizeInBits() == 16) &&
1597 "unexpected vector split in ps argument type");
1599 Splits.push_back(*Arg);
1605 // We can safely skip PS inputs.
1606 Skipped.set(Arg->getOrigArgIndex());
1611 Info->markPSInputAllocated(PSInputNum);
1613 Info->markPSInputEnabled(PSInputNum);
1618 Splits.push_back(*Arg);
1622 // Allocate special inputs passed in VGPRs.
1623 void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1624 MachineFunction &MF,
1625 const SIRegisterInfo &TRI,
1626 SIMachineFunctionInfo &Info) const {
1627 const LLT S32 = LLT::scalar(32);
1628 MachineRegisterInfo &MRI = MF.getRegInfo();
1630 if (Info.hasWorkItemIDX()) {
1631 Register Reg = AMDGPU::VGPR0;
1632 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1634 CCInfo.AllocateReg(Reg);
1635 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg));
1638 if (Info.hasWorkItemIDY()) {
1639 Register Reg = AMDGPU::VGPR1;
1640 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1642 CCInfo.AllocateReg(Reg);
1643 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1646 if (Info.hasWorkItemIDZ()) {
1647 Register Reg = AMDGPU::VGPR2;
1648 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1650 CCInfo.AllocateReg(Reg);
1651 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1655 // Try to allocate a VGPR at the end of the argument list, or if no argument
1656 // VGPRs are left allocating a stack slot.
1657 // If \p Mask is is given it indicates bitfield position in the register.
1658 // If \p Arg is given use it with new ]p Mask instead of allocating new.
1659 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1660 ArgDescriptor Arg = ArgDescriptor()) {
1662 return ArgDescriptor::createArg(Arg, Mask);
1664 ArrayRef<MCPhysReg> ArgVGPRs
1665 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1666 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1667 if (RegIdx == ArgVGPRs.size()) {
1668 // Spill to stack required.
1669 int64_t Offset = CCInfo.AllocateStack(4, 4);
1671 return ArgDescriptor::createStack(Offset, Mask);
1674 unsigned Reg = ArgVGPRs[RegIdx];
1675 Reg = CCInfo.AllocateReg(Reg);
1676 assert(Reg != AMDGPU::NoRegister);
1678 MachineFunction &MF = CCInfo.getMachineFunction();
1679 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1680 MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1681 return ArgDescriptor::createRegister(Reg, Mask);
1684 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1685 const TargetRegisterClass *RC,
1686 unsigned NumArgRegs) {
1687 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1688 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1689 if (RegIdx == ArgSGPRs.size())
1690 report_fatal_error("ran out of SGPRs for arguments");
1692 unsigned Reg = ArgSGPRs[RegIdx];
1693 Reg = CCInfo.AllocateReg(Reg);
1694 assert(Reg != AMDGPU::NoRegister);
1696 MachineFunction &MF = CCInfo.getMachineFunction();
1697 MF.addLiveIn(Reg, RC);
1698 return ArgDescriptor::createRegister(Reg);
1701 static ArgDescriptor allocateSGPR32Input(CCState &CCInfo) {
1702 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1705 static ArgDescriptor allocateSGPR64Input(CCState &CCInfo) {
1706 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
1709 void SITargetLowering::allocateSpecialInputVGPRs(CCState &CCInfo,
1710 MachineFunction &MF,
1711 const SIRegisterInfo &TRI,
1712 SIMachineFunctionInfo &Info) const {
1713 const unsigned Mask = 0x3ff;
1716 if (Info.hasWorkItemIDX()) {
1717 Arg = allocateVGPR32Input(CCInfo, Mask);
1718 Info.setWorkItemIDX(Arg);
1721 if (Info.hasWorkItemIDY()) {
1722 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
1723 Info.setWorkItemIDY(Arg);
1726 if (Info.hasWorkItemIDZ())
1727 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
1730 void SITargetLowering::allocateSpecialInputSGPRs(
1732 MachineFunction &MF,
1733 const SIRegisterInfo &TRI,
1734 SIMachineFunctionInfo &Info) const {
1735 auto &ArgInfo = Info.getArgInfo();
1737 // TODO: Unify handling with private memory pointers.
1739 if (Info.hasDispatchPtr())
1740 ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
1742 if (Info.hasQueuePtr())
1743 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
1745 if (Info.hasKernargSegmentPtr())
1746 ArgInfo.KernargSegmentPtr = allocateSGPR64Input(CCInfo);
1748 if (Info.hasDispatchID())
1749 ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
1751 // flat_scratch_init is not applicable for non-kernel functions.
1753 if (Info.hasWorkGroupIDX())
1754 ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
1756 if (Info.hasWorkGroupIDY())
1757 ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
1759 if (Info.hasWorkGroupIDZ())
1760 ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
1762 if (Info.hasImplicitArgPtr())
1763 ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
1766 // Allocate special inputs passed in user SGPRs.
1767 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
1768 MachineFunction &MF,
1769 const SIRegisterInfo &TRI,
1770 SIMachineFunctionInfo &Info) const {
1771 if (Info.hasImplicitBufferPtr()) {
1772 unsigned ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
1773 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1774 CCInfo.AllocateReg(ImplicitBufferPtrReg);
1777 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
1778 if (Info.hasPrivateSegmentBuffer()) {
1779 unsigned PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
1780 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1781 CCInfo.AllocateReg(PrivateSegmentBufferReg);
1784 if (Info.hasDispatchPtr()) {
1785 unsigned DispatchPtrReg = Info.addDispatchPtr(TRI);
1786 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1787 CCInfo.AllocateReg(DispatchPtrReg);
1790 if (Info.hasQueuePtr()) {
1791 unsigned QueuePtrReg = Info.addQueuePtr(TRI);
1792 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1793 CCInfo.AllocateReg(QueuePtrReg);
1796 if (Info.hasKernargSegmentPtr()) {
1797 MachineRegisterInfo &MRI = MF.getRegInfo();
1798 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
1799 CCInfo.AllocateReg(InputPtrReg);
1801 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1802 MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
1805 if (Info.hasDispatchID()) {
1806 unsigned DispatchIDReg = Info.addDispatchID(TRI);
1807 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1808 CCInfo.AllocateReg(DispatchIDReg);
1811 if (Info.hasFlatScratchInit()) {
1812 unsigned FlatScratchInitReg = Info.addFlatScratchInit(TRI);
1813 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1814 CCInfo.AllocateReg(FlatScratchInitReg);
1817 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
1818 // these from the dispatch pointer.
1821 // Allocate special input registers that are initialized per-wave.
1822 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
1823 MachineFunction &MF,
1824 SIMachineFunctionInfo &Info,
1825 CallingConv::ID CallConv,
1826 bool IsShader) const {
1827 if (Info.hasWorkGroupIDX()) {
1828 unsigned Reg = Info.addWorkGroupIDX();
1829 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1830 CCInfo.AllocateReg(Reg);
1833 if (Info.hasWorkGroupIDY()) {
1834 unsigned Reg = Info.addWorkGroupIDY();
1835 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1836 CCInfo.AllocateReg(Reg);
1839 if (Info.hasWorkGroupIDZ()) {
1840 unsigned Reg = Info.addWorkGroupIDZ();
1841 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1842 CCInfo.AllocateReg(Reg);
1845 if (Info.hasWorkGroupInfo()) {
1846 unsigned Reg = Info.addWorkGroupInfo();
1847 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1848 CCInfo.AllocateReg(Reg);
1851 if (Info.hasPrivateSegmentWaveByteOffset()) {
1852 // Scratch wave offset passed in system SGPR.
1853 unsigned PrivateSegmentWaveByteOffsetReg;
1856 PrivateSegmentWaveByteOffsetReg =
1857 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
1859 // This is true if the scratch wave byte offset doesn't have a fixed
1861 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
1862 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
1863 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
1866 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
1868 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1869 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1873 static void reservePrivateMemoryRegs(const TargetMachine &TM,
1874 MachineFunction &MF,
1875 const SIRegisterInfo &TRI,
1876 SIMachineFunctionInfo &Info) {
1877 // Now that we've figured out where the scratch register inputs are, see if
1878 // should reserve the arguments and use them directly.
1879 MachineFrameInfo &MFI = MF.getFrameInfo();
1880 bool HasStackObjects = MFI.hasStackObjects();
1881 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1883 // Record that we know we have non-spill stack objects so we don't need to
1884 // check all stack objects later.
1885 if (HasStackObjects)
1886 Info.setHasNonSpillStackObjects(true);
1888 // Everything live out of a block is spilled with fast regalloc, so it's
1889 // almost certain that spilling will be required.
1890 if (TM.getOptLevel() == CodeGenOpt::None)
1891 HasStackObjects = true;
1893 // For now assume stack access is needed in any callee functions, so we need
1894 // the scratch registers to pass in.
1895 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
1897 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
1898 // If we have stack objects, we unquestionably need the private buffer
1899 // resource. For the Code Object V2 ABI, this will be the first 4 user
1900 // SGPR inputs. We can reserve those and use them directly.
1902 Register PrivateSegmentBufferReg =
1903 Info.getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
1904 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
1906 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
1907 // We tentatively reserve the last registers (skipping the last registers
1908 // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
1909 // we'll replace these with the ones immediately after those which were
1910 // really allocated. In the prologue copies will be inserted from the
1911 // argument to these reserved registers.
1913 // Without HSA, relocations are used for the scratch pointer and the
1914 // buffer resource setup is always inserted in the prologue. Scratch wave
1915 // offset is still in an input SGPR.
1916 Info.setScratchRSrcReg(ReservedBufferReg);
1919 // hasFP should be accurate for kernels even before the frame is finalized.
1920 if (ST.getFrameLowering()->hasFP(MF)) {
1921 MachineRegisterInfo &MRI = MF.getRegInfo();
1923 // Try to use s32 as the SP, but move it if it would interfere with input
1924 // arguments. This won't work with calls though.
1926 // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
1928 if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
1929 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
1931 assert(AMDGPU::isShader(MF.getFunction().getCallingConv()));
1934 report_fatal_error("call in graphics shader with too many input SGPRs");
1936 for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
1937 if (!MRI.isLiveIn(Reg)) {
1938 Info.setStackPtrOffsetReg(Reg);
1943 if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
1944 report_fatal_error("failed to find register for SP");
1947 if (MFI.hasCalls()) {
1948 Info.setScratchWaveOffsetReg(AMDGPU::SGPR33);
1949 Info.setFrameOffsetReg(AMDGPU::SGPR33);
1951 unsigned ReservedOffsetReg =
1952 TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1953 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1954 Info.setFrameOffsetReg(ReservedOffsetReg);
1956 } else if (RequiresStackAccess) {
1957 assert(!MFI.hasCalls());
1958 // We know there are accesses and they will be done relative to SP, so just
1959 // pin it to the input.
1961 // FIXME: Should not do this if inline asm is reading/writing these
1963 Register PreloadedSP = Info.getPreloadedReg(
1964 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1966 Info.setStackPtrOffsetReg(PreloadedSP);
1967 Info.setScratchWaveOffsetReg(PreloadedSP);
1968 Info.setFrameOffsetReg(PreloadedSP);
1970 assert(!MFI.hasCalls());
1972 // There may not be stack access at all. There may still be spills, or
1973 // access of a constant pointer (in which cases an extra copy will be
1974 // emitted in the prolog).
1975 unsigned ReservedOffsetReg
1976 = TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1977 Info.setStackPtrOffsetReg(ReservedOffsetReg);
1978 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1979 Info.setFrameOffsetReg(ReservedOffsetReg);
1983 bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
1984 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
1985 return !Info->isEntryFunction();
1988 void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
1992 void SITargetLowering::insertCopiesSplitCSR(
1993 MachineBasicBlock *Entry,
1994 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
1995 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
1997 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
2001 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2002 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
2003 MachineBasicBlock::iterator MBBI = Entry->begin();
2004 for (const MCPhysReg *I = IStart; *I; ++I) {
2005 const TargetRegisterClass *RC = nullptr;
2006 if (AMDGPU::SReg_64RegClass.contains(*I))
2007 RC = &AMDGPU::SGPR_64RegClass;
2008 else if (AMDGPU::SReg_32RegClass.contains(*I))
2009 RC = &AMDGPU::SGPR_32RegClass;
2011 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2013 Register NewVR = MRI->createVirtualRegister(RC);
2014 // Create copy from CSR to a virtual register.
2015 Entry->addLiveIn(*I);
2016 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2019 // Insert the copy-back instructions right before the terminator.
2020 for (auto *Exit : Exits)
2021 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2022 TII->get(TargetOpcode::COPY), *I)
2027 SDValue SITargetLowering::LowerFormalArguments(
2028 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2029 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2030 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2031 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2033 MachineFunction &MF = DAG.getMachineFunction();
2034 const Function &Fn = MF.getFunction();
2035 FunctionType *FType = MF.getFunction().getFunctionType();
2036 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2038 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
2039 DiagnosticInfoUnsupported NoGraphicsHSA(
2040 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2041 DAG.getContext()->diagnose(NoGraphicsHSA);
2042 return DAG.getEntryNode();
2045 SmallVector<ISD::InputArg, 16> Splits;
2046 SmallVector<CCValAssign, 16> ArgLocs;
2047 BitVector Skipped(Ins.size());
2048 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2051 bool IsShader = AMDGPU::isShader(CallConv);
2052 bool IsKernel = AMDGPU::isKernel(CallConv);
2053 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2056 processShaderInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2058 // At least one interpolation mode must be enabled or else the GPU will
2061 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2062 // set PSInputAddr, the user wants to enable some bits after the compilation
2063 // based on run-time states. Since we can't know what the final PSInputEna
2064 // will look like, so we shouldn't do anything here and the user should take
2065 // responsibility for the correct programming.
2067 // Otherwise, the following restrictions apply:
2068 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2069 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2071 if (CallConv == CallingConv::AMDGPU_PS) {
2072 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2073 ((Info->getPSInputAddr() & 0xF) == 0 &&
2074 Info->isPSInputAllocated(11))) {
2075 CCInfo.AllocateReg(AMDGPU::VGPR0);
2076 CCInfo.AllocateReg(AMDGPU::VGPR1);
2077 Info->markPSInputAllocated(0);
2078 Info->markPSInputEnabled(0);
2080 if (Subtarget->isAmdPalOS()) {
2081 // For isAmdPalOS, the user does not enable some bits after compilation
2082 // based on run-time states; the register values being generated here are
2083 // the final ones set in hardware. Therefore we need to apply the
2084 // workaround to PSInputAddr and PSInputEnable together. (The case where
2085 // a bit is set in PSInputAddr but not PSInputEnable is where the
2086 // frontend set up an input arg for a particular interpolation mode, but
2087 // nothing uses that input arg. Really we should have an earlier pass
2088 // that removes such an arg.)
2089 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2090 if ((PsInputBits & 0x7F) == 0 ||
2091 ((PsInputBits & 0xF) == 0 &&
2092 (PsInputBits >> 11 & 1)))
2093 Info->markPSInputEnabled(
2094 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
2098 assert(!Info->hasDispatchPtr() &&
2099 !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&
2100 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
2101 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&
2102 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
2103 !Info->hasWorkItemIDZ());
2104 } else if (IsKernel) {
2105 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX());
2107 Splits.append(Ins.begin(), Ins.end());
2111 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2112 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2116 analyzeFormalArgumentsCompute(CCInfo, Ins);
2118 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2119 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2122 SmallVector<SDValue, 16> Chains;
2124 // FIXME: This is the minimum kernel argument alignment. We should improve
2125 // this to the maximum alignment of the arguments.
2127 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2129 const unsigned KernelArgBaseAlign = 16;
2131 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2132 const ISD::InputArg &Arg = Ins[i];
2133 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2134 InVals.push_back(DAG.getUNDEF(Arg.VT));
2138 CCValAssign &VA = ArgLocs[ArgIdx++];
2139 MVT VT = VA.getLocVT();
2141 if (IsEntryFunc && VA.isMemLoc()) {
2143 EVT MemVT = VA.getLocVT();
2145 const uint64_t Offset = VA.getLocMemOffset();
2146 unsigned Align = MinAlign(KernelArgBaseAlign, Offset);
2148 SDValue Arg = lowerKernargMemParameter(
2149 DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
2150 Chains.push_back(Arg.getValue(1));
2153 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2154 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2155 ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2156 ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2157 // On SI local pointers are just offsets into LDS, so they are always
2158 // less than 16-bits. On CI and newer they could potentially be
2159 // real pointers, so we can't guarantee their size.
2160 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2161 DAG.getValueType(MVT::i16));
2164 InVals.push_back(Arg);
2166 } else if (!IsEntryFunc && VA.isMemLoc()) {
2167 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2168 InVals.push_back(Val);
2169 if (!Arg.Flags.isByVal())
2170 Chains.push_back(Val.getValue(1));
2174 assert(VA.isRegLoc() && "Parameter must be in a register!");
2176 Register Reg = VA.getLocReg();
2177 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2178 EVT ValVT = VA.getValVT();
2180 Reg = MF.addLiveIn(Reg, RC);
2181 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2183 if (Arg.Flags.isSRet()) {
2184 // The return object should be reasonably addressable.
2186 // FIXME: This helps when the return is a real sret. If it is a
2187 // automatically inserted sret (i.e. CanLowerReturn returns false), an
2188 // extra copy is inserted in SelectionDAGBuilder which obscures this.
2190 = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
2191 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2192 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2195 // If this is an 8 or 16-bit value, it is really passed promoted
2196 // to 32 bits. Insert an assert[sz]ext to capture this, then
2197 // truncate to the right size.
2198 switch (VA.getLocInfo()) {
2199 case CCValAssign::Full:
2201 case CCValAssign::BCvt:
2202 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2204 case CCValAssign::SExt:
2205 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2206 DAG.getValueType(ValVT));
2207 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2209 case CCValAssign::ZExt:
2210 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2211 DAG.getValueType(ValVT));
2212 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2214 case CCValAssign::AExt:
2215 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2218 llvm_unreachable("Unknown loc info!");
2221 InVals.push_back(Val);
2225 // Special inputs come after user arguments.
2226 allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2229 // Start adding system SGPRs.
2231 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsShader);
2233 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2234 CCInfo.AllocateReg(Info->getScratchWaveOffsetReg());
2235 CCInfo.AllocateReg(Info->getFrameOffsetReg());
2236 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2239 auto &ArgUsageInfo =
2240 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2241 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2243 unsigned StackArgSize = CCInfo.getNextStackOffset();
2244 Info->setBytesInStackArgArea(StackArgSize);
2246 return Chains.empty() ? Chain :
2247 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2250 // TODO: If return values can't fit in registers, we should return as many as
2251 // possible in registers before passing on stack.
2252 bool SITargetLowering::CanLowerReturn(
2253 CallingConv::ID CallConv,
2254 MachineFunction &MF, bool IsVarArg,
2255 const SmallVectorImpl<ISD::OutputArg> &Outs,
2256 LLVMContext &Context) const {
2257 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2258 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2259 // for shaders. Vector types should be explicitly handled by CC.
2260 if (AMDGPU::isEntryFunctionCC(CallConv))
2263 SmallVector<CCValAssign, 16> RVLocs;
2264 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2265 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2269 SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2271 const SmallVectorImpl<ISD::OutputArg> &Outs,
2272 const SmallVectorImpl<SDValue> &OutVals,
2273 const SDLoc &DL, SelectionDAG &DAG) const {
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2277 if (AMDGPU::isKernel(CallConv)) {
2278 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2282 bool IsShader = AMDGPU::isShader(CallConv);
2284 Info->setIfReturnsVoid(Outs.empty());
2285 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2287 // CCValAssign - represent the assignment of the return value to a location.
2288 SmallVector<CCValAssign, 48> RVLocs;
2289 SmallVector<ISD::OutputArg, 48> Splits;
2291 // CCState - Info about the registers and stack slots.
2292 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2295 // Analyze outgoing return values.
2296 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2299 SmallVector<SDValue, 48> RetOps;
2300 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2302 // Add return address for callable functions.
2303 if (!Info->isEntryFunction()) {
2304 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2305 SDValue ReturnAddrReg = CreateLiveInRegister(
2306 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2308 SDValue ReturnAddrVirtualReg = DAG.getRegister(
2309 MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
2312 DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2313 Flag = Chain.getValue(1);
2314 RetOps.push_back(ReturnAddrVirtualReg);
2317 // Copy the result values into the output registers.
2318 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2319 ++I, ++RealRVLocIdx) {
2320 CCValAssign &VA = RVLocs[I];
2321 assert(VA.isRegLoc() && "Can only return in registers!");
2322 // TODO: Partially return in registers if return values don't fit.
2323 SDValue Arg = OutVals[RealRVLocIdx];
2325 // Copied from other backends.
2326 switch (VA.getLocInfo()) {
2327 case CCValAssign::Full:
2329 case CCValAssign::BCvt:
2330 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2332 case CCValAssign::SExt:
2333 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2335 case CCValAssign::ZExt:
2336 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2338 case CCValAssign::AExt:
2339 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2342 llvm_unreachable("Unknown loc info!");
2345 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2346 Flag = Chain.getValue(1);
2347 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2350 // FIXME: Does sret work properly?
2351 if (!Info->isEntryFunction()) {
2352 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2353 const MCPhysReg *I =
2354 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2357 if (AMDGPU::SReg_64RegClass.contains(*I))
2358 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2359 else if (AMDGPU::SReg_32RegClass.contains(*I))
2360 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2362 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2367 // Update chain and glue.
2370 RetOps.push_back(Flag);
2372 unsigned Opc = AMDGPUISD::ENDPGM;
2374 Opc = IsShader ? AMDGPUISD::RETURN_TO_EPILOG : AMDGPUISD::RET_FLAG;
2375 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2378 SDValue SITargetLowering::LowerCallResult(
2379 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2380 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2381 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2382 SDValue ThisVal) const {
2383 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2385 // Assign locations to each value returned by this call.
2386 SmallVector<CCValAssign, 16> RVLocs;
2387 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2389 CCInfo.AnalyzeCallResult(Ins, RetCC);
2391 // Copy all of the result registers out of their specified physreg.
2392 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2393 CCValAssign VA = RVLocs[i];
2396 if (VA.isRegLoc()) {
2397 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2398 Chain = Val.getValue(1);
2399 InFlag = Val.getValue(2);
2400 } else if (VA.isMemLoc()) {
2401 report_fatal_error("TODO: return values in memory");
2403 llvm_unreachable("unknown argument location type");
2405 switch (VA.getLocInfo()) {
2406 case CCValAssign::Full:
2408 case CCValAssign::BCvt:
2409 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2411 case CCValAssign::ZExt:
2412 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2413 DAG.getValueType(VA.getValVT()));
2414 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2416 case CCValAssign::SExt:
2417 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2418 DAG.getValueType(VA.getValVT()));
2419 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2421 case CCValAssign::AExt:
2422 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2425 llvm_unreachable("Unknown loc info!");
2428 InVals.push_back(Val);
2434 // Add code to pass special inputs required depending on used features separate
2435 // from the explicit user arguments present in the IR.
2436 void SITargetLowering::passSpecialInputs(
2437 CallLoweringInfo &CLI,
2439 const SIMachineFunctionInfo &Info,
2440 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2441 SmallVectorImpl<SDValue> &MemOpChains,
2442 SDValue Chain) const {
2443 // If we don't have a call site, this was a call inserted by
2444 // legalization. These can never use special inputs.
2448 const Function *CalleeFunc = CLI.CS.getCalledFunction();
2451 SelectionDAG &DAG = CLI.DAG;
2452 const SDLoc &DL = CLI.DL;
2454 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2456 auto &ArgUsageInfo =
2457 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2458 const AMDGPUFunctionArgInfo &CalleeArgInfo
2459 = ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2461 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2463 // TODO: Unify with private memory register handling. This is complicated by
2464 // the fact that at least in kernels, the input argument is not necessarily
2465 // in the same location as the input.
2466 AMDGPUFunctionArgInfo::PreloadedValue InputRegs[] = {
2467 AMDGPUFunctionArgInfo::DISPATCH_PTR,
2468 AMDGPUFunctionArgInfo::QUEUE_PTR,
2469 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR,
2470 AMDGPUFunctionArgInfo::DISPATCH_ID,
2471 AMDGPUFunctionArgInfo::WORKGROUP_ID_X,
2472 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,
2473 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,
2474 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
2477 for (auto InputID : InputRegs) {
2478 const ArgDescriptor *OutgoingArg;
2479 const TargetRegisterClass *ArgRC;
2481 std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
2485 const ArgDescriptor *IncomingArg;
2486 const TargetRegisterClass *IncomingArgRC;
2487 std::tie(IncomingArg, IncomingArgRC)
2488 = CallerArgInfo.getPreloadedValue(InputID);
2489 assert(IncomingArgRC == ArgRC);
2491 // All special arguments are ints for now.
2492 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2496 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2498 // The implicit arg ptr is special because it doesn't have a corresponding
2499 // input for kernels, and is computed from the kernarg segment pointer.
2500 assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
2501 InputReg = getImplicitArgPtr(DAG, DL);
2504 if (OutgoingArg->isRegister()) {
2505 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2507 unsigned SpecialArgOffset = CCInfo.AllocateStack(ArgVT.getStoreSize(), 4);
2508 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2510 MemOpChains.push_back(ArgStore);
2514 // Pack workitem IDs into a single register or pass it as is if already
2516 const ArgDescriptor *OutgoingArg;
2517 const TargetRegisterClass *ArgRC;
2519 std::tie(OutgoingArg, ArgRC) =
2520 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2522 std::tie(OutgoingArg, ArgRC) =
2523 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2525 std::tie(OutgoingArg, ArgRC) =
2526 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2530 const ArgDescriptor *IncomingArgX
2531 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X).first;
2532 const ArgDescriptor *IncomingArgY
2533 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y).first;
2534 const ArgDescriptor *IncomingArgZ
2535 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z).first;
2540 // If incoming ids are not packed we need to pack them.
2541 if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo.WorkItemIDX)
2542 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2544 if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo.WorkItemIDY) {
2545 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2546 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2547 DAG.getShiftAmountConstant(10, MVT::i32, SL));
2548 InputReg = InputReg.getNode() ?
2549 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2552 if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo.WorkItemIDZ) {
2553 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2554 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2555 DAG.getShiftAmountConstant(20, MVT::i32, SL));
2556 InputReg = InputReg.getNode() ?
2557 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2560 if (!InputReg.getNode()) {
2561 // Workitem ids are already packed, any of present incoming arguments
2562 // will carry all required fields.
2563 ArgDescriptor IncomingArg = ArgDescriptor::createArg(
2564 IncomingArgX ? *IncomingArgX :
2565 IncomingArgY ? *IncomingArgY :
2566 *IncomingArgZ, ~0u);
2567 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2570 if (OutgoingArg->isRegister()) {
2571 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2573 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, 4);
2574 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2576 MemOpChains.push_back(ArgStore);
2580 static bool canGuaranteeTCO(CallingConv::ID CC) {
2581 return CC == CallingConv::Fast;
2584 /// Return true if we might ever do TCO for calls with this calling convention.
2585 static bool mayTailCallThisCC(CallingConv::ID CC) {
2587 case CallingConv::C:
2590 return canGuaranteeTCO(CC);
2594 bool SITargetLowering::isEligibleForTailCallOptimization(
2595 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2596 const SmallVectorImpl<ISD::OutputArg> &Outs,
2597 const SmallVectorImpl<SDValue> &OutVals,
2598 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2599 if (!mayTailCallThisCC(CalleeCC))
2602 MachineFunction &MF = DAG.getMachineFunction();
2603 const Function &CallerF = MF.getFunction();
2604 CallingConv::ID CallerCC = CallerF.getCallingConv();
2605 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2606 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2608 // Kernels aren't callable, and don't have a live in return address so it
2609 // doesn't make sense to do a tail call with entry functions.
2610 if (!CallerPreserved)
2613 bool CCMatch = CallerCC == CalleeCC;
2615 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2616 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2621 // TODO: Can we handle var args?
2625 for (const Argument &Arg : CallerF.args()) {
2626 if (Arg.hasByValAttr())
2630 LLVMContext &Ctx = *DAG.getContext();
2632 // Check that the call results are passed in the same way.
2633 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2634 CCAssignFnForCall(CalleeCC, IsVarArg),
2635 CCAssignFnForCall(CallerCC, IsVarArg)))
2638 // The callee has to preserve all registers the caller needs to preserve.
2640 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2641 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2645 // Nothing more to check if the callee is taking no arguments.
2649 SmallVector<CCValAssign, 16> ArgLocs;
2650 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2652 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2654 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
2655 // If the stack arguments for this call do not fit into our own save area then
2656 // the call cannot be made tail.
2657 // TODO: Is this really necessary?
2658 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2661 const MachineRegisterInfo &MRI = MF.getRegInfo();
2662 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
2665 bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2666 if (!CI->isTailCall())
2669 const Function *ParentFn = CI->getParent()->getParent();
2670 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
2675 // The wave scratch offset register is used as the global base pointer.
2676 SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
2677 SmallVectorImpl<SDValue> &InVals) const {
2678 SelectionDAG &DAG = CLI.DAG;
2679 const SDLoc &DL = CLI.DL;
2680 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2681 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2682 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2683 SDValue Chain = CLI.Chain;
2684 SDValue Callee = CLI.Callee;
2685 bool &IsTailCall = CLI.IsTailCall;
2686 CallingConv::ID CallConv = CLI.CallConv;
2687 bool IsVarArg = CLI.IsVarArg;
2688 bool IsSibCall = false;
2689 bool IsThisReturn = false;
2690 MachineFunction &MF = DAG.getMachineFunction();
2692 if (Callee.isUndef() || isNullConstant(Callee)) {
2693 if (!CLI.IsTailCall) {
2694 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
2695 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
2702 return lowerUnhandledCall(CLI, InVals,
2703 "unsupported call to variadic function ");
2706 if (!CLI.CS.getInstruction())
2707 report_fatal_error("unsupported libcall legalization");
2709 if (!CLI.CS.getCalledFunction()) {
2710 return lowerUnhandledCall(CLI, InVals,
2711 "unsupported indirect call to function ");
2714 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
2715 return lowerUnhandledCall(CLI, InVals,
2716 "unsupported required tail call to function ");
2719 if (AMDGPU::isShader(MF.getFunction().getCallingConv())) {
2720 // Note the issue is with the CC of the calling function, not of the call
2722 return lowerUnhandledCall(CLI, InVals,
2723 "unsupported call from graphics shader of function ");
2727 IsTailCall = isEligibleForTailCallOptimization(
2728 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
2729 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) {
2730 report_fatal_error("failed to perform tail call elimination on a call "
2731 "site marked musttail");
2734 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2736 // A sibling call is one where we're under the usual C ABI and not planning
2737 // to change that but can still do a tail call:
2738 if (!TailCallOpt && IsTailCall)
2745 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2747 // Analyze operands of the call, assigning locations to each operand.
2748 SmallVector<CCValAssign, 16> ArgLocs;
2749 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2750 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
2752 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
2754 // Get a count of how many bytes are to be pushed on the stack.
2755 unsigned NumBytes = CCInfo.getNextStackOffset();
2758 // Since we're not changing the ABI to make this a tail call, the memory
2759 // operands are already available in the caller's incoming argument space.
2763 // FPDiff is the byte offset of the call's argument area from the callee's.
2764 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2765 // by this amount for a tail call. In a sibling call it must be 0 because the
2766 // caller will deallocate the entire stack and the callee still expects its
2767 // arguments to begin at SP+0. Completely unused for non-tail calls.
2769 MachineFrameInfo &MFI = MF.getFrameInfo();
2770 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2772 // Adjust the stack pointer for the new arguments...
2773 // These operations are automatically eliminated by the prolog/epilog pass
2775 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
2777 SmallVector<SDValue, 4> CopyFromChains;
2779 // In the HSA case, this should be an identity copy.
2780 SDValue ScratchRSrcReg
2781 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
2782 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
2783 CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
2784 Chain = DAG.getTokenFactor(DL, CopyFromChains);
2787 SmallVector<SDValue, 8> MemOpChains;
2788 MVT PtrVT = MVT::i32;
2790 // Walk the register/memloc assignments, inserting copies/loads.
2791 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2792 CCValAssign &VA = ArgLocs[i];
2793 SDValue Arg = OutVals[i];
2795 // Promote the value if needed.
2796 switch (VA.getLocInfo()) {
2797 case CCValAssign::Full:
2799 case CCValAssign::BCvt:
2800 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2802 case CCValAssign::ZExt:
2803 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2805 case CCValAssign::SExt:
2806 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2808 case CCValAssign::AExt:
2809 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2811 case CCValAssign::FPExt:
2812 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2815 llvm_unreachable("Unknown loc info!");
2818 if (VA.isRegLoc()) {
2819 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2821 assert(VA.isMemLoc());
2824 MachinePointerInfo DstInfo;
2826 unsigned LocMemOffset = VA.getLocMemOffset();
2827 int32_t Offset = LocMemOffset;
2829 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
2830 MaybeAlign Alignment;
2833 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2834 unsigned OpSize = Flags.isByVal() ?
2835 Flags.getByValSize() : VA.getValVT().getStoreSize();
2837 // FIXME: We can have better than the minimum byval required alignment.
2840 ? MaybeAlign(Flags.getByValAlign())
2841 : commonAlignment(Subtarget->getStackAlignment(), Offset);
2843 Offset = Offset + FPDiff;
2844 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
2846 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2847 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
2849 // Make sure any stack arguments overlapping with where we're storing
2850 // are loaded before this eventual operation. Otherwise they'll be
2853 // FIXME: Why is this really necessary? This seems to just result in a
2854 // lot of code to copy the stack and write them back to the same
2855 // locations, which are supposed to be immutable?
2856 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
2859 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
2861 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset);
2864 if (Outs[i].Flags.isByVal()) {
2866 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
2867 SDValue Cpy = DAG.getMemcpy(
2868 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2869 /*isVol = */ false, /*AlwaysInline = */ true,
2870 /*isTailCall = */ false, DstInfo,
2871 MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS));
2873 MemOpChains.push_back(Cpy);
2875 SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo,
2876 Alignment ? Alignment->value() : 0);
2877 MemOpChains.push_back(Store);
2882 // Copy special input registers after user input arguments.
2883 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
2885 if (!MemOpChains.empty())
2886 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2888 // Build a sequence of copy-to-reg nodes chained together with token chain
2889 // and flag operands which copy the outgoing args into the appropriate regs.
2891 for (auto &RegToPass : RegsToPass) {
2892 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
2893 RegToPass.second, InFlag);
2894 InFlag = Chain.getValue(1);
2898 SDValue PhysReturnAddrReg;
2900 // Since the return is being combined with the call, we need to pass on the
2903 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2904 SDValue ReturnAddrReg = CreateLiveInRegister(
2905 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2907 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2909 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
2910 InFlag = Chain.getValue(1);
2913 // We don't usually want to end the call-sequence here because we would tidy
2914 // the frame up *after* the call, however in the ABI-changing tail-call case
2915 // we've carefully laid out the parameters so that when sp is reset they'll be
2916 // in the correct location.
2917 if (IsTailCall && !IsSibCall) {
2918 Chain = DAG.getCALLSEQ_END(Chain,
2919 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
2920 DAG.getTargetConstant(0, DL, MVT::i32),
2922 InFlag = Chain.getValue(1);
2925 std::vector<SDValue> Ops;
2926 Ops.push_back(Chain);
2927 Ops.push_back(Callee);
2928 // Add a redundant copy of the callee global which will not be legalized, as
2929 // we need direct access to the callee later.
2930 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Callee);
2931 const GlobalValue *GV = GSD->getGlobal();
2932 Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
2935 // Each tail call may have to adjust the stack by a different amount, so
2936 // this information must travel along with the operation for eventual
2937 // consumption by emitEpilogue.
2938 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2940 Ops.push_back(PhysReturnAddrReg);
2943 // Add argument registers to the end of the list so that they are known live
2945 for (auto &RegToPass : RegsToPass) {
2946 Ops.push_back(DAG.getRegister(RegToPass.first,
2947 RegToPass.second.getValueType()));
2950 // Add a register mask operand representing the call-preserved registers.
2952 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
2953 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2954 assert(Mask && "Missing call preserved mask for calling convention");
2955 Ops.push_back(DAG.getRegisterMask(Mask));
2957 if (InFlag.getNode())
2958 Ops.push_back(InFlag);
2960 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2962 // If we're doing a tall call, use a TC_RETURN here rather than an
2963 // actual call instruction.
2965 MFI.setHasTailCall();
2966 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
2969 // Returns a chain and a flag for retval copy to use.
2970 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
2971 Chain = Call.getValue(0);
2972 InFlag = Call.getValue(1);
2974 uint64_t CalleePopBytes = NumBytes;
2975 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
2976 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
2979 InFlag = Chain.getValue(1);
2981 // Handle result values, copying them out of physregs into vregs that we
2983 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2984 InVals, IsThisReturn,
2985 IsThisReturn ? OutVals[0] : SDValue());
2988 Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
2989 const MachineFunction &MF) const {
2990 Register Reg = StringSwitch<Register>(RegName)
2991 .Case("m0", AMDGPU::M0)
2992 .Case("exec", AMDGPU::EXEC)
2993 .Case("exec_lo", AMDGPU::EXEC_LO)
2994 .Case("exec_hi", AMDGPU::EXEC_HI)
2995 .Case("flat_scratch", AMDGPU::FLAT_SCR)
2996 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
2997 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
2998 .Default(Register());
3000 if (Reg == AMDGPU::NoRegister) {
3001 report_fatal_error(Twine("invalid register name \""
3002 + StringRef(RegName) + "\"."));
3006 if (!Subtarget->hasFlatScrRegister() &&
3007 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
3008 report_fatal_error(Twine("invalid register \""
3009 + StringRef(RegName) + "\" for subtarget."));
3014 case AMDGPU::EXEC_LO:
3015 case AMDGPU::EXEC_HI:
3016 case AMDGPU::FLAT_SCR_LO:
3017 case AMDGPU::FLAT_SCR_HI:
3018 if (VT.getSizeInBits() == 32)
3022 case AMDGPU::FLAT_SCR:
3023 if (VT.getSizeInBits() == 64)
3027 llvm_unreachable("missing register type checking");
3030 report_fatal_error(Twine("invalid type for register \""
3031 + StringRef(RegName) + "\"."));
3034 // If kill is not the last instruction, split the block so kill is always a
3035 // proper terminator.
3036 MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
3037 MachineBasicBlock *BB) const {
3038 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3040 MachineBasicBlock::iterator SplitPoint(&MI);
3043 if (SplitPoint == BB->end()) {
3044 // Don't bother with a new block.
3045 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3049 MachineFunction *MF = BB->getParent();
3050 MachineBasicBlock *SplitBB
3051 = MF->CreateMachineBasicBlock(BB->getBasicBlock());
3053 MF->insert(++MachineFunction::iterator(BB), SplitBB);
3054 SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
3056 SplitBB->transferSuccessorsAndUpdatePHIs(BB);
3057 BB->addSuccessor(SplitBB);
3059 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3063 // Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3064 // \p MI will be the only instruction in the loop body block. Otherwise, it will
3065 // be the first instruction in the remainder block.
3067 /// \returns { LoopBody, Remainder }
3068 static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3069 splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
3070 MachineFunction *MF = MBB.getParent();
3071 MachineBasicBlock::iterator I(&MI);
3073 // To insert the loop we need to split the block. Move everything after this
3074 // point to a new block, and insert a new empty block between the two.
3075 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
3076 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3077 MachineFunction::iterator MBBI(MBB);
3080 MF->insert(MBBI, LoopBB);
3081 MF->insert(MBBI, RemainderBB);
3083 LoopBB->addSuccessor(LoopBB);
3084 LoopBB->addSuccessor(RemainderBB);
3086 // Move the rest of the block into a new block.
3087 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3090 auto Next = std::next(I);
3092 // Move instruction to loop body.
3093 LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3095 // Move the rest of the block.
3096 RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3098 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3101 MBB.addSuccessor(LoopBB);
3103 return std::make_pair(LoopBB, RemainderBB);
3106 /// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3107 void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
3108 MachineBasicBlock *MBB = MI.getParent();
3109 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3110 auto I = MI.getIterator();
3111 auto E = std::next(I);
3113 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3116 MIBundleBuilder Bundler(*MBB, I, E);
3117 finalizeBundle(*MBB, Bundler.begin());
3121 SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
3122 MachineBasicBlock *BB) const {
3123 const DebugLoc &DL = MI.getDebugLoc();
3125 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3127 MachineBasicBlock *LoopBB;
3128 MachineBasicBlock *RemainderBB;
3129 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3131 // Apparently kill flags are only valid if the def is in the same block?
3132 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3133 Src->setIsKill(false);
3135 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3137 MachineBasicBlock::iterator I = LoopBB->end();
3139 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3140 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
3142 // Clear TRAP_STS.MEM_VIOL
3143 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3145 .addImm(EncodedReg);
3147 bundleInstWithWaitcnt(MI);
3149 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3151 // Load and check TRAP_STS.MEM_VIOL
3152 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3153 .addImm(EncodedReg);
3155 // FIXME: Do we need to use an isel pseudo that may clobber scc?
3156 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3157 .addReg(Reg, RegState::Kill)
3159 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3165 // Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3166 // wavefront. If the value is uniform and just happens to be in a VGPR, this
3167 // will only do one iteration. In the worst case, this will loop 64 times.
3169 // TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3170 static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
3171 const SIInstrInfo *TII,
3172 MachineRegisterInfo &MRI,
3173 MachineBasicBlock &OrigBB,
3174 MachineBasicBlock &LoopBB,
3176 const MachineOperand &IdxReg,
3180 unsigned InitSaveExecReg,
3183 bool IsIndirectSrc) {
3184 MachineFunction *MF = OrigBB.getParent();
3185 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3186 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3187 MachineBasicBlock::iterator I = LoopBB.begin();
3189 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3190 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3191 Register NewExec = MRI.createVirtualRegister(BoolRC);
3192 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3193 Register CondReg = MRI.createVirtualRegister(BoolRC);
3195 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3201 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3202 .addReg(InitSaveExecReg)
3207 // Read the next variant <- also loop target.
3208 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3209 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
3211 // Compare the just read M0 value to all possible Idx values.
3212 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3213 .addReg(CurrentIdxReg)
3214 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
3216 // Update EXEC, save the original EXEC value to VCC.
3217 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3218 : AMDGPU::S_AND_SAVEEXEC_B64),
3220 .addReg(CondReg, RegState::Kill);
3222 MRI.setSimpleHint(NewExec, CondReg);
3224 if (UseGPRIdxMode) {
3227 IdxReg = CurrentIdxReg;
3229 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3230 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
3231 .addReg(CurrentIdxReg, RegState::Kill)
3234 unsigned IdxMode = IsIndirectSrc ?
3235 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
3236 MachineInstr *SetOn =
3237 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3238 .addReg(IdxReg, RegState::Kill)
3240 SetOn->getOperand(3).setIsUndef();
3242 // Move index from VCC into M0
3244 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3245 .addReg(CurrentIdxReg, RegState::Kill);
3247 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3248 .addReg(CurrentIdxReg, RegState::Kill)
3253 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3254 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3255 MachineInstr *InsertPt =
3256 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3257 : AMDGPU::S_XOR_B64_term), Exec)
3261 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3264 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3265 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3268 return InsertPt->getIterator();
3271 // This has slightly sub-optimal regalloc when the source vector is killed by
3272 // the read. The register allocator does not understand that the kill is
3273 // per-workitem, so is kept alive for the whole loop so we end up not re-using a
3274 // subregister from it, using 1 more VGPR than necessary. This was saved when
3275 // this was expanded after register allocation.
3276 static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
3277 MachineBasicBlock &MBB,
3279 unsigned InitResultReg,
3283 bool IsIndirectSrc) {
3284 MachineFunction *MF = MBB.getParent();
3285 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3286 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3287 MachineRegisterInfo &MRI = MF->getRegInfo();
3288 const DebugLoc &DL = MI.getDebugLoc();
3289 MachineBasicBlock::iterator I(&MI);
3291 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3292 Register DstReg = MI.getOperand(0).getReg();
3293 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3294 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3295 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3296 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3298 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3300 // Save the EXEC mask
3301 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3304 MachineBasicBlock *LoopBB;
3305 MachineBasicBlock *RemainderBB;
3306 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3308 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3310 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3311 InitResultReg, DstReg, PhiReg, TmpExec,
3312 Offset, UseGPRIdxMode, IsIndirectSrc);
3314 MachineBasicBlock::iterator First = RemainderBB->begin();
3315 BuildMI(*RemainderBB, First, DL, TII->get(MovExecOpc), Exec)
3321 // Returns subreg index, offset
3322 static std::pair<unsigned, int>
3323 computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3324 const TargetRegisterClass *SuperRC,
3327 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3329 // Skip out of bounds offsets, or else we would end up using an undefined
3331 if (Offset >= NumElts || Offset < 0)
3332 return std::make_pair(AMDGPU::sub0, Offset);
3334 return std::make_pair(AMDGPU::sub0 + Offset, 0);
3337 // Return true if the index is an SGPR and was set.
3338 static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII,
3339 MachineRegisterInfo &MRI,
3343 bool IsIndirectSrc) {
3344 MachineBasicBlock *MBB = MI.getParent();
3345 const DebugLoc &DL = MI.getDebugLoc();
3346 MachineBasicBlock::iterator I(&MI);
3348 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3349 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3351 assert(Idx->getReg() != AMDGPU::NoRegister);
3353 if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
3356 if (UseGPRIdxMode) {
3357 unsigned IdxMode = IsIndirectSrc ?
3358 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
3360 MachineInstr *SetOn =
3361 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3365 SetOn->getOperand(3).setIsUndef();
3367 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3368 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3371 MachineInstr *SetOn =
3372 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3373 .addReg(Tmp, RegState::Kill)
3376 SetOn->getOperand(3).setIsUndef();
3383 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3386 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3394 // Control flow needs to be inserted if indexing with a VGPR.
3395 static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3396 MachineBasicBlock &MBB,
3397 const GCNSubtarget &ST) {
3398 const SIInstrInfo *TII = ST.getInstrInfo();
3399 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3400 MachineFunction *MF = MBB.getParent();
3401 MachineRegisterInfo &MRI = MF->getRegInfo();
3403 Register Dst = MI.getOperand(0).getReg();
3404 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3405 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3407 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3410 std::tie(SubReg, Offset)
3411 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3413 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3415 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, true)) {
3416 MachineBasicBlock::iterator I(&MI);
3417 const DebugLoc &DL = MI.getDebugLoc();
3419 if (UseGPRIdxMode) {
3420 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3421 // to avoid interfering with other uses, so probably requires a new
3422 // optimization pass.
3423 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3424 .addReg(SrcReg, RegState::Undef, SubReg)
3425 .addReg(SrcReg, RegState::Implicit)
3426 .addReg(AMDGPU::M0, RegState::Implicit);
3427 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3429 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3430 .addReg(SrcReg, RegState::Undef, SubReg)
3431 .addReg(SrcReg, RegState::Implicit);
3434 MI.eraseFromParent();
3439 const DebugLoc &DL = MI.getDebugLoc();
3440 MachineBasicBlock::iterator I(&MI);
3442 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3443 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3445 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3447 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3448 Offset, UseGPRIdxMode, true);
3449 MachineBasicBlock *LoopBB = InsPt->getParent();
3451 if (UseGPRIdxMode) {
3452 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3453 .addReg(SrcReg, RegState::Undef, SubReg)
3454 .addReg(SrcReg, RegState::Implicit)
3455 .addReg(AMDGPU::M0, RegState::Implicit);
3456 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3458 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3459 .addReg(SrcReg, RegState::Undef, SubReg)
3460 .addReg(SrcReg, RegState::Implicit);
3463 MI.eraseFromParent();
3468 static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
3469 const TargetRegisterClass *VecRC) {
3470 switch (TRI.getRegSizeInBits(*VecRC)) {
3472 return AMDGPU::V_MOVRELD_B32_V1;
3474 return AMDGPU::V_MOVRELD_B32_V2;
3475 case 128: // 16 bytes
3476 return AMDGPU::V_MOVRELD_B32_V4;
3477 case 256: // 32 bytes
3478 return AMDGPU::V_MOVRELD_B32_V8;
3479 case 512: // 64 bytes
3480 return AMDGPU::V_MOVRELD_B32_V16;
3482 llvm_unreachable("unsupported size for MOVRELD pseudos");
3486 static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3487 MachineBasicBlock &MBB,
3488 const GCNSubtarget &ST) {
3489 const SIInstrInfo *TII = ST.getInstrInfo();
3490 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3491 MachineFunction *MF = MBB.getParent();
3492 MachineRegisterInfo &MRI = MF->getRegInfo();
3494 Register Dst = MI.getOperand(0).getReg();
3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3496 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3497 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3498 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3499 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3501 // This can be an immediate, but will be folded later.
3502 assert(Val->getReg());
3505 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3508 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3510 if (Idx->getReg() == AMDGPU::NoRegister) {
3511 MachineBasicBlock::iterator I(&MI);
3512 const DebugLoc &DL = MI.getDebugLoc();
3514 assert(Offset == 0);
3516 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3521 MI.eraseFromParent();
3525 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
3526 MachineBasicBlock::iterator I(&MI);
3527 const DebugLoc &DL = MI.getDebugLoc();
3529 if (UseGPRIdxMode) {
3530 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3531 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3533 .addReg(Dst, RegState::ImplicitDefine)
3534 .addReg(SrcVec->getReg(), RegState::Implicit)
3535 .addReg(AMDGPU::M0, RegState::Implicit);
3537 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3539 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3541 BuildMI(MBB, I, DL, MovRelDesc)
3542 .addReg(Dst, RegState::Define)
3543 .addReg(SrcVec->getReg())
3545 .addImm(SubReg - AMDGPU::sub0);
3548 MI.eraseFromParent();
3553 MRI.clearKillFlags(Val->getReg());
3555 const DebugLoc &DL = MI.getDebugLoc();
3557 Register PhiReg = MRI.createVirtualRegister(VecRC);
3559 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3560 Offset, UseGPRIdxMode, false);
3561 MachineBasicBlock *LoopBB = InsPt->getParent();
3563 if (UseGPRIdxMode) {
3564 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3565 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
3567 .addReg(Dst, RegState::ImplicitDefine)
3568 .addReg(PhiReg, RegState::Implicit)
3569 .addReg(AMDGPU::M0, RegState::Implicit);
3570 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3572 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3574 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
3575 .addReg(Dst, RegState::Define)
3578 .addImm(SubReg - AMDGPU::sub0);
3581 MI.eraseFromParent();
3586 MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3587 MachineInstr &MI, MachineBasicBlock *BB) const {
3589 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3590 MachineFunction *MF = BB->getParent();
3591 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3593 if (TII->isMIMG(MI)) {
3594 if (MI.memoperands_empty() && MI.mayLoadOrStore()) {
3595 report_fatal_error("missing mem operand from MIMG instruction");
3597 // Add a memoperand for mimg instructions so that they aren't assumed to
3598 // be ordered memory instuctions.
3603 switch (MI.getOpcode()) {
3604 case AMDGPU::S_ADD_U64_PSEUDO:
3605 case AMDGPU::S_SUB_U64_PSEUDO: {
3606 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3607 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3608 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3609 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3610 const DebugLoc &DL = MI.getDebugLoc();
3612 MachineOperand &Dest = MI.getOperand(0);
3613 MachineOperand &Src0 = MI.getOperand(1);
3614 MachineOperand &Src1 = MI.getOperand(2);
3616 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3617 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3619 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3620 Src0, BoolRC, AMDGPU::sub0,
3621 &AMDGPU::SReg_32RegClass);
3622 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3623 Src0, BoolRC, AMDGPU::sub1,
3624 &AMDGPU::SReg_32RegClass);
3626 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3627 Src1, BoolRC, AMDGPU::sub0,
3628 &AMDGPU::SReg_32RegClass);
3629 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3630 Src1, BoolRC, AMDGPU::sub1,
3631 &AMDGPU::SReg_32RegClass);
3633 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
3635 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3636 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3637 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3640 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3643 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3645 .addImm(AMDGPU::sub0)
3647 .addImm(AMDGPU::sub1);
3648 MI.eraseFromParent();
3651 case AMDGPU::SI_INIT_M0: {
3652 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
3653 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3654 .add(MI.getOperand(0));
3655 MI.eraseFromParent();
3658 case AMDGPU::SI_INIT_EXEC:
3659 // This should be before all vector instructions.
3660 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3662 .addImm(MI.getOperand(0).getImm());
3663 MI.eraseFromParent();
3666 case AMDGPU::SI_INIT_EXEC_LO:
3667 // This should be before all vector instructions.
3668 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3670 .addImm(MI.getOperand(0).getImm());
3671 MI.eraseFromParent();
3674 case AMDGPU::SI_INIT_EXEC_FROM_INPUT: {
3675 // Extract the thread count from an SGPR input and set EXEC accordingly.
3676 // Since BFM can't shift by 64, handle that case with CMP + CMOV.
3678 // S_BFE_U32 count, input, {shift, 7}
3679 // S_BFM_B64 exec, count, 0
3680 // S_CMP_EQ_U32 count, 64
3681 // S_CMOV_B64 exec, -1
3682 MachineInstr *FirstMI = &*BB->begin();
3683 MachineRegisterInfo &MRI = MF->getRegInfo();
3684 Register InputReg = MI.getOperand(0).getReg();
3685 Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3688 // Move the COPY of the input reg to the beginning, so that we can use it.
3689 for (auto I = BB->begin(); I != &MI; I++) {
3690 if (I->getOpcode() != TargetOpcode::COPY ||
3691 I->getOperand(0).getReg() != InputReg)
3695 FirstMI = &*++BB->begin();
3697 I->removeFromParent();
3698 BB->insert(FirstMI, &*I);
3706 // This should be before all vector instructions.
3707 unsigned Mask = (getSubtarget()->getWavefrontSize() << 1) - 1;
3708 bool isWave32 = getSubtarget()->isWave32();
3709 unsigned Exec = isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3710 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3712 .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
3713 BuildMI(*BB, FirstMI, DebugLoc(),
3714 TII->get(isWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
3718 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
3719 .addReg(CountReg, RegState::Kill)
3720 .addImm(getSubtarget()->getWavefrontSize());
3721 BuildMI(*BB, FirstMI, DebugLoc(),
3722 TII->get(isWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
3725 MI.eraseFromParent();
3729 case AMDGPU::GET_GROUPSTATICSIZE: {
3730 assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||
3731 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL);
3732 DebugLoc DL = MI.getDebugLoc();
3733 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3734 .add(MI.getOperand(0))
3735 .addImm(MFI->getLDSSize());
3736 MI.eraseFromParent();
3739 case AMDGPU::SI_INDIRECT_SRC_V1:
3740 case AMDGPU::SI_INDIRECT_SRC_V2:
3741 case AMDGPU::SI_INDIRECT_SRC_V4:
3742 case AMDGPU::SI_INDIRECT_SRC_V8:
3743 case AMDGPU::SI_INDIRECT_SRC_V16:
3744 return emitIndirectSrc(MI, *BB, *getSubtarget());
3745 case AMDGPU::SI_INDIRECT_DST_V1:
3746 case AMDGPU::SI_INDIRECT_DST_V2:
3747 case AMDGPU::SI_INDIRECT_DST_V4:
3748 case AMDGPU::SI_INDIRECT_DST_V8:
3749 case AMDGPU::SI_INDIRECT_DST_V16:
3750 return emitIndirectDst(MI, *BB, *getSubtarget());
3751 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
3752 case AMDGPU::SI_KILL_I1_PSEUDO:
3753 return splitKillBlock(MI, BB);
3754 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
3755 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3756 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3757 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3759 Register Dst = MI.getOperand(0).getReg();
3760 Register Src0 = MI.getOperand(1).getReg();
3761 Register Src1 = MI.getOperand(2).getReg();
3762 const DebugLoc &DL = MI.getDebugLoc();
3763 Register SrcCond = MI.getOperand(3).getReg();
3765 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3766 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3767 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3768 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
3770 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3774 .addReg(Src0, 0, AMDGPU::sub0)
3776 .addReg(Src1, 0, AMDGPU::sub0)
3777 .addReg(SrcCondCopy);
3778 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3780 .addReg(Src0, 0, AMDGPU::sub1)
3782 .addReg(Src1, 0, AMDGPU::sub1)
3783 .addReg(SrcCondCopy);
3785 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3787 .addImm(AMDGPU::sub0)
3789 .addImm(AMDGPU::sub1);
3790 MI.eraseFromParent();
3793 case AMDGPU::SI_BR_UNDEF: {
3794 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3795 const DebugLoc &DL = MI.getDebugLoc();
3796 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3797 .add(MI.getOperand(0));
3798 Br->getOperand(1).setIsUndef(true); // read undef SCC
3799 MI.eraseFromParent();
3802 case AMDGPU::ADJCALLSTACKUP:
3803 case AMDGPU::ADJCALLSTACKDOWN: {
3804 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
3805 MachineInstrBuilder MIB(*MF, &MI);
3807 // Add an implicit use of the frame offset reg to prevent the restore copy
3808 // inserted after the call from being reorderd after stack operations in the
3809 // the caller's frame.
3810 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
3811 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
3812 .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
3815 case AMDGPU::SI_CALL_ISEL: {
3816 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3817 const DebugLoc &DL = MI.getDebugLoc();
3819 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
3821 MachineInstrBuilder MIB;
3822 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
3824 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3825 MIB.add(MI.getOperand(I));
3827 MIB.cloneMemRefs(MI);
3828 MI.eraseFromParent();
3831 case AMDGPU::V_ADD_I32_e32:
3832 case AMDGPU::V_SUB_I32_e32:
3833 case AMDGPU::V_SUBREV_I32_e32: {
3834 // TODO: Define distinct V_*_I32_Pseudo instructions instead.
3835 const DebugLoc &DL = MI.getDebugLoc();
3836 unsigned Opc = MI.getOpcode();
3838 bool NeedClampOperand = false;
3839 if (TII->pseudoToMCOpcode(Opc) == -1) {
3840 Opc = AMDGPU::getVOPe64(Opc);
3841 NeedClampOperand = true;
3844 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
3845 if (TII->isVOP3(*I)) {
3846 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3847 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3848 I.addReg(TRI->getVCC(), RegState::Define);
3850 I.add(MI.getOperand(1))
3851 .add(MI.getOperand(2));
3852 if (NeedClampOperand)
3853 I.addImm(0); // clamp bit for e64 encoding
3855 TII->legalizeOperands(*I);
3857 MI.eraseFromParent();
3860 case AMDGPU::DS_GWS_INIT:
3861 case AMDGPU::DS_GWS_SEMA_V:
3862 case AMDGPU::DS_GWS_SEMA_BR:
3863 case AMDGPU::DS_GWS_SEMA_P:
3864 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
3865 case AMDGPU::DS_GWS_BARRIER:
3866 // A s_waitcnt 0 is required to be the instruction immediately following.
3867 if (getSubtarget()->hasGWSAutoReplay()) {
3868 bundleInstWithWaitcnt(MI);
3872 return emitGWSMemViolTestLoop(MI, BB);
3874 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
3878 bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
3879 return isTypeLegal(VT.getScalarType());
3882 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
3883 // This currently forces unfolding various combinations of fsub into fma with
3884 // free fneg'd operands. As long as we have fast FMA (controlled by
3885 // isFMAFasterThanFMulAndFAdd), we should perform these.
3887 // When fma is quarter rate, for f64 where add / sub are at best half rate,
3888 // most of these combines appear to be cycle neutral but save on instruction
3889 // count / code size.
3893 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
3895 if (!VT.isVector()) {
3898 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
3901 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
3902 // TODO: Should i16 be used always if legal? For now it would force VALU
3904 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
3907 // Answering this is somewhat tricky and depends on the specific device which
3908 // have different rates for fma or all f64 operations.
3910 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
3911 // regardless of which device (although the number of cycles differs between
3912 // devices), so it is always profitable for f64.
3914 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
3915 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
3916 // which we can always do even without fused FP ops since it returns the same
3917 // result as the separate operations and since it is always full
3918 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
3919 // however does not support denormals, so we do report fma as faster if we have
3920 // a fast fma device and require denormals.
3922 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3924 VT = VT.getScalarType();
3926 switch (VT.getSimpleVT().SimpleTy) {
3928 // This is as fast on some subtargets. However, we always have full rate f32
3929 // mad available which returns the same result as the separate operations
3930 // which we should prefer over fma. We can't use this if we want to support
3931 // denormals, so only report this in these cases.
3932 if (hasFP32Denormals(MF))
3933 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
3935 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
3936 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
3941 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
3949 bool SITargetLowering::isFMADLegalForFAddFSub(const SelectionDAG &DAG,
3950 const SDNode *N) const {
3951 // TODO: Check future ftz flag
3952 // v_mad_f32/v_mac_f32 do not support denormals.
3953 EVT VT = N->getValueType(0);
3955 return !hasFP32Denormals(DAG.getMachineFunction());
3956 if (VT == MVT::f16) {
3957 return Subtarget->hasMadF16() &&
3958 !hasFP64FP16Denormals(DAG.getMachineFunction());
3964 //===----------------------------------------------------------------------===//
3965 // Custom DAG Lowering Operations
3966 //===----------------------------------------------------------------------===//
3968 // Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3969 // wider vector type is legal.
3970 SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
3971 SelectionDAG &DAG) const {
3972 unsigned Opc = Op.getOpcode();
3973 EVT VT = Op.getValueType();
3974 assert(VT == MVT::v4f16);
3977 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
3980 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
3982 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
3985 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3988 // Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3989 // wider vector type is legal.
3990 SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
3991 SelectionDAG &DAG) const {
3992 unsigned Opc = Op.getOpcode();
3993 EVT VT = Op.getValueType();
3994 assert(VT == MVT::v4i16 || VT == MVT::v4f16);
3997 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3999 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4003 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
4005 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
4008 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4011 SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
4012 SelectionDAG &DAG) const {
4013 unsigned Opc = Op.getOpcode();
4014 EVT VT = Op.getValueType();
4015 assert(VT == MVT::v4i16 || VT == MVT::v4f16);
4018 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4020 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4022 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
4026 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
4028 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
4031 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4035 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4036 switch (Op.getOpcode()) {
4037 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
4038 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4039 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4041 SDValue Result = LowerLOAD(Op, DAG);
4042 assert((!Result.getNode() ||
4043 Result.getNode()->getNumValues() == 2) &&
4044 "Load should return a value and a chain");
4050 return LowerTrig(Op, DAG);
4051 case ISD::SELECT: return LowerSELECT(Op, DAG);
4052 case ISD::FDIV: return LowerFDIV(Op, DAG);
4053 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
4054 case ISD::STORE: return LowerSTORE(Op, DAG);
4055 case ISD::GlobalAddress: {
4056 MachineFunction &MF = DAG.getMachineFunction();
4057 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
4058 return LowerGlobalAddress(MFI, Op, DAG);
4060 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4061 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4062 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4063 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4064 case ISD::INSERT_SUBVECTOR:
4065 return lowerINSERT_SUBVECTOR(Op, DAG);
4066 case ISD::INSERT_VECTOR_ELT:
4067 return lowerINSERT_VECTOR_ELT(Op, DAG);
4068 case ISD::EXTRACT_VECTOR_ELT:
4069 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4070 case ISD::VECTOR_SHUFFLE:
4071 return lowerVECTOR_SHUFFLE(Op, DAG);
4072 case ISD::BUILD_VECTOR:
4073 return lowerBUILD_VECTOR(Op, DAG);
4075 return lowerFP_ROUND(Op, DAG);
4077 return lowerTRAP(Op, DAG);
4078 case ISD::DEBUGTRAP:
4079 return lowerDEBUGTRAP(Op, DAG);
4082 case ISD::FCANONICALIZE:
4083 return splitUnaryVectorOp(Op, DAG);
4086 return lowerFMINNUM_FMAXNUM(Op, DAG);
4088 return splitTernaryVectorOp(Op, DAG);
4101 case ISD::FMINNUM_IEEE:
4102 case ISD::FMAXNUM_IEEE:
4103 return splitBinaryVectorOp(Op, DAG);
4108 static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
4110 SelectionDAG &DAG, bool Unpacked) {
4111 if (!LoadVT.isVector())
4114 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4115 // Truncate to v2i16/v4i16.
4116 EVT IntLoadVT = LoadVT.changeTypeToInteger();
4118 // Workaround legalizer not scalarizing truncate after vector op
4119 // legalization byt not creating intermediate vector trunc.
4120 SmallVector<SDValue, 4> Elts;
4121 DAG.ExtractVectorElements(Result, Elts);
4122 for (SDValue &Elt : Elts)
4123 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4125 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4127 // Bitcast to original type (v2f16/v4f16).
4128 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4131 // Cast back to the original packed type.
4132 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4135 SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4138 ArrayRef<SDValue> Ops,
4139 bool IsIntrinsic) const {
4142 bool Unpacked = Subtarget->hasUnpackedD16VMem();
4143 EVT LoadVT = M->getValueType(0);
4145 EVT EquivLoadVT = LoadVT;
4146 if (Unpacked && LoadVT.isVector()) {
4147 EquivLoadVT = LoadVT.isVector() ?
4148 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
4149 LoadVT.getVectorNumElements()) : LoadVT;
4152 // Change from v4f16/v2f16 to EquivLoadVT.
4153 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4156 = DAG.getMemIntrinsicNode(
4157 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4158 VTList, Ops, M->getMemoryVT(),
4159 M->getMemOperand());
4160 if (!Unpacked) // Just adjusted the opcode.
4163 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4165 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4168 SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4170 ArrayRef<SDValue> Ops) const {
4172 EVT LoadVT = M->getValueType(0);
4173 EVT EltType = LoadVT.getScalarType();
4174 EVT IntVT = LoadVT.changeTypeToInteger();
4176 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4179 IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD;
4182 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4185 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4186 if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4187 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4189 if (isTypeLegal(LoadVT)) {
4190 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4191 M->getMemOperand(), DAG);
4194 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4195 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4196 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4197 M->getMemOperand(), DAG);
4198 return DAG.getMergeValues(
4199 {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4203 static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
4204 SDNode *N, SelectionDAG &DAG) {
4205 EVT VT = N->getValueType(0);
4206 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4207 int CondCode = CD->getSExtValue();
4208 if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
4209 CondCode > ICmpInst::Predicate::LAST_ICMP_PREDICATE)
4210 return DAG.getUNDEF(VT);
4212 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4214 SDValue LHS = N->getOperand(1);
4215 SDValue RHS = N->getOperand(2);
4219 EVT CmpVT = LHS.getValueType();
4220 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4221 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4222 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4223 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4224 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4227 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4229 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4230 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4232 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4233 DAG.getCondCode(CCOpcode));
4234 if (VT.bitsEq(CCVT))
4236 return DAG.getZExtOrTrunc(SetCC, DL, VT);
4239 static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
4240 SDNode *N, SelectionDAG &DAG) {
4241 EVT VT = N->getValueType(0);
4242 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4244 int CondCode = CD->getSExtValue();
4245 if (CondCode < FCmpInst::Predicate::FIRST_FCMP_PREDICATE ||
4246 CondCode > FCmpInst::Predicate::LAST_FCMP_PREDICATE) {
4247 return DAG.getUNDEF(VT);
4250 SDValue Src0 = N->getOperand(1);
4251 SDValue Src1 = N->getOperand(2);
4252 EVT CmpVT = Src0.getValueType();
4255 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4256 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4257 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4260 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4261 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4262 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4263 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4264 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4265 Src1, DAG.getCondCode(CCOpcode));
4266 if (VT.bitsEq(CCVT))
4268 return DAG.getZExtOrTrunc(SetCC, SL, VT);
4271 void SITargetLowering::ReplaceNodeResults(SDNode *N,
4272 SmallVectorImpl<SDValue> &Results,
4273 SelectionDAG &DAG) const {
4274 switch (N->getOpcode()) {
4275 case ISD::INSERT_VECTOR_ELT: {
4276 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4277 Results.push_back(Res);
4280 case ISD::EXTRACT_VECTOR_ELT: {
4281 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4282 Results.push_back(Res);
4285 case ISD::INTRINSIC_WO_CHAIN: {
4286 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4288 case Intrinsic::amdgcn_cvt_pkrtz: {
4289 SDValue Src0 = N->getOperand(1);
4290 SDValue Src1 = N->getOperand(2);
4292 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
4294 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4297 case Intrinsic::amdgcn_cvt_pknorm_i16:
4298 case Intrinsic::amdgcn_cvt_pknorm_u16:
4299 case Intrinsic::amdgcn_cvt_pk_i16:
4300 case Intrinsic::amdgcn_cvt_pk_u16: {
4301 SDValue Src0 = N->getOperand(1);
4302 SDValue Src1 = N->getOperand(2);
4306 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4307 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
4308 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4309 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
4310 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
4311 Opcode = AMDGPUISD::CVT_PK_I16_I32;
4313 Opcode = AMDGPUISD::CVT_PK_U16_U32;
4315 EVT VT = N->getValueType(0);
4316 if (isTypeLegal(VT))
4317 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4319 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
4320 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
4327 case ISD::INTRINSIC_W_CHAIN: {
4328 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
4329 if (Res.getOpcode() == ISD::MERGE_VALUES) {
4331 Results.push_back(Res.getOperand(0));
4332 Results.push_back(Res.getOperand(1));
4334 Results.push_back(Res);
4335 Results.push_back(Res.getValue(1));
4344 EVT VT = N->getValueType(0);
4345 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
4346 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
4347 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
4349 EVT SelectVT = NewVT;
4350 if (NewVT.bitsLT(MVT::i32)) {
4351 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4352 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
4353 SelectVT = MVT::i32;
4356 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
4357 N->getOperand(0), LHS, RHS);
4359 if (NewVT != SelectVT)
4360 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
4361 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
4365 if (N->getValueType(0) != MVT::v2f16)
4369 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4371 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
4373 DAG.getConstant(0x80008000, SL, MVT::i32));
4374 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4378 if (N->getValueType(0) != MVT::v2f16)
4382 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4384 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
4386 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
4387 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4395 /// Helper function for LowerBRCOND
4396 static SDNode *findUser(SDValue Value, unsigned Opcode) {
4398 SDNode *Parent = Value.getNode();
4399 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
4402 if (I.getUse().get() != Value)
4405 if (I->getOpcode() == Opcode)
4411 unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
4412 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4413 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
4414 case Intrinsic::amdgcn_if:
4415 return AMDGPUISD::IF;
4416 case Intrinsic::amdgcn_else:
4417 return AMDGPUISD::ELSE;
4418 case Intrinsic::amdgcn_loop:
4419 return AMDGPUISD::LOOP;
4420 case Intrinsic::amdgcn_end_cf:
4421 llvm_unreachable("should not occur");
4427 // break, if_break, else_break are all only used as inputs to loop, not
4428 // directly as branch conditions.
4432 bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
4433 const Triple &TT = getTargetMachine().getTargetTriple();
4434 return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4435 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4436 AMDGPU::shouldEmitConstantsToTextSection(TT);
4439 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
4440 // FIXME: Either avoid relying on address space here or change the default
4441 // address space for functions to avoid the explicit check.
4442 return (GV->getValueType()->isFunctionTy() ||
4443 GV->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
4444 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4445 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4446 !shouldEmitFixup(GV) &&
4447 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
4450 bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
4451 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
4454 /// This transforms the control flow intrinsics to get the branch destination as
4455 /// last parameter, also switches branch target with BR if the need arise
4456 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
4457 SelectionDAG &DAG) const {
4460 SDNode *Intr = BRCOND.getOperand(1).getNode();
4461 SDValue Target = BRCOND.getOperand(2);
4462 SDNode *BR = nullptr;
4463 SDNode *SetCC = nullptr;
4465 if (Intr->getOpcode() == ISD::SETCC) {
4466 // As long as we negate the condition everything is fine
4468 Intr = SetCC->getOperand(0).getNode();
4471 // Get the target from BR if we don't negate the condition
4472 BR = findUser(BRCOND, ISD::BR);
4473 Target = BR->getOperand(1);
4476 // FIXME: This changes the types of the intrinsics instead of introducing new
4477 // nodes with the correct types.
4478 // e.g. llvm.amdgcn.loop
4480 // eg: i1,ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3
4481 // => t9: ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3, BasicBlock:ch<bb1 0x7fee5286d088>
4483 unsigned CFNode = isCFIntrinsic(Intr);
4485 // This is a uniform branch so we don't need to legalize.
4489 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
4490 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
4493 (SetCC->getConstantOperandVal(1) == 1 &&
4494 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
4497 // operands of the new intrinsic call
4498 SmallVector<SDValue, 4> Ops;
4500 Ops.push_back(BRCOND.getOperand(0));
4502 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
4503 Ops.push_back(Target);
4505 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
4507 // build the new intrinsic call
4508 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
4513 BRCOND.getOperand(0)
4516 Result = DAG.getMergeValues(Ops, DL).getNode();
4520 // Give the branch instruction our target
4523 BRCOND.getOperand(2)
4525 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
4526 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
4527 BR = NewBR.getNode();
4530 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
4532 // Copy the intrinsic results to registers
4533 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
4534 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
4538 Chain = DAG.getCopyToReg(
4540 CopyToReg->getOperand(1),
4541 SDValue(Result, i - 1),
4544 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
4547 // Remove the old intrinsic from the chain
4548 DAG.ReplaceAllUsesOfValueWith(
4549 SDValue(Intr, Intr->getNumValues() - 1),
4550 Intr->getOperand(0));
4555 SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
4556 SelectionDAG &DAG) const {
4557 MVT VT = Op.getSimpleValueType();
4559 // Checking the depth
4560 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0)
4561 return DAG.getConstant(0, DL, VT);
4563 MachineFunction &MF = DAG.getMachineFunction();
4564 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4565 // Check for kernel and shader functions
4566 if (Info->isEntryFunction())
4567 return DAG.getConstant(0, DL, VT);
4569 MachineFrameInfo &MFI = MF.getFrameInfo();
4570 // There is a call to @llvm.returnaddress in this function
4571 MFI.setReturnAddressIsTaken(true);
4573 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
4574 // Get the return address reg and mark it as an implicit live-in
4575 unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
4577 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4580 SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
4584 return Op.getValueType().bitsLE(VT) ?
4585 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
4586 DAG.getNode(ISD::FTRUNC, DL, VT, Op);
4589 SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
4590 assert(Op.getValueType() == MVT::f16 &&
4591 "Do not know how to custom lower FP_ROUND for non-f16 type");
4593 SDValue Src = Op.getOperand(0);
4594 EVT SrcVT = Src.getValueType();
4595 if (SrcVT != MVT::f64)
4600 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
4601 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
4602 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
4605 SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
4606 SelectionDAG &DAG) const {
4607 EVT VT = Op.getValueType();
4608 const MachineFunction &MF = DAG.getMachineFunction();
4609 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4610 bool IsIEEEMode = Info->getMode().IEEE;
4612 // FIXME: Assert during eslection that this is only selected for
4613 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
4614 // mode functions, but this happens to be OK since it's only done in cases
4615 // where there is known no sNaN.
4617 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
4619 if (VT == MVT::v4f16)
4620 return splitBinaryVectorOp(Op, DAG);
4624 SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
4626 SDValue Chain = Op.getOperand(0);
4628 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4629 !Subtarget->isTrapHandlerEnabled())
4630 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
4632 MachineFunction &MF = DAG.getMachineFunction();
4633 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4634 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4635 assert(UserSGPR != AMDGPU::NoRegister);
4636 SDValue QueuePtr = CreateLiveInRegister(
4637 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4638 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
4639 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
4640 QueuePtr, SDValue());
4643 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMTrap, SL, MVT::i16),
4647 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4650 SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
4652 SDValue Chain = Op.getOperand(0);
4653 MachineFunction &MF = DAG.getMachineFunction();
4655 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4656 !Subtarget->isTrapHandlerEnabled()) {
4657 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
4658 "debugtrap handler not supported",
4661 LLVMContext &Ctx = MF.getFunction().getContext();
4662 Ctx.diagnose(NoTrap);
4668 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMDebugTrap, SL, MVT::i16)
4670 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4673 SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
4674 SelectionDAG &DAG) const {
4675 // FIXME: Use inline constants (src_{shared, private}_base) instead.
4676 if (Subtarget->hasApertureRegs()) {
4677 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
4678 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
4679 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
4680 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
4681 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
4682 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
4684 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
4685 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
4686 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
4688 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
4689 SDValue ApertureReg = SDValue(
4690 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
4691 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
4692 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
4695 MachineFunction &MF = DAG.getMachineFunction();
4696 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4697 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4698 assert(UserSGPR != AMDGPU::NoRegister);
4700 SDValue QueuePtr = CreateLiveInRegister(
4701 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4703 // Offset into amd_queue_t for group_segment_aperture_base_hi /
4704 // private_segment_aperture_base_hi.
4705 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
4707 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset);
4709 // TODO: Use custom target PseudoSourceValue.
4710 // TODO: We should use the value from the IR intrinsic call, but it might not
4711 // be available and how do we get it?
4712 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
4713 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
4714 MinAlign(64, StructOffset),
4715 MachineMemOperand::MODereferenceable |
4716 MachineMemOperand::MOInvariant);
4719 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
4720 SelectionDAG &DAG) const {
4722 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
4724 SDValue Src = ASC->getOperand(0);
4725 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
4727 const AMDGPUTargetMachine &TM =
4728 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
4730 // flat -> local/private
4731 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4732 unsigned DestAS = ASC->getDestAddressSpace();
4734 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
4735 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
4736 unsigned NullVal = TM.getNullPointerValue(DestAS);
4737 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4738 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
4739 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
4741 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
4742 NonNull, Ptr, SegmentNullPtr);
4746 // local/private -> flat
4747 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4748 unsigned SrcAS = ASC->getSrcAddressSpace();
4750 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
4751 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
4752 unsigned NullVal = TM.getNullPointerValue(SrcAS);
4753 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4756 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
4758 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
4760 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
4762 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
4763 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
4768 // global <-> flat are no-ops and never emitted.
4770 const MachineFunction &MF = DAG.getMachineFunction();
4771 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
4772 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
4773 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
4775 return DAG.getUNDEF(ASC->getValueType(0));
4778 // This lowers an INSERT_SUBVECTOR by extracting the individual elements from
4779 // the small vector and inserting them into the big vector. That is better than
4780 // the default expansion of doing it via a stack slot. Even though the use of
4781 // the stack slot would be optimized away afterwards, the stack slot itself
4783 SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
4784 SelectionDAG &DAG) const {
4785 SDValue Vec = Op.getOperand(0);
4786 SDValue Ins = Op.getOperand(1);
4787 SDValue Idx = Op.getOperand(2);
4788 EVT VecVT = Vec.getValueType();
4789 EVT InsVT = Ins.getValueType();
4790 EVT EltVT = VecVT.getVectorElementType();
4791 unsigned InsNumElts = InsVT.getVectorNumElements();
4792 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4795 for (unsigned I = 0; I != InsNumElts; ++I) {
4796 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins,
4797 DAG.getConstant(I, SL, MVT::i32));
4798 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
4799 DAG.getConstant(IdxVal + I, SL, MVT::i32));
4804 SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4805 SelectionDAG &DAG) const {
4806 SDValue Vec = Op.getOperand(0);
4807 SDValue InsVal = Op.getOperand(1);
4808 SDValue Idx = Op.getOperand(2);
4809 EVT VecVT = Vec.getValueType();
4810 EVT EltVT = VecVT.getVectorElementType();
4811 unsigned VecSize = VecVT.getSizeInBits();
4812 unsigned EltSize = EltVT.getSizeInBits();
4815 assert(VecSize <= 64);
4817 unsigned NumElts = VecVT.getVectorNumElements();
4819 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
4821 if (NumElts == 4 && EltSize == 16 && KIdx) {
4822 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
4824 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4825 DAG.getConstant(0, SL, MVT::i32));
4826 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4827 DAG.getConstant(1, SL, MVT::i32));
4829 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
4830 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
4832 unsigned Idx = KIdx->getZExtValue();
4833 bool InsertLo = Idx < 2;
4834 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
4835 InsertLo ? LoVec : HiVec,
4836 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
4837 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
4839 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
4841 SDValue Concat = InsertLo ?
4842 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
4843 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
4845 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
4848 if (isa<ConstantSDNode>(Idx))
4851 MVT IntVT = MVT::getIntegerVT(VecSize);
4853 // Avoid stack access for dynamic indexing.
4854 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
4856 // Create a congruent vector with the target value in each element so that
4857 // the required element can be masked and ORed into the target vector.
4858 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
4859 DAG.getSplatBuildVector(VecVT, SL, InsVal));
4861 assert(isPowerOf2_32(EltSize));
4862 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4864 // Convert vector index to bit-index.
4865 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4867 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4868 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
4869 DAG.getConstant(0xffff, SL, IntVT),
4872 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
4873 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
4874 DAG.getNOT(SL, BFM, IntVT), BCVec);
4876 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
4877 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
4880 SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4881 SelectionDAG &DAG) const {
4884 EVT ResultVT = Op.getValueType();
4885 SDValue Vec = Op.getOperand(0);
4886 SDValue Idx = Op.getOperand(1);
4887 EVT VecVT = Vec.getValueType();
4888 unsigned VecSize = VecVT.getSizeInBits();
4889 EVT EltVT = VecVT.getVectorElementType();
4890 assert(VecSize <= 64);
4892 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
4894 // Make sure we do any optimizations that will make it easier to fold
4895 // source modifiers before obscuring it with bit operations.
4897 // XXX - Why doesn't this get called when vector_shuffle is expanded?
4898 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
4901 unsigned EltSize = EltVT.getSizeInBits();
4902 assert(isPowerOf2_32(EltSize));
4904 MVT IntVT = MVT::getIntegerVT(VecSize);
4905 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4907 // Convert vector index to bit-index (* EltSize)
4908 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4910 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4911 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
4913 if (ResultVT == MVT::f16) {
4914 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
4915 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
4918 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
4921 static bool elementPairIsContiguous(ArrayRef<int> Mask, int Elt) {
4922 assert(Elt % 2 == 0);
4923 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
4926 SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4927 SelectionDAG &DAG) const {
4929 EVT ResultVT = Op.getValueType();
4930 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
4932 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;
4933 EVT EltVT = PackVT.getVectorElementType();
4934 int SrcNumElts = Op.getOperand(0).getValueType().getVectorNumElements();
4936 // vector_shuffle <0,1,6,7> lhs, rhs
4937 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
4939 // vector_shuffle <6,7,2,3> lhs, rhs
4940 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
4942 // vector_shuffle <6,7,0,1> lhs, rhs
4943 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
4945 // Avoid scalarizing when both halves are reading from consecutive elements.
4946 SmallVector<SDValue, 4> Pieces;
4947 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) {
4948 if (elementPairIsContiguous(SVN->getMask(), I)) {
4949 const int Idx = SVN->getMaskElt(I);
4950 int VecIdx = Idx < SrcNumElts ? 0 : 1;
4951 int EltIdx = Idx < SrcNumElts ? Idx : Idx - SrcNumElts;
4952 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
4953 PackVT, SVN->getOperand(VecIdx),
4954 DAG.getConstant(EltIdx, SL, MVT::i32));
4955 Pieces.push_back(SubVec);
4957 const int Idx0 = SVN->getMaskElt(I);
4958 const int Idx1 = SVN->getMaskElt(I + 1);
4959 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
4960 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
4961 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
4962 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
4964 SDValue Vec0 = SVN->getOperand(VecIdx0);
4965 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
4966 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32));
4968 SDValue Vec1 = SVN->getOperand(VecIdx1);
4969 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
4970 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
4971 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 }));
4975 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
4978 SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
4979 SelectionDAG &DAG) const {
4981 EVT VT = Op.getValueType();
4983 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
4984 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
4986 // Turn into pair of packed build_vectors.
4987 // TODO: Special case for constants that can be materialized with s_mov_b64.
4988 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
4989 { Op.getOperand(0), Op.getOperand(1) });
4990 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
4991 { Op.getOperand(2), Op.getOperand(3) });
4993 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
4994 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
4996 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
4997 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
5000 assert(VT == MVT::v2f16 || VT == MVT::v2i16);
5001 assert(!Subtarget->hasVOP3PInsts() && "this should be legal");
5003 SDValue Lo = Op.getOperand(0);
5004 SDValue Hi = Op.getOperand(1);
5006 // Avoid adding defined bits with the zero_extend.
5008 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5009 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
5010 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
5013 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
5014 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5016 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
5017 DAG.getConstant(16, SL, MVT::i32));
5019 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
5021 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5022 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
5024 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
5025 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
5029 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5030 // We can fold offsets for anything that doesn't require a GOT relocation.
5031 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
5032 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5033 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5034 !shouldEmitGOTReloc(GA->getGlobal());
5038 buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
5039 const SDLoc &DL, unsigned Offset, EVT PtrVT,
5040 unsigned GAFlags = SIInstrInfo::MO_NONE) {
5041 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
5042 // lowered to the following code sequence:
5044 // For constant address space:
5045 // s_getpc_b64 s[0:1]
5046 // s_add_u32 s0, s0, $symbol
5047 // s_addc_u32 s1, s1, 0
5049 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5050 // a fixup or relocation is emitted to replace $symbol with a literal
5051 // constant, which is a pc-relative offset from the encoding of the $symbol
5052 // operand to the global variable.
5054 // For global address space:
5055 // s_getpc_b64 s[0:1]
5056 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
5057 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
5059 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5060 // fixups or relocations are emitted to replace $symbol@*@lo and
5061 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
5062 // which is a 64-bit pc-relative offset from the encoding of the $symbol
5063 // operand to the global variable.
5065 // What we want here is an offset from the value returned by s_getpc
5066 // (which is the address of the s_add_u32 instruction) to the global
5067 // variable, but since the encoding of $symbol starts 4 bytes after the start
5068 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
5069 // small. This requires us to add 4 to the global variable offset in order to
5070 // compute the correct address.
5072 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
5074 if (GAFlags == SIInstrInfo::MO_NONE) {
5075 PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
5078 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags + 1);
5080 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
5083 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
5085 SelectionDAG &DAG) const {
5086 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
5087 const GlobalValue *GV = GSD->getGlobal();
5088 if ((GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5089 (!GV->hasExternalLinkage() ||
5090 getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||
5091 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)) ||
5092 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
5093 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
5094 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
5097 EVT PtrVT = Op.getValueType();
5099 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
5100 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
5101 SIInstrInfo::MO_ABS32_LO);
5102 return DAG.getNode(AMDGPUISD::LDS, DL, MVT::i32, GA);
5105 if (shouldEmitFixup(GV))
5106 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
5107 else if (shouldEmitPCReloc(GV))
5108 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
5109 SIInstrInfo::MO_REL32);
5111 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
5112 SIInstrInfo::MO_GOTPCREL32);
5114 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
5115 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
5116 const DataLayout &DataLayout = DAG.getDataLayout();
5117 unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
5118 MachinePointerInfo PtrInfo
5119 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
5121 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
5122 MachineMemOperand::MODereferenceable |
5123 MachineMemOperand::MOInvariant);
5126 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
5127 const SDLoc &DL, SDValue V) const {
5128 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
5129 // the destination register.
5131 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
5132 // so we will end up with redundant moves to m0.
5134 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
5136 // A Null SDValue creates a glue result.
5137 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
5139 return SDValue(M0, 0);
5142 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
5145 unsigned Offset) const {
5147 SDValue Param = lowerKernargMemParameter(DAG, MVT::i32, MVT::i32, SL,
5148 DAG.getEntryNode(), Offset, 4, false);
5149 // The local size values will have the hi 16-bits as zero.
5150 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
5151 DAG.getValueType(VT));
5154 static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5156 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5157 "non-hsa intrinsic with hsa target",
5159 DAG.getContext()->diagnose(BadIntrin);
5160 return DAG.getUNDEF(VT);
5163 static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5165 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5166 "intrinsic not supported on subtarget",
5168 DAG.getContext()->diagnose(BadIntrin);
5169 return DAG.getUNDEF(VT);
5172 static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
5173 ArrayRef<SDValue> Elts) {
5174 assert(!Elts.empty());
5178 if (Elts.size() == 1) {
5181 } else if (Elts.size() == 2) {
5184 } else if (Elts.size() <= 4) {
5187 } else if (Elts.size() <= 8) {
5191 assert(Elts.size() <= 16);
5196 SmallVector<SDValue, 16> VecElts(NumElts);
5197 for (unsigned i = 0; i < Elts.size(); ++i) {
5198 SDValue Elt = Elts[i];
5199 if (Elt.getValueType() != MVT::f32)
5200 Elt = DAG.getBitcast(MVT::f32, Elt);
5203 for (unsigned i = Elts.size(); i < NumElts; ++i)
5204 VecElts[i] = DAG.getUNDEF(MVT::f32);
5208 return DAG.getBuildVector(Type, DL, VecElts);
5211 static bool parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG,
5212 SDValue *GLC, SDValue *SLC, SDValue *DLC) {
5213 auto CachePolicyConst = cast<ConstantSDNode>(CachePolicy.getNode());
5215 uint64_t Value = CachePolicyConst->getZExtValue();
5216 SDLoc DL(CachePolicy);
5218 *GLC = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5219 Value &= ~(uint64_t)0x1;
5222 *SLC = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5223 Value &= ~(uint64_t)0x2;
5226 *DLC = DAG.getTargetConstant((Value & 0x4) ? 1 : 0, DL, MVT::i32);
5227 Value &= ~(uint64_t)0x4;
5233 // Re-construct the required return value for a image load intrinsic.
5234 // This is more complicated due to the optional use TexFailCtrl which means the required
5235 // return type is an aggregate
5236 static SDValue constructRetValue(SelectionDAG &DAG,
5237 MachineSDNode *Result,
5238 ArrayRef<EVT> ResultTypes,
5239 bool IsTexFail, bool Unpacked, bool IsD16,
5240 int DMaskPop, int NumVDataDwords,
5241 const SDLoc &DL, LLVMContext &Context) {
5242 // Determine the required return type. This is the same regardless of IsTexFail flag
5243 EVT ReqRetVT = ResultTypes[0];
5244 EVT ReqRetEltVT = ReqRetVT.isVector() ? ReqRetVT.getVectorElementType() : ReqRetVT;
5245 int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
5246 EVT AdjEltVT = Unpacked && IsD16 ? MVT::i32 : ReqRetEltVT;
5247 EVT AdjVT = Unpacked ? ReqRetNumElts > 1 ? EVT::getVectorVT(Context, AdjEltVT, ReqRetNumElts)
5251 // Extract data part of the result
5252 // Bitcast the result to the same type as the required return type
5254 if (IsD16 && !Unpacked)
5255 NumElts = NumVDataDwords << 1;
5257 NumElts = NumVDataDwords;
5259 EVT CastVT = NumElts > 1 ? EVT::getVectorVT(Context, AdjEltVT, NumElts)
5262 // Special case for v6f16. Rather than add support for this, use v3i32 to
5263 // extract the data elements
5264 bool V6F16Special = false;
5266 CastVT = EVT::getVectorVT(Context, MVT::i32, NumElts / 2);
5268 ReqRetNumElts >>= 1;
5269 V6F16Special = true;
5273 SDValue N = SDValue(Result, 0);
5274 SDValue CastRes = DAG.getNode(ISD::BITCAST, DL, CastVT, N);
5276 // Iterate over the result
5277 SmallVector<SDValue, 4> BVElts;
5279 if (CastVT.isVector()) {
5280 DAG.ExtractVectorElements(CastRes, BVElts, 0, DMaskPop);
5282 BVElts.push_back(CastRes);
5284 int ExtraElts = ReqRetNumElts - DMaskPop;
5286 BVElts.push_back(DAG.getUNDEF(AdjEltVT));
5289 if (ReqRetNumElts > 1) {
5290 SDValue NewVec = DAG.getBuildVector(AdjVT, DL, BVElts);
5291 if (IsD16 && Unpacked)
5292 PreTFCRes = adjustLoadValueTypeImpl(NewVec, ReqRetVT, DL, DAG, Unpacked);
5296 PreTFCRes = BVElts[0];
5300 PreTFCRes = DAG.getNode(ISD::BITCAST, DL, MVT::v4f16, PreTFCRes);
5303 if (Result->getNumValues() > 1)
5304 return DAG.getMergeValues({PreTFCRes, SDValue(Result, 1)}, DL);
5309 // Extract the TexFail result and insert into aggregate return
5310 SmallVector<SDValue, 1> TFCElt;
5311 DAG.ExtractVectorElements(N, TFCElt, DMaskPop, 1);
5312 SDValue TFCRes = DAG.getNode(ISD::BITCAST, DL, ResultTypes[1], TFCElt[0]);
5313 return DAG.getMergeValues({PreTFCRes, TFCRes, SDValue(Result, 1)}, DL);
5316 static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
5317 SDValue *LWE, bool &IsTexFail) {
5318 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.getNode());
5320 uint64_t Value = TexFailCtrlConst->getZExtValue();
5325 SDLoc DL(TexFailCtrlConst);
5326 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5327 Value &= ~(uint64_t)0x1;
5328 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5329 Value &= ~(uint64_t)0x2;
5334 SDValue SITargetLowering::lowerImage(SDValue Op,
5335 const AMDGPU::ImageDimIntrinsicInfo *Intr,
5336 SelectionDAG &DAG) const {
5338 MachineFunction &MF = DAG.getMachineFunction();
5339 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
5340 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
5341 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
5342 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
5343 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
5344 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
5345 const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
5346 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
5347 unsigned IntrOpcode = Intr->BaseOpcode;
5348 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
5350 SmallVector<EVT, 3> ResultTypes(Op->value_begin(), Op->value_end());
5351 SmallVector<EVT, 3> OrigResultTypes(Op->value_begin(), Op->value_end());
5356 bool AdjustRetType = false;
5358 unsigned AddrIdx; // Index of first address argument
5360 unsigned DMaskLanes = 0;
5362 if (BaseOpcode->Atomic) {
5363 VData = Op.getOperand(2);
5365 bool Is64Bit = VData.getValueType() == MVT::i64;
5366 if (BaseOpcode->AtomicX2) {
5367 SDValue VData2 = Op.getOperand(3);
5368 VData = DAG.getBuildVector(Is64Bit ? MVT::v2i64 : MVT::v2i32, DL,
5371 VData = DAG.getBitcast(MVT::v4i32, VData);
5373 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
5374 DMask = Is64Bit ? 0xf : 0x3;
5375 NumVDataDwords = Is64Bit ? 4 : 2;
5378 DMask = Is64Bit ? 0x3 : 0x1;
5379 NumVDataDwords = Is64Bit ? 2 : 1;
5383 unsigned DMaskIdx = BaseOpcode->Store ? 3 : isa<MemSDNode>(Op) ? 2 : 1;
5384 auto DMaskConst = cast<ConstantSDNode>(Op.getOperand(DMaskIdx));
5385 DMask = DMaskConst->getZExtValue();
5386 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
5388 if (BaseOpcode->Store) {
5389 VData = Op.getOperand(2);
5391 MVT StoreVT = VData.getSimpleValueType();
5392 if (StoreVT.getScalarType() == MVT::f16) {
5393 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5394 return Op; // D16 is unsupported for this instruction
5397 VData = handleD16VData(VData, DAG);
5400 NumVDataDwords = (VData.getValueType().getSizeInBits() + 31) / 32;
5402 // Work out the num dwords based on the dmask popcount and underlying type
5403 // and whether packing is supported.
5404 MVT LoadVT = ResultTypes[0].getSimpleVT();
5405 if (LoadVT.getScalarType() == MVT::f16) {
5406 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5407 return Op; // D16 is unsupported for this instruction
5412 // Confirm that the return type is large enough for the dmask specified
5413 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) ||
5414 (!LoadVT.isVector() && DMaskLanes > 1))
5417 if (IsD16 && !Subtarget->hasUnpackedD16VMem())
5418 NumVDataDwords = (DMaskLanes + 1) / 2;
5420 NumVDataDwords = DMaskLanes;
5422 AdjustRetType = true;
5425 AddrIdx = DMaskIdx + 1;
5428 unsigned NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0;
5429 unsigned NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0;
5430 unsigned NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0;
5431 unsigned NumVAddrs = BaseOpcode->NumExtraArgs + NumGradients +
5433 unsigned NumMIVAddrs = NumVAddrs;
5435 SmallVector<SDValue, 4> VAddrs;
5437 // Optimize _L to _LZ when _L is zero
5438 if (LZMappingInfo) {
5439 if (auto ConstantLod =
5440 dyn_cast<ConstantFPSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
5441 if (ConstantLod->isZero() || ConstantLod->isNegative()) {
5442 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
5443 NumMIVAddrs--; // remove 'lod'
5448 // Optimize _mip away, when 'lod' is zero
5449 if (MIPMappingInfo) {
5450 if (auto ConstantLod =
5451 dyn_cast<ConstantSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
5452 if (ConstantLod->isNullValue()) {
5453 IntrOpcode = MIPMappingInfo->NONMIP; // set new opcode to variant without _mip
5454 NumMIVAddrs--; // remove 'lod'
5459 // Check for 16 bit addresses and pack if true.
5460 unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;
5461 MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType();
5462 const MVT VAddrScalarVT = VAddrVT.getScalarType();
5463 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
5464 ST->hasFeature(AMDGPU::FeatureR128A16)) {
5466 const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
5467 for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {
5468 SDValue AddrLo, AddrHi;
5469 // Push back extra arguments.
5471 AddrLo = Op.getOperand(i);
5473 AddrLo = Op.getOperand(i);
5474 // Dz/dh, dz/dv and the last odd coord are packed with undef. Also,
5475 // in 1D, derivatives dx/dh and dx/dv are packed with undef.
5476 if (((i + 1) >= (AddrIdx + NumMIVAddrs)) ||
5477 ((NumGradients / 2) % 2 == 1 &&
5478 (i == DimIdx + (NumGradients / 2) - 1 ||
5479 i == DimIdx + NumGradients - 1))) {
5480 AddrHi = DAG.getUNDEF(MVT::f16);
5482 AddrHi = Op.getOperand(i + 1);
5485 AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
5487 AddrLo = DAG.getBitcast(MVT::i32, AddrLo);
5489 VAddrs.push_back(AddrLo);
5492 for (unsigned i = 0; i < NumMIVAddrs; ++i)
5493 VAddrs.push_back(Op.getOperand(AddrIdx + i));
5496 // If the register allocator cannot place the address registers contiguously
5497 // without introducing moves, then using the non-sequential address encoding
5498 // is always preferable, since it saves VALU instructions and is usually a
5499 // wash in terms of code size or even better.
5501 // However, we currently have no way of hinting to the register allocator that
5502 // MIMG addresses should be placed contiguously when it is possible to do so,
5503 // so force non-NSA for the common 2-address case as a heuristic.
5505 // SIShrinkInstructions will convert NSA encodings to non-NSA after register
5506 // allocation when possible.
5508 ST->hasFeature(AMDGPU::FeatureNSAEncoding) && VAddrs.size() >= 3;
5511 VAddr = getBuildDwordsVector(DAG, DL, VAddrs);
5513 SDValue True = DAG.getTargetConstant(1, DL, MVT::i1);
5514 SDValue False = DAG.getTargetConstant(0, DL, MVT::i1);
5515 unsigned CtrlIdx; // Index of texfailctrl argument
5517 if (!BaseOpcode->Sampler) {
5519 CtrlIdx = AddrIdx + NumVAddrs + 1;
5522 cast<ConstantSDNode>(Op.getOperand(AddrIdx + NumVAddrs + 2));
5524 Unorm = UnormConst->getZExtValue() ? True : False;
5525 CtrlIdx = AddrIdx + NumVAddrs + 3;
5530 SDValue TexFail = Op.getOperand(CtrlIdx);
5531 bool IsTexFail = false;
5532 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
5537 // Expecting to get an error flag since TFC is on - and dmask is 0
5538 // Force dmask to be at least 1 otherwise the instruction will fail
5543 NumVDataDwords += 1;
5544 AdjustRetType = true;
5547 // Has something earlier tagged that the return type needs adjusting
5548 // This happens if the instruction is a load or has set TexFailCtrl flags
5549 if (AdjustRetType) {
5550 // NumVDataDwords reflects the true number of dwords required in the return type
5551 if (DMaskLanes == 0 && !BaseOpcode->Store) {
5552 // This is a no-op load. This can be eliminated
5553 SDValue Undef = DAG.getUNDEF(Op.getValueType());
5554 if (isa<MemSDNode>(Op))
5555 return DAG.getMergeValues({Undef, Op.getOperand(0)}, DL);
5559 EVT NewVT = NumVDataDwords > 1 ?
5560 EVT::getVectorVT(*DAG.getContext(), MVT::f32, NumVDataDwords)
5563 ResultTypes[0] = NewVT;
5564 if (ResultTypes.size() == 3) {
5565 // Original result was aggregate type used for TexFailCtrl results
5566 // The actual instruction returns as a vector type which has now been
5567 // created. Remove the aggregate result.
5568 ResultTypes.erase(&ResultTypes[1]);
5575 if (BaseOpcode->Atomic) {
5576 GLC = True; // TODO no-return optimization
5577 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, nullptr, &SLC,
5578 IsGFX10 ? &DLC : nullptr))
5581 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, &GLC, &SLC,
5582 IsGFX10 ? &DLC : nullptr))
5586 SmallVector<SDValue, 26> Ops;
5587 if (BaseOpcode->Store || BaseOpcode->Atomic)
5588 Ops.push_back(VData); // vdata
5590 for (const SDValue &Addr : VAddrs)
5591 Ops.push_back(Addr);
5593 Ops.push_back(VAddr);
5595 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs)); // rsrc
5596 if (BaseOpcode->Sampler)
5597 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs + 1)); // sampler
5598 Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32));
5600 Ops.push_back(DAG.getTargetConstant(DimInfo->Encoding, DL, MVT::i32));
5601 Ops.push_back(Unorm);
5606 Ops.push_back(IsA16 && // a16 or r128
5607 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
5608 Ops.push_back(TFE); // tfe
5609 Ops.push_back(LWE); // lwe
5611 Ops.push_back(DimInfo->DA ? True : False);
5612 if (BaseOpcode->HasD16)
5613 Ops.push_back(IsD16 ? True : False);
5614 if (isa<MemSDNode>(Op))
5615 Ops.push_back(Op.getOperand(0)); // chain
5617 int NumVAddrDwords =
5618 UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32;
5622 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode,
5623 UseNSA ? AMDGPU::MIMGEncGfx10NSA
5624 : AMDGPU::MIMGEncGfx10Default,
5625 NumVDataDwords, NumVAddrDwords);
5627 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5628 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx8,
5629 NumVDataDwords, NumVAddrDwords);
5631 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx6,
5632 NumVDataDwords, NumVAddrDwords);
5634 assert(Opcode != -1);
5636 MachineSDNode *NewNode = DAG.getMachineNode(Opcode, DL, ResultTypes, Ops);
5637 if (auto MemOp = dyn_cast<MemSDNode>(Op)) {
5638 MachineMemOperand *MemRef = MemOp->getMemOperand();
5639 DAG.setNodeMemRefs(NewNode, {MemRef});
5642 if (BaseOpcode->AtomicX2) {
5643 SmallVector<SDValue, 1> Elt;
5644 DAG.ExtractVectorElements(SDValue(NewNode, 0), Elt, 0, 1);
5645 return DAG.getMergeValues({Elt[0], SDValue(NewNode, 1)}, DL);
5646 } else if (!BaseOpcode->Store) {
5647 return constructRetValue(DAG, NewNode,
5648 OrigResultTypes, IsTexFail,
5649 Subtarget->hasUnpackedD16VMem(), IsD16,
5650 DMaskLanes, NumVDataDwords, DL,
5654 return SDValue(NewNode, 0);
5657 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
5658 SDValue Offset, SDValue GLC, SDValue DLC,
5659 SelectionDAG &DAG) const {
5660 MachineFunction &MF = DAG.getMachineFunction();
5662 const DataLayout &DataLayout = DAG.getDataLayout();
5664 DataLayout.getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5666 MachineMemOperand *MMO = MF.getMachineMemOperand(
5667 MachinePointerInfo(),
5668 MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
5669 MachineMemOperand::MOInvariant,
5670 VT.getStoreSize(), Align);
5672 if (!Offset->isDivergent()) {
5680 // Widen vec3 load to vec4.
5681 if (VT.isVector() && VT.getVectorNumElements() == 3) {
5683 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
5684 auto WidenedOp = DAG.getMemIntrinsicNode(
5685 AMDGPUISD::SBUFFER_LOAD, DL, DAG.getVTList(WidenedVT), Ops, WidenedVT,
5686 MF.getMachineMemOperand(MMO, 0, WidenedVT.getStoreSize()));
5687 auto Subvector = DAG.getNode(
5688 ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp,
5689 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
5693 return DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD, DL,
5694 DAG.getVTList(VT), Ops, VT, MMO);
5697 // We have a divergent offset. Emit a MUBUF buffer load instead. We can
5698 // assume that the buffer is unswizzled.
5699 SmallVector<SDValue, 4> Loads;
5700 unsigned NumLoads = 1;
5701 MVT LoadVT = VT.getSimpleVT();
5702 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1;
5703 assert((LoadVT.getScalarType() == MVT::i32 ||
5704 LoadVT.getScalarType() == MVT::f32));
5706 if (NumElts == 8 || NumElts == 16) {
5707 NumLoads = NumElts / 4;
5708 LoadVT = MVT::v4i32;
5711 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue});
5712 unsigned CachePolicy = cast<ConstantSDNode>(GLC)->getZExtValue();
5714 DAG.getEntryNode(), // Chain
5716 DAG.getConstant(0, DL, MVT::i32), // vindex
5720 DAG.getTargetConstant(CachePolicy, DL, MVT::i32), // cachepolicy
5721 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
5724 // Use the alignment to ensure that the required offsets will fit into the
5725 // immediate offsets.
5726 setBufferOffsets(Offset, DAG, &Ops[3], NumLoads > 1 ? 16 * NumLoads : 4);
5728 uint64_t InstOffset = cast<ConstantSDNode>(Ops[5])->getZExtValue();
5729 for (unsigned i = 0; i < NumLoads; ++i) {
5730 Ops[5] = DAG.getTargetConstant(InstOffset + 16 * i, DL, MVT::i32);
5731 Loads.push_back(getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD, DL, VTList, Ops,
5735 if (VT == MVT::v8i32 || VT == MVT::v16i32)
5736 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads);
5741 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5742 SelectionDAG &DAG) const {
5743 MachineFunction &MF = DAG.getMachineFunction();
5744 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
5746 EVT VT = Op.getValueType();
5748 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5750 // TODO: Should this propagate fast-math-flags?
5752 switch (IntrinsicID) {
5753 case Intrinsic::amdgcn_implicit_buffer_ptr: {
5754 if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction()))
5755 return emitNonHSAIntrinsicError(DAG, DL, VT);
5756 return getPreloadedValue(DAG, *MFI, VT,
5757 AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR);
5759 case Intrinsic::amdgcn_dispatch_ptr:
5760 case Intrinsic::amdgcn_queue_ptr: {
5761 if (!Subtarget->isAmdHsaOrMesa(MF.getFunction())) {
5762 DiagnosticInfoUnsupported BadIntrin(
5763 MF.getFunction(), "unsupported hsa intrinsic without hsa target",
5765 DAG.getContext()->diagnose(BadIntrin);
5766 return DAG.getUNDEF(VT);
5769 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
5770 AMDGPUFunctionArgInfo::DISPATCH_PTR : AMDGPUFunctionArgInfo::QUEUE_PTR;
5771 return getPreloadedValue(DAG, *MFI, VT, RegID);
5773 case Intrinsic::amdgcn_implicitarg_ptr: {
5774 if (MFI->isEntryFunction())
5775 return getImplicitArgPtr(DAG, DL);
5776 return getPreloadedValue(DAG, *MFI, VT,
5777 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
5779 case Intrinsic::amdgcn_kernarg_segment_ptr: {
5780 return getPreloadedValue(DAG, *MFI, VT,
5781 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
5783 case Intrinsic::amdgcn_dispatch_id: {
5784 return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::DISPATCH_ID);
5786 case Intrinsic::amdgcn_rcp:
5787 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
5788 case Intrinsic::amdgcn_rsq:
5789 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
5790 case Intrinsic::amdgcn_rsq_legacy:
5791 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5792 return emitRemovedIntrinsicError(DAG, DL, VT);
5794 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
5795 case Intrinsic::amdgcn_rcp_legacy:
5796 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5797 return emitRemovedIntrinsicError(DAG, DL, VT);
5798 return DAG.getNode(AMDGPUISD::RCP_LEGACY, DL, VT, Op.getOperand(1));
5799 case Intrinsic::amdgcn_rsq_clamp: {
5800 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5801 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
5803 Type *Type = VT.getTypeForEVT(*DAG.getContext());
5804 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
5805 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
5807 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
5808 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
5809 DAG.getConstantFP(Max, DL, VT));
5810 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
5811 DAG.getConstantFP(Min, DL, VT));
5813 case Intrinsic::r600_read_ngroups_x:
5814 if (Subtarget->isAmdHsaOS())
5815 return emitNonHSAIntrinsicError(DAG, DL, VT);
5817 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5818 SI::KernelInputOffsets::NGROUPS_X, 4, false);
5819 case Intrinsic::r600_read_ngroups_y:
5820 if (Subtarget->isAmdHsaOS())
5821 return emitNonHSAIntrinsicError(DAG, DL, VT);
5823 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5824 SI::KernelInputOffsets::NGROUPS_Y, 4, false);
5825 case Intrinsic::r600_read_ngroups_z:
5826 if (Subtarget->isAmdHsaOS())
5827 return emitNonHSAIntrinsicError(DAG, DL, VT);
5829 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5830 SI::KernelInputOffsets::NGROUPS_Z, 4, false);
5831 case Intrinsic::r600_read_global_size_x:
5832 if (Subtarget->isAmdHsaOS())
5833 return emitNonHSAIntrinsicError(DAG, DL, VT);
5835 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5836 SI::KernelInputOffsets::GLOBAL_SIZE_X, 4, false);
5837 case Intrinsic::r600_read_global_size_y:
5838 if (Subtarget->isAmdHsaOS())
5839 return emitNonHSAIntrinsicError(DAG, DL, VT);
5841 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5842 SI::KernelInputOffsets::GLOBAL_SIZE_Y, 4, false);
5843 case Intrinsic::r600_read_global_size_z:
5844 if (Subtarget->isAmdHsaOS())
5845 return emitNonHSAIntrinsicError(DAG, DL, VT);
5847 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5848 SI::KernelInputOffsets::GLOBAL_SIZE_Z, 4, false);
5849 case Intrinsic::r600_read_local_size_x:
5850 if (Subtarget->isAmdHsaOS())
5851 return emitNonHSAIntrinsicError(DAG, DL, VT);
5853 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5854 SI::KernelInputOffsets::LOCAL_SIZE_X);
5855 case Intrinsic::r600_read_local_size_y:
5856 if (Subtarget->isAmdHsaOS())
5857 return emitNonHSAIntrinsicError(DAG, DL, VT);
5859 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5860 SI::KernelInputOffsets::LOCAL_SIZE_Y);
5861 case Intrinsic::r600_read_local_size_z:
5862 if (Subtarget->isAmdHsaOS())
5863 return emitNonHSAIntrinsicError(DAG, DL, VT);
5865 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5866 SI::KernelInputOffsets::LOCAL_SIZE_Z);
5867 case Intrinsic::amdgcn_workgroup_id_x:
5868 case Intrinsic::r600_read_tgid_x:
5869 return getPreloadedValue(DAG, *MFI, VT,
5870 AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
5871 case Intrinsic::amdgcn_workgroup_id_y:
5872 case Intrinsic::r600_read_tgid_y:
5873 return getPreloadedValue(DAG, *MFI, VT,
5874 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
5875 case Intrinsic::amdgcn_workgroup_id_z:
5876 case Intrinsic::r600_read_tgid_z:
5877 return getPreloadedValue(DAG, *MFI, VT,
5878 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
5879 case Intrinsic::amdgcn_workitem_id_x:
5880 case Intrinsic::r600_read_tidig_x:
5881 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5882 SDLoc(DAG.getEntryNode()),
5883 MFI->getArgInfo().WorkItemIDX);
5884 case Intrinsic::amdgcn_workitem_id_y:
5885 case Intrinsic::r600_read_tidig_y:
5886 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5887 SDLoc(DAG.getEntryNode()),
5888 MFI->getArgInfo().WorkItemIDY);
5889 case Intrinsic::amdgcn_workitem_id_z:
5890 case Intrinsic::r600_read_tidig_z:
5891 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5892 SDLoc(DAG.getEntryNode()),
5893 MFI->getArgInfo().WorkItemIDZ);
5894 case Intrinsic::amdgcn_wavefrontsize:
5895 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
5896 SDLoc(Op), MVT::i32);
5897 case Intrinsic::amdgcn_s_buffer_load: {
5898 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
5900 SDValue DLC = DAG.getTargetConstant(0, DL, MVT::i1);
5901 if (!parseCachePolicy(Op.getOperand(3), DAG, &GLC, nullptr,
5902 IsGFX10 ? &DLC : nullptr))
5904 return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), GLC, DLC,
5907 case Intrinsic::amdgcn_fdiv_fast:
5908 return lowerFDIV_FAST(Op, DAG);
5909 case Intrinsic::amdgcn_interp_p1_f16: {
5910 SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5911 Op.getOperand(5), SDValue());
5912 if (getSubtarget()->getLDSBankCount() == 16) {
5915 // FIXME: This implicitly will insert a second CopyToReg to M0.
5916 SDValue S = DAG.getNode(
5917 ISD::INTRINSIC_WO_CHAIN, DL, MVT::f32,
5918 DAG.getTargetConstant(Intrinsic::amdgcn_interp_mov, DL, MVT::i32),
5919 DAG.getConstant(2, DL, MVT::i32), // P0
5920 Op.getOperand(2), // Attrchan
5921 Op.getOperand(3), // Attr
5922 Op.getOperand(5)); // m0
5925 Op.getOperand(1), // Src0
5926 Op.getOperand(2), // Attrchan
5927 Op.getOperand(3), // Attr
5928 DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
5929 S, // Src2 - holds two f16 values selected by high
5930 DAG.getTargetConstant(0, DL, MVT::i32), // $src2_modifiers
5931 Op.getOperand(4), // high
5932 DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
5933 DAG.getTargetConstant(0, DL, MVT::i32) // $omod
5935 return DAG.getNode(AMDGPUISD::INTERP_P1LV_F16, DL, MVT::f32, Ops);
5939 Op.getOperand(1), // Src0
5940 Op.getOperand(2), // Attrchan
5941 Op.getOperand(3), // Attr
5942 DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
5943 Op.getOperand(4), // high
5944 DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
5945 DAG.getTargetConstant(0, DL, MVT::i32), // $omod
5948 return DAG.getNode(AMDGPUISD::INTERP_P1LL_F16, DL, MVT::f32, Ops);
5951 case Intrinsic::amdgcn_sin:
5952 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
5954 case Intrinsic::amdgcn_cos:
5955 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
5957 case Intrinsic::amdgcn_mul_u24:
5958 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT, Op.getOperand(1), Op.getOperand(2));
5959 case Intrinsic::amdgcn_mul_i24:
5960 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT, Op.getOperand(1), Op.getOperand(2));
5962 case Intrinsic::amdgcn_log_clamp: {
5963 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5966 DiagnosticInfoUnsupported BadIntrin(
5967 MF.getFunction(), "intrinsic not supported on subtarget",
5969 DAG.getContext()->diagnose(BadIntrin);
5970 return DAG.getUNDEF(VT);
5972 case Intrinsic::amdgcn_ldexp:
5973 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT,
5974 Op.getOperand(1), Op.getOperand(2));
5976 case Intrinsic::amdgcn_fract:
5977 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
5979 case Intrinsic::amdgcn_class:
5980 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
5981 Op.getOperand(1), Op.getOperand(2));
5982 case Intrinsic::amdgcn_div_fmas:
5983 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
5984 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5987 case Intrinsic::amdgcn_div_fixup:
5988 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
5989 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5991 case Intrinsic::amdgcn_trig_preop:
5992 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
5993 Op.getOperand(1), Op.getOperand(2));
5994 case Intrinsic::amdgcn_div_scale: {
5995 const ConstantSDNode *Param = cast<ConstantSDNode>(Op.getOperand(3));
5997 // Translate to the operands expected by the machine instruction. The
5998 // first parameter must be the same as the first instruction.
5999 SDValue Numerator = Op.getOperand(1);
6000 SDValue Denominator = Op.getOperand(2);
6002 // Note this order is opposite of the machine instruction's operations,
6003 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
6004 // intrinsic has the numerator as the first operand to match a normal
6005 // division operation.
6007 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
6009 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
6010 Denominator, Numerator);
6012 case Intrinsic::amdgcn_icmp: {
6013 // There is a Pat that handles this variant, so return it as-is.
6014 if (Op.getOperand(1).getValueType() == MVT::i1 &&
6015 Op.getConstantOperandVal(2) == 0 &&
6016 Op.getConstantOperandVal(3) == ICmpInst::Predicate::ICMP_NE)
6018 return lowerICMPIntrinsic(*this, Op.getNode(), DAG);
6020 case Intrinsic::amdgcn_fcmp: {
6021 return lowerFCMPIntrinsic(*this, Op.getNode(), DAG);
6023 case Intrinsic::amdgcn_fmed3:
6024 return DAG.getNode(AMDGPUISD::FMED3, DL, VT,
6025 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
6026 case Intrinsic::amdgcn_fdot2:
6027 return DAG.getNode(AMDGPUISD::FDOT2, DL, VT,
6028 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
6030 case Intrinsic::amdgcn_fmul_legacy:
6031 return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT,
6032 Op.getOperand(1), Op.getOperand(2));
6033 case Intrinsic::amdgcn_sffbh:
6034 return DAG.getNode(AMDGPUISD::FFBH_I32, DL, VT, Op.getOperand(1));
6035 case Intrinsic::amdgcn_sbfe:
6036 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
6037 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
6038 case Intrinsic::amdgcn_ubfe:
6039 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
6040 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
6041 case Intrinsic::amdgcn_cvt_pkrtz:
6042 case Intrinsic::amdgcn_cvt_pknorm_i16:
6043 case Intrinsic::amdgcn_cvt_pknorm_u16:
6044 case Intrinsic::amdgcn_cvt_pk_i16:
6045 case Intrinsic::amdgcn_cvt_pk_u16: {
6046 // FIXME: Stop adding cast if v2f16/v2i16 are legal.
6047 EVT VT = Op.getValueType();
6050 if (IntrinsicID == Intrinsic::amdgcn_cvt_pkrtz)
6051 Opcode = AMDGPUISD::CVT_PKRTZ_F16_F32;
6052 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_i16)
6053 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
6054 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_u16)
6055 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
6056 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pk_i16)
6057 Opcode = AMDGPUISD::CVT_PK_I16_I32;
6059 Opcode = AMDGPUISD::CVT_PK_U16_U32;
6061 if (isTypeLegal(VT))
6062 return DAG.getNode(Opcode, DL, VT, Op.getOperand(1), Op.getOperand(2));
6064 SDValue Node = DAG.getNode(Opcode, DL, MVT::i32,
6065 Op.getOperand(1), Op.getOperand(2));
6066 return DAG.getNode(ISD::BITCAST, DL, VT, Node);
6068 case Intrinsic::amdgcn_fmad_ftz:
6069 return DAG.getNode(AMDGPUISD::FMAD_FTZ, DL, VT, Op.getOperand(1),
6070 Op.getOperand(2), Op.getOperand(3));
6072 case Intrinsic::amdgcn_if_break:
6073 return SDValue(DAG.getMachineNode(AMDGPU::SI_IF_BREAK, DL, VT,
6074 Op->getOperand(1), Op->getOperand(2)), 0);
6076 case Intrinsic::amdgcn_groupstaticsize: {
6077 Triple::OSType OS = getTargetMachine().getTargetTriple().getOS();
6078 if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
6081 const Module *M = MF.getFunction().getParent();
6082 const GlobalValue *GV =
6083 M->getNamedValue(Intrinsic::getName(Intrinsic::amdgcn_groupstaticsize));
6084 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
6085 SIInstrInfo::MO_ABS32_LO);
6086 return {DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, GA), 0};
6088 case Intrinsic::amdgcn_is_shared:
6089 case Intrinsic::amdgcn_is_private: {
6091 unsigned AS = (IntrinsicID == Intrinsic::amdgcn_is_shared) ?
6092 AMDGPUAS::LOCAL_ADDRESS : AMDGPUAS::PRIVATE_ADDRESS;
6093 SDValue Aperture = getSegmentAperture(AS, SL, DAG);
6094 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32,
6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec,
6098 DAG.getConstant(1, SL, MVT::i32));
6099 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ);
6102 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
6103 AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
6104 return lowerImage(Op, ImageDimIntr, DAG);
6110 // This function computes an appropriate offset to pass to
6111 // MachineMemOperand::setOffset() based on the offset inputs to
6112 // an intrinsic. If any of the offsets are non-contstant or
6113 // if VIndex is non-zero then this function returns 0. Otherwise,
6114 // it returns the sum of VOffset, SOffset, and Offset.
6115 static unsigned getBufferOffsetForMMO(SDValue VOffset,
6118 SDValue VIndex = SDValue()) {
6120 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) ||
6121 !isa<ConstantSDNode>(Offset))
6125 if (!isa<ConstantSDNode>(VIndex) || !cast<ConstantSDNode>(VIndex)->isNullValue())
6129 return cast<ConstantSDNode>(VOffset)->getSExtValue() +
6130 cast<ConstantSDNode>(SOffset)->getSExtValue() +
6131 cast<ConstantSDNode>(Offset)->getSExtValue();
6134 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
6135 SelectionDAG &DAG) const {
6136 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6140 case Intrinsic::amdgcn_ds_ordered_add:
6141 case Intrinsic::amdgcn_ds_ordered_swap: {
6142 MemSDNode *M = cast<MemSDNode>(Op);
6143 SDValue Chain = M->getOperand(0);
6144 SDValue M0 = M->getOperand(2);
6145 SDValue Value = M->getOperand(3);
6146 unsigned IndexOperand = M->getConstantOperandVal(7);
6147 unsigned WaveRelease = M->getConstantOperandVal(8);
6148 unsigned WaveDone = M->getConstantOperandVal(9);
6149 unsigned ShaderType;
6150 unsigned Instruction;
6152 unsigned OrderedCountIndex = IndexOperand & 0x3f;
6153 IndexOperand &= ~0x3f;
6154 unsigned CountDw = 0;
6156 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) {
6157 CountDw = (IndexOperand >> 24) & 0xf;
6158 IndexOperand &= ~(0xf << 24);
6160 if (CountDw < 1 || CountDw > 4) {
6162 "ds_ordered_count: dword count must be between 1 and 4");
6167 report_fatal_error("ds_ordered_count: bad index operand");
6170 case Intrinsic::amdgcn_ds_ordered_add:
6173 case Intrinsic::amdgcn_ds_ordered_swap:
6178 if (WaveDone && !WaveRelease)
6179 report_fatal_error("ds_ordered_count: wave_done requires wave_release");
6181 switch (DAG.getMachineFunction().getFunction().getCallingConv()) {
6182 case CallingConv::AMDGPU_CS:
6183 case CallingConv::AMDGPU_KERNEL:
6186 case CallingConv::AMDGPU_PS:
6189 case CallingConv::AMDGPU_VS:
6192 case CallingConv::AMDGPU_GS:
6196 report_fatal_error("ds_ordered_count unsupported for this calling conv");
6199 unsigned Offset0 = OrderedCountIndex << 2;
6200 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
6203 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
6204 Offset1 |= (CountDw - 1) << 6;
6206 unsigned Offset = Offset0 | (Offset1 << 8);
6211 DAG.getTargetConstant(Offset, DL, MVT::i16),
6212 copyToM0(DAG, Chain, DL, M0).getValue(1), // Glue
6214 return DAG.getMemIntrinsicNode(AMDGPUISD::DS_ORDERED_COUNT, DL,
6215 M->getVTList(), Ops, M->getMemoryVT(),
6216 M->getMemOperand());
6218 case Intrinsic::amdgcn_ds_fadd: {
6219 MemSDNode *M = cast<MemSDNode>(Op);
6222 case Intrinsic::amdgcn_ds_fadd:
6223 Opc = ISD::ATOMIC_LOAD_FADD;
6227 return DAG.getAtomic(Opc, SDLoc(Op), M->getMemoryVT(),
6228 M->getOperand(0), M->getOperand(2), M->getOperand(3),
6229 M->getMemOperand());
6231 case Intrinsic::amdgcn_atomic_inc:
6232 case Intrinsic::amdgcn_atomic_dec:
6233 case Intrinsic::amdgcn_ds_fmin:
6234 case Intrinsic::amdgcn_ds_fmax: {
6235 MemSDNode *M = cast<MemSDNode>(Op);
6238 case Intrinsic::amdgcn_atomic_inc:
6239 Opc = AMDGPUISD::ATOMIC_INC;
6241 case Intrinsic::amdgcn_atomic_dec:
6242 Opc = AMDGPUISD::ATOMIC_DEC;
6244 case Intrinsic::amdgcn_ds_fmin:
6245 Opc = AMDGPUISD::ATOMIC_LOAD_FMIN;
6247 case Intrinsic::amdgcn_ds_fmax:
6248 Opc = AMDGPUISD::ATOMIC_LOAD_FMAX;
6251 llvm_unreachable("Unknown intrinsic!");
6254 M->getOperand(0), // Chain
6255 M->getOperand(2), // Ptr
6256 M->getOperand(3) // Value
6259 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
6260 M->getMemoryVT(), M->getMemOperand());
6262 case Intrinsic::amdgcn_buffer_load:
6263 case Intrinsic::amdgcn_buffer_load_format: {
6264 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
6265 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
6267 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
6268 IdxEn = Idx->getZExtValue() != 0;
6270 Op.getOperand(0), // Chain
6271 Op.getOperand(2), // rsrc
6272 Op.getOperand(3), // vindex
6273 SDValue(), // voffset -- will be set by setBufferOffsets
6274 SDValue(), // soffset -- will be set by setBufferOffsets
6275 SDValue(), // offset -- will be set by setBufferOffsets
6276 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6277 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6280 unsigned Offset = setBufferOffsets(Op.getOperand(4), DAG, &Ops[3]);
6281 // We don't know the offset if vindex is non-zero, so clear it.
6285 unsigned Opc = (IntrID == Intrinsic::amdgcn_buffer_load) ?
6286 AMDGPUISD::BUFFER_LOAD : AMDGPUISD::BUFFER_LOAD_FORMAT;
6288 EVT VT = Op.getValueType();
6289 EVT IntVT = VT.changeTypeToInteger();
6290 auto *M = cast<MemSDNode>(Op);
6291 M->getMemOperand()->setOffset(Offset);
6292 EVT LoadVT = Op.getValueType();
6294 if (LoadVT.getScalarType() == MVT::f16)
6295 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
6298 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
6299 if (LoadVT.getScalarType() == MVT::i8 ||
6300 LoadVT.getScalarType() == MVT::i16)
6301 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
6303 return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
6304 M->getMemOperand(), DAG);
6306 case Intrinsic::amdgcn_raw_buffer_load:
6307 case Intrinsic::amdgcn_raw_buffer_load_format: {
6308 const bool IsFormat = IntrID == Intrinsic::amdgcn_raw_buffer_load_format;
6310 auto Offsets = splitBufferOffsets(Op.getOperand(3), DAG);
6312 Op.getOperand(0), // Chain
6313 Op.getOperand(2), // rsrc
6314 DAG.getConstant(0, DL, MVT::i32), // vindex
6315 Offsets.first, // voffset
6316 Op.getOperand(4), // soffset
6317 Offsets.second, // offset
6318 Op.getOperand(5), // cachepolicy, swizzled buffer
6319 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6322 auto *M = cast<MemSDNode>(Op);
6323 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[3], Ops[4], Ops[5]));
6324 return lowerIntrinsicLoad(M, IsFormat, DAG, Ops);
6326 case Intrinsic::amdgcn_struct_buffer_load:
6327 case Intrinsic::amdgcn_struct_buffer_load_format: {
6328 const bool IsFormat = IntrID == Intrinsic::amdgcn_struct_buffer_load_format;
6330 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6332 Op.getOperand(0), // Chain
6333 Op.getOperand(2), // rsrc
6334 Op.getOperand(3), // vindex
6335 Offsets.first, // voffset
6336 Op.getOperand(5), // soffset
6337 Offsets.second, // offset
6338 Op.getOperand(6), // cachepolicy, swizzled buffer
6339 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
6342 auto *M = cast<MemSDNode>(Op);
6343 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[3], Ops[4], Ops[5],
6345 return lowerIntrinsicLoad(cast<MemSDNode>(Op), IsFormat, DAG, Ops);
6347 case Intrinsic::amdgcn_tbuffer_load: {
6348 MemSDNode *M = cast<MemSDNode>(Op);
6349 EVT LoadVT = Op.getValueType();
6351 unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
6352 unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue();
6353 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue();
6354 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(10))->getZExtValue();
6356 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
6357 IdxEn = Idx->getZExtValue() != 0;
6359 Op.getOperand(0), // Chain
6360 Op.getOperand(2), // rsrc
6361 Op.getOperand(3), // vindex
6362 Op.getOperand(4), // voffset
6363 Op.getOperand(5), // soffset
6364 Op.getOperand(6), // offset
6365 DAG.getTargetConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
6366 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6367 DAG.getTargetConstant(IdxEn, DL, MVT::i1) // idxen
6370 if (LoadVT.getScalarType() == MVT::f16)
6371 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
6373 return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
6374 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6377 case Intrinsic::amdgcn_raw_tbuffer_load: {
6378 MemSDNode *M = cast<MemSDNode>(Op);
6379 EVT LoadVT = Op.getValueType();
6380 auto Offsets = splitBufferOffsets(Op.getOperand(3), DAG);
6383 Op.getOperand(0), // Chain
6384 Op.getOperand(2), // rsrc
6385 DAG.getConstant(0, DL, MVT::i32), // vindex
6386 Offsets.first, // voffset
6387 Op.getOperand(4), // soffset
6388 Offsets.second, // offset
6389 Op.getOperand(5), // format
6390 Op.getOperand(6), // cachepolicy, swizzled buffer
6391 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6394 if (LoadVT.getScalarType() == MVT::f16)
6395 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
6397 return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
6398 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6401 case Intrinsic::amdgcn_struct_tbuffer_load: {
6402 MemSDNode *M = cast<MemSDNode>(Op);
6403 EVT LoadVT = Op.getValueType();
6404 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6407 Op.getOperand(0), // Chain
6408 Op.getOperand(2), // rsrc
6409 Op.getOperand(3), // vindex
6410 Offsets.first, // voffset
6411 Op.getOperand(5), // soffset
6412 Offsets.second, // offset
6413 Op.getOperand(6), // format
6414 Op.getOperand(7), // cachepolicy, swizzled buffer
6415 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
6418 if (LoadVT.getScalarType() == MVT::f16)
6419 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
6421 return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
6422 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6425 case Intrinsic::amdgcn_buffer_atomic_swap:
6426 case Intrinsic::amdgcn_buffer_atomic_add:
6427 case Intrinsic::amdgcn_buffer_atomic_sub:
6428 case Intrinsic::amdgcn_buffer_atomic_smin:
6429 case Intrinsic::amdgcn_buffer_atomic_umin:
6430 case Intrinsic::amdgcn_buffer_atomic_smax:
6431 case Intrinsic::amdgcn_buffer_atomic_umax:
6432 case Intrinsic::amdgcn_buffer_atomic_and:
6433 case Intrinsic::amdgcn_buffer_atomic_or:
6434 case Intrinsic::amdgcn_buffer_atomic_xor: {
6435 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
6437 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
6438 IdxEn = Idx->getZExtValue() != 0;
6440 Op.getOperand(0), // Chain
6441 Op.getOperand(2), // vdata
6442 Op.getOperand(3), // rsrc
6443 Op.getOperand(4), // vindex
6444 SDValue(), // voffset -- will be set by setBufferOffsets
6445 SDValue(), // soffset -- will be set by setBufferOffsets
6446 SDValue(), // offset -- will be set by setBufferOffsets
6447 DAG.getTargetConstant(Slc << 1, DL, MVT::i32), // cachepolicy
6448 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6450 unsigned Offset = setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
6451 // We don't know the offset if vindex is non-zero, so clear it.
6454 EVT VT = Op.getValueType();
6456 auto *M = cast<MemSDNode>(Op);
6457 M->getMemOperand()->setOffset(Offset);
6458 unsigned Opcode = 0;
6461 case Intrinsic::amdgcn_buffer_atomic_swap:
6462 Opcode = AMDGPUISD::BUFFER_ATOMIC_SWAP;
6464 case Intrinsic::amdgcn_buffer_atomic_add:
6465 Opcode = AMDGPUISD::BUFFER_ATOMIC_ADD;
6467 case Intrinsic::amdgcn_buffer_atomic_sub:
6468 Opcode = AMDGPUISD::BUFFER_ATOMIC_SUB;
6470 case Intrinsic::amdgcn_buffer_atomic_smin:
6471 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMIN;
6473 case Intrinsic::amdgcn_buffer_atomic_umin:
6474 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMIN;
6476 case Intrinsic::amdgcn_buffer_atomic_smax:
6477 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMAX;
6479 case Intrinsic::amdgcn_buffer_atomic_umax:
6480 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMAX;
6482 case Intrinsic::amdgcn_buffer_atomic_and:
6483 Opcode = AMDGPUISD::BUFFER_ATOMIC_AND;
6485 case Intrinsic::amdgcn_buffer_atomic_or:
6486 Opcode = AMDGPUISD::BUFFER_ATOMIC_OR;
6488 case Intrinsic::amdgcn_buffer_atomic_xor:
6489 Opcode = AMDGPUISD::BUFFER_ATOMIC_XOR;
6492 llvm_unreachable("unhandled atomic opcode");
6495 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
6496 M->getMemOperand());
6498 case Intrinsic::amdgcn_raw_buffer_atomic_swap:
6499 case Intrinsic::amdgcn_raw_buffer_atomic_add:
6500 case Intrinsic::amdgcn_raw_buffer_atomic_sub:
6501 case Intrinsic::amdgcn_raw_buffer_atomic_smin:
6502 case Intrinsic::amdgcn_raw_buffer_atomic_umin:
6503 case Intrinsic::amdgcn_raw_buffer_atomic_smax:
6504 case Intrinsic::amdgcn_raw_buffer_atomic_umax:
6505 case Intrinsic::amdgcn_raw_buffer_atomic_and:
6506 case Intrinsic::amdgcn_raw_buffer_atomic_or:
6507 case Intrinsic::amdgcn_raw_buffer_atomic_xor:
6508 case Intrinsic::amdgcn_raw_buffer_atomic_inc:
6509 case Intrinsic::amdgcn_raw_buffer_atomic_dec: {
6510 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6512 Op.getOperand(0), // Chain
6513 Op.getOperand(2), // vdata
6514 Op.getOperand(3), // rsrc
6515 DAG.getConstant(0, DL, MVT::i32), // vindex
6516 Offsets.first, // voffset
6517 Op.getOperand(5), // soffset
6518 Offsets.second, // offset
6519 Op.getOperand(6), // cachepolicy
6520 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6522 EVT VT = Op.getValueType();
6524 auto *M = cast<MemSDNode>(Op);
6525 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[4], Ops[5], Ops[6]));
6526 unsigned Opcode = 0;
6529 case Intrinsic::amdgcn_raw_buffer_atomic_swap:
6530 Opcode = AMDGPUISD::BUFFER_ATOMIC_SWAP;
6532 case Intrinsic::amdgcn_raw_buffer_atomic_add:
6533 Opcode = AMDGPUISD::BUFFER_ATOMIC_ADD;
6535 case Intrinsic::amdgcn_raw_buffer_atomic_sub:
6536 Opcode = AMDGPUISD::BUFFER_ATOMIC_SUB;
6538 case Intrinsic::amdgcn_raw_buffer_atomic_smin:
6539 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMIN;
6541 case Intrinsic::amdgcn_raw_buffer_atomic_umin:
6542 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMIN;
6544 case Intrinsic::amdgcn_raw_buffer_atomic_smax:
6545 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMAX;
6547 case Intrinsic::amdgcn_raw_buffer_atomic_umax:
6548 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMAX;
6550 case Intrinsic::amdgcn_raw_buffer_atomic_and:
6551 Opcode = AMDGPUISD::BUFFER_ATOMIC_AND;
6553 case Intrinsic::amdgcn_raw_buffer_atomic_or:
6554 Opcode = AMDGPUISD::BUFFER_ATOMIC_OR;
6556 case Intrinsic::amdgcn_raw_buffer_atomic_xor:
6557 Opcode = AMDGPUISD::BUFFER_ATOMIC_XOR;
6559 case Intrinsic::amdgcn_raw_buffer_atomic_inc:
6560 Opcode = AMDGPUISD::BUFFER_ATOMIC_INC;
6562 case Intrinsic::amdgcn_raw_buffer_atomic_dec:
6563 Opcode = AMDGPUISD::BUFFER_ATOMIC_DEC;
6566 llvm_unreachable("unhandled atomic opcode");
6569 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
6570 M->getMemOperand());
6572 case Intrinsic::amdgcn_struct_buffer_atomic_swap:
6573 case Intrinsic::amdgcn_struct_buffer_atomic_add:
6574 case Intrinsic::amdgcn_struct_buffer_atomic_sub:
6575 case Intrinsic::amdgcn_struct_buffer_atomic_smin:
6576 case Intrinsic::amdgcn_struct_buffer_atomic_umin:
6577 case Intrinsic::amdgcn_struct_buffer_atomic_smax:
6578 case Intrinsic::amdgcn_struct_buffer_atomic_umax:
6579 case Intrinsic::amdgcn_struct_buffer_atomic_and:
6580 case Intrinsic::amdgcn_struct_buffer_atomic_or:
6581 case Intrinsic::amdgcn_struct_buffer_atomic_xor:
6582 case Intrinsic::amdgcn_struct_buffer_atomic_inc:
6583 case Intrinsic::amdgcn_struct_buffer_atomic_dec: {
6584 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
6586 Op.getOperand(0), // Chain
6587 Op.getOperand(2), // vdata
6588 Op.getOperand(3), // rsrc
6589 Op.getOperand(4), // vindex
6590 Offsets.first, // voffset
6591 Op.getOperand(6), // soffset
6592 Offsets.second, // offset
6593 Op.getOperand(7), // cachepolicy
6594 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
6596 EVT VT = Op.getValueType();
6598 auto *M = cast<MemSDNode>(Op);
6599 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[4], Ops[5], Ops[6],
6601 unsigned Opcode = 0;
6604 case Intrinsic::amdgcn_struct_buffer_atomic_swap:
6605 Opcode = AMDGPUISD::BUFFER_ATOMIC_SWAP;
6607 case Intrinsic::amdgcn_struct_buffer_atomic_add:
6608 Opcode = AMDGPUISD::BUFFER_ATOMIC_ADD;
6610 case Intrinsic::amdgcn_struct_buffer_atomic_sub:
6611 Opcode = AMDGPUISD::BUFFER_ATOMIC_SUB;
6613 case Intrinsic::amdgcn_struct_buffer_atomic_smin:
6614 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMIN;
6616 case Intrinsic::amdgcn_struct_buffer_atomic_umin:
6617 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMIN;
6619 case Intrinsic::amdgcn_struct_buffer_atomic_smax:
6620 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMAX;
6622 case Intrinsic::amdgcn_struct_buffer_atomic_umax:
6623 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMAX;
6625 case Intrinsic::amdgcn_struct_buffer_atomic_and:
6626 Opcode = AMDGPUISD::BUFFER_ATOMIC_AND;
6628 case Intrinsic::amdgcn_struct_buffer_atomic_or:
6629 Opcode = AMDGPUISD::BUFFER_ATOMIC_OR;
6631 case Intrinsic::amdgcn_struct_buffer_atomic_xor:
6632 Opcode = AMDGPUISD::BUFFER_ATOMIC_XOR;
6634 case Intrinsic::amdgcn_struct_buffer_atomic_inc:
6635 Opcode = AMDGPUISD::BUFFER_ATOMIC_INC;
6637 case Intrinsic::amdgcn_struct_buffer_atomic_dec:
6638 Opcode = AMDGPUISD::BUFFER_ATOMIC_DEC;
6641 llvm_unreachable("unhandled atomic opcode");
6644 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
6645 M->getMemOperand());
6647 case Intrinsic::amdgcn_buffer_atomic_cmpswap: {
6648 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
6650 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(5)))
6651 IdxEn = Idx->getZExtValue() != 0;
6653 Op.getOperand(0), // Chain
6654 Op.getOperand(2), // src
6655 Op.getOperand(3), // cmp
6656 Op.getOperand(4), // rsrc
6657 Op.getOperand(5), // vindex
6658 SDValue(), // voffset -- will be set by setBufferOffsets
6659 SDValue(), // soffset -- will be set by setBufferOffsets
6660 SDValue(), // offset -- will be set by setBufferOffsets
6661 DAG.getTargetConstant(Slc << 1, DL, MVT::i32), // cachepolicy
6662 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6664 unsigned Offset = setBufferOffsets(Op.getOperand(6), DAG, &Ops[5]);
6665 // We don't know the offset if vindex is non-zero, so clear it.
6668 EVT VT = Op.getValueType();
6669 auto *M = cast<MemSDNode>(Op);
6670 M->getMemOperand()->setOffset(Offset);
6672 return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_CMPSWAP, DL,
6673 Op->getVTList(), Ops, VT, M->getMemOperand());
6675 case Intrinsic::amdgcn_raw_buffer_atomic_cmpswap: {
6676 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
6678 Op.getOperand(0), // Chain
6679 Op.getOperand(2), // src
6680 Op.getOperand(3), // cmp
6681 Op.getOperand(4), // rsrc
6682 DAG.getConstant(0, DL, MVT::i32), // vindex
6683 Offsets.first, // voffset
6684 Op.getOperand(6), // soffset
6685 Offsets.second, // offset
6686 Op.getOperand(7), // cachepolicy
6687 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6689 EVT VT = Op.getValueType();
6690 auto *M = cast<MemSDNode>(Op);
6691 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[5], Ops[6], Ops[7]));
6693 return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_CMPSWAP, DL,
6694 Op->getVTList(), Ops, VT, M->getMemOperand());
6696 case Intrinsic::amdgcn_struct_buffer_atomic_cmpswap: {
6697 auto Offsets = splitBufferOffsets(Op.getOperand(6), DAG);
6699 Op.getOperand(0), // Chain
6700 Op.getOperand(2), // src
6701 Op.getOperand(3), // cmp
6702 Op.getOperand(4), // rsrc
6703 Op.getOperand(5), // vindex
6704 Offsets.first, // voffset
6705 Op.getOperand(7), // soffset
6706 Offsets.second, // offset
6707 Op.getOperand(8), // cachepolicy
6708 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
6710 EVT VT = Op.getValueType();
6711 auto *M = cast<MemSDNode>(Op);
6712 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[5], Ops[6], Ops[7],
6715 return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_CMPSWAP, DL,
6716 Op->getVTList(), Ops, VT, M->getMemOperand());
6720 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
6721 AMDGPU::getImageDimIntrinsicInfo(IntrID))
6722 return lowerImage(Op, ImageDimIntr, DAG);
6728 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
6729 // dwordx4 if on SI.
6730 SDValue SITargetLowering::getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL,
6732 ArrayRef<SDValue> Ops, EVT MemVT,
6733 MachineMemOperand *MMO,
6734 SelectionDAG &DAG) const {
6735 EVT VT = VTList.VTs[0];
6737 EVT WidenedMemVT = MemVT;
6738 if (!Subtarget->hasDwordx3LoadStores() &&
6739 (WidenedVT == MVT::v3i32 || WidenedVT == MVT::v3f32)) {
6740 WidenedVT = EVT::getVectorVT(*DAG.getContext(),
6741 WidenedVT.getVectorElementType(), 4);
6742 WidenedMemVT = EVT::getVectorVT(*DAG.getContext(),
6743 WidenedMemVT.getVectorElementType(), 4);
6744 MMO = DAG.getMachineFunction().getMachineMemOperand(MMO, 0, 16);
6747 assert(VTList.NumVTs == 2);
6748 SDVTList WidenedVTList = DAG.getVTList(WidenedVT, VTList.VTs[1]);
6750 auto NewOp = DAG.getMemIntrinsicNode(Opcode, DL, WidenedVTList, Ops,
6752 if (WidenedVT != VT) {
6753 auto Extract = DAG.getNode(
6754 ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp,
6755 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
6756 NewOp = DAG.getMergeValues({ Extract, SDValue(NewOp.getNode(), 1) }, DL);
6761 SDValue SITargetLowering::handleD16VData(SDValue VData,
6762 SelectionDAG &DAG) const {
6763 EVT StoreVT = VData.getValueType();
6765 // No change for f16 and legal vector D16 types.
6766 if (!StoreVT.isVector())
6770 assert((StoreVT.getVectorNumElements() != 3) && "Handle v3f16");
6772 if (Subtarget->hasUnpackedD16VMem()) {
6773 // We need to unpack the packed data to store.
6774 EVT IntStoreVT = StoreVT.changeTypeToInteger();
6775 SDValue IntVData = DAG.getNode(ISD::BITCAST, DL, IntStoreVT, VData);
6777 EVT EquivStoreVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
6778 StoreVT.getVectorNumElements());
6779 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, EquivStoreVT, IntVData);
6780 return DAG.UnrollVectorOp(ZExt.getNode());
6783 assert(isTypeLegal(StoreVT));
6787 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
6788 SelectionDAG &DAG) const {
6790 SDValue Chain = Op.getOperand(0);
6791 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6792 MachineFunction &MF = DAG.getMachineFunction();
6794 switch (IntrinsicID) {
6795 case Intrinsic::amdgcn_exp: {
6796 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2));
6797 const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(3));
6798 const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(8));
6799 const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(9));
6801 const SDValue Ops[] = {
6803 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt
6804 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), // en
6805 Op.getOperand(4), // src0
6806 Op.getOperand(5), // src1
6807 Op.getOperand(6), // src2
6808 Op.getOperand(7), // src3
6809 DAG.getTargetConstant(0, DL, MVT::i1), // compr
6810 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1)
6813 unsigned Opc = Done->isNullValue() ?
6814 AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
6815 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
6817 case Intrinsic::amdgcn_exp_compr: {
6818 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2));
6819 const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(3));
6820 SDValue Src0 = Op.getOperand(4);
6821 SDValue Src1 = Op.getOperand(5);
6822 const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(6));
6823 const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(7));
6825 SDValue Undef = DAG.getUNDEF(MVT::f32);
6826 const SDValue Ops[] = {
6828 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt
6829 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), // en
6830 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0),
6831 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src1),
6834 DAG.getTargetConstant(1, DL, MVT::i1), // compr
6835 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1)
6838 unsigned Opc = Done->isNullValue() ?
6839 AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
6840 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
6842 case Intrinsic::amdgcn_s_barrier: {
6843 if (getTargetMachine().getOptLevel() > CodeGenOpt::None) {
6844 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
6845 unsigned WGSize = ST.getFlatWorkGroupSizes(MF.getFunction()).second;
6846 if (WGSize <= ST.getWavefrontSize())
6847 return SDValue(DAG.getMachineNode(AMDGPU::WAVE_BARRIER, DL, MVT::Other,
6848 Op.getOperand(0)), 0);
6852 case Intrinsic::amdgcn_tbuffer_store: {
6853 SDValue VData = Op.getOperand(2);
6854 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6856 VData = handleD16VData(VData, DAG);
6857 unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue();
6858 unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue();
6859 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(10))->getZExtValue();
6860 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(11))->getZExtValue();
6862 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
6863 IdxEn = Idx->getZExtValue() != 0;
6867 Op.getOperand(3), // rsrc
6868 Op.getOperand(4), // vindex
6869 Op.getOperand(5), // voffset
6870 Op.getOperand(6), // soffset
6871 Op.getOperand(7), // offset
6872 DAG.getTargetConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
6873 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6874 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idexen
6876 unsigned Opc = IsD16 ? AMDGPUISD::TBUFFER_STORE_FORMAT_D16 :
6877 AMDGPUISD::TBUFFER_STORE_FORMAT;
6878 MemSDNode *M = cast<MemSDNode>(Op);
6879 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6880 M->getMemoryVT(), M->getMemOperand());
6883 case Intrinsic::amdgcn_struct_tbuffer_store: {
6884 SDValue VData = Op.getOperand(2);
6885 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6887 VData = handleD16VData(VData, DAG);
6888 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
6892 Op.getOperand(3), // rsrc
6893 Op.getOperand(4), // vindex
6894 Offsets.first, // voffset
6895 Op.getOperand(6), // soffset
6896 Offsets.second, // offset
6897 Op.getOperand(7), // format
6898 Op.getOperand(8), // cachepolicy, swizzled buffer
6899 DAG.getTargetConstant(1, DL, MVT::i1), // idexen
6901 unsigned Opc = IsD16 ? AMDGPUISD::TBUFFER_STORE_FORMAT_D16 :
6902 AMDGPUISD::TBUFFER_STORE_FORMAT;
6903 MemSDNode *M = cast<MemSDNode>(Op);
6904 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6905 M->getMemoryVT(), M->getMemOperand());
6908 case Intrinsic::amdgcn_raw_tbuffer_store: {
6909 SDValue VData = Op.getOperand(2);
6910 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6912 VData = handleD16VData(VData, DAG);
6913 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6917 Op.getOperand(3), // rsrc
6918 DAG.getConstant(0, DL, MVT::i32), // vindex
6919 Offsets.first, // voffset
6920 Op.getOperand(5), // soffset
6921 Offsets.second, // offset
6922 Op.getOperand(6), // format
6923 Op.getOperand(7), // cachepolicy, swizzled buffer
6924 DAG.getTargetConstant(0, DL, MVT::i1), // idexen
6926 unsigned Opc = IsD16 ? AMDGPUISD::TBUFFER_STORE_FORMAT_D16 :
6927 AMDGPUISD::TBUFFER_STORE_FORMAT;
6928 MemSDNode *M = cast<MemSDNode>(Op);
6929 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6930 M->getMemoryVT(), M->getMemOperand());
6933 case Intrinsic::amdgcn_buffer_store:
6934 case Intrinsic::amdgcn_buffer_store_format: {
6935 SDValue VData = Op.getOperand(2);
6936 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6938 VData = handleD16VData(VData, DAG);
6939 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
6940 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
6942 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
6943 IdxEn = Idx->getZExtValue() != 0;
6947 Op.getOperand(3), // rsrc
6948 Op.getOperand(4), // vindex
6949 SDValue(), // voffset -- will be set by setBufferOffsets
6950 SDValue(), // soffset -- will be set by setBufferOffsets
6951 SDValue(), // offset -- will be set by setBufferOffsets
6952 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6953 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6955 unsigned Offset = setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
6956 // We don't know the offset if vindex is non-zero, so clear it.
6959 unsigned Opc = IntrinsicID == Intrinsic::amdgcn_buffer_store ?
6960 AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
6961 Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
6962 MemSDNode *M = cast<MemSDNode>(Op);
6963 M->getMemOperand()->setOffset(Offset);
6965 // Handle BUFFER_STORE_BYTE/SHORT overloaded intrinsics
6966 EVT VDataType = VData.getValueType().getScalarType();
6967 if (VDataType == MVT::i8 || VDataType == MVT::i16)
6968 return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
6970 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6971 M->getMemoryVT(), M->getMemOperand());
6974 case Intrinsic::amdgcn_raw_buffer_store:
6975 case Intrinsic::amdgcn_raw_buffer_store_format: {
6976 const bool IsFormat =
6977 IntrinsicID == Intrinsic::amdgcn_raw_buffer_store_format;
6979 SDValue VData = Op.getOperand(2);
6980 EVT VDataVT = VData.getValueType();
6981 EVT EltType = VDataVT.getScalarType();
6982 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
6984 VData = handleD16VData(VData, DAG);
6986 if (!isTypeLegal(VDataVT)) {
6988 DAG.getNode(ISD::BITCAST, DL,
6989 getEquivalentMemType(*DAG.getContext(), VDataVT), VData);
6992 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6996 Op.getOperand(3), // rsrc
6997 DAG.getConstant(0, DL, MVT::i32), // vindex
6998 Offsets.first, // voffset
6999 Op.getOperand(5), // soffset
7000 Offsets.second, // offset
7001 Op.getOperand(6), // cachepolicy, swizzled buffer
7002 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
7005 IsFormat ? AMDGPUISD::BUFFER_STORE_FORMAT : AMDGPUISD::BUFFER_STORE;
7006 Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
7007 MemSDNode *M = cast<MemSDNode>(Op);
7008 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[4], Ops[5], Ops[6]));
7010 // Handle BUFFER_STORE_BYTE/SHORT overloaded intrinsics
7011 if (!IsD16 && !VDataVT.isVector() && EltType.getSizeInBits() < 32)
7012 return handleByteShortBufferStores(DAG, VDataVT, DL, Ops, M);
7014 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
7015 M->getMemoryVT(), M->getMemOperand());
7018 case Intrinsic::amdgcn_struct_buffer_store:
7019 case Intrinsic::amdgcn_struct_buffer_store_format: {
7020 const bool IsFormat =
7021 IntrinsicID == Intrinsic::amdgcn_struct_buffer_store_format;
7023 SDValue VData = Op.getOperand(2);
7024 EVT VDataVT = VData.getValueType();
7025 EVT EltType = VDataVT.getScalarType();
7026 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
7029 VData = handleD16VData(VData, DAG);
7031 if (!isTypeLegal(VDataVT)) {
7033 DAG.getNode(ISD::BITCAST, DL,
7034 getEquivalentMemType(*DAG.getContext(), VDataVT), VData);
7037 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
7041 Op.getOperand(3), // rsrc
7042 Op.getOperand(4), // vindex
7043 Offsets.first, // voffset
7044 Op.getOperand(6), // soffset
7045 Offsets.second, // offset
7046 Op.getOperand(7), // cachepolicy, swizzled buffer
7047 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
7049 unsigned Opc = IntrinsicID == Intrinsic::amdgcn_struct_buffer_store ?
7050 AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
7051 Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
7052 MemSDNode *M = cast<MemSDNode>(Op);
7053 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[4], Ops[5], Ops[6],
7056 // Handle BUFFER_STORE_BYTE/SHORT overloaded intrinsics
7057 EVT VDataType = VData.getValueType().getScalarType();
7058 if (!IsD16 && !VDataVT.isVector() && EltType.getSizeInBits() < 32)
7059 return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
7061 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
7062 M->getMemoryVT(), M->getMemOperand());
7065 case Intrinsic::amdgcn_buffer_atomic_fadd: {
7066 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
7068 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
7069 IdxEn = Idx->getZExtValue() != 0;
7072 Op.getOperand(2), // vdata
7073 Op.getOperand(3), // rsrc
7074 Op.getOperand(4), // vindex
7075 SDValue(), // voffset -- will be set by setBufferOffsets
7076 SDValue(), // soffset -- will be set by setBufferOffsets
7077 SDValue(), // offset -- will be set by setBufferOffsets
7078 DAG.getTargetConstant(Slc << 1, DL, MVT::i32), // cachepolicy
7079 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
7081 unsigned Offset = setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
7082 // We don't know the offset if vindex is non-zero, so clear it.
7085 EVT VT = Op.getOperand(2).getValueType();
7087 auto *M = cast<MemSDNode>(Op);
7088 M->getMemOperand()->setOffset(Offset);
7089 unsigned Opcode = VT.isVector() ? AMDGPUISD::BUFFER_ATOMIC_PK_FADD
7090 : AMDGPUISD::BUFFER_ATOMIC_FADD;
7092 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
7093 M->getMemOperand());
7096 case Intrinsic::amdgcn_global_atomic_fadd: {
7099 Op.getOperand(2), // ptr
7100 Op.getOperand(3) // vdata
7102 EVT VT = Op.getOperand(3).getValueType();
7104 auto *M = cast<MemSDNode>(Op);
7105 if (VT.isVector()) {
7106 return DAG.getMemIntrinsicNode(
7107 AMDGPUISD::ATOMIC_PK_FADD, DL, Op->getVTList(), Ops, VT,
7108 M->getMemOperand());
7111 return DAG.getAtomic(ISD::ATOMIC_LOAD_FADD, DL, VT,
7112 DAG.getVTList(VT, MVT::Other), Ops,
7113 M->getMemOperand()).getValue(1);
7115 case Intrinsic::amdgcn_end_cf:
7116 return SDValue(DAG.getMachineNode(AMDGPU::SI_END_CF, DL, MVT::Other,
7117 Op->getOperand(2), Chain), 0);
7120 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
7121 AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
7122 return lowerImage(Op, ImageDimIntr, DAG);
7129 // The raw.(t)buffer and struct.(t)buffer intrinsics have two offset args:
7130 // offset (the offset that is included in bounds checking and swizzling, to be
7131 // split between the instruction's voffset and immoffset fields) and soffset
7132 // (the offset that is excluded from bounds checking and swizzling, to go in
7133 // the instruction's soffset field). This function takes the first kind of
7134 // offset and figures out how to split it between voffset and immoffset.
7135 std::pair<SDValue, SDValue> SITargetLowering::splitBufferOffsets(
7136 SDValue Offset, SelectionDAG &DAG) const {
7138 const unsigned MaxImm = 4095;
7139 SDValue N0 = Offset;
7140 ConstantSDNode *C1 = nullptr;
7142 if ((C1 = dyn_cast<ConstantSDNode>(N0)))
7144 else if (DAG.isBaseWithConstantOffset(N0)) {
7145 C1 = cast<ConstantSDNode>(N0.getOperand(1));
7146 N0 = N0.getOperand(0);
7150 unsigned ImmOffset = C1->getZExtValue();
7151 // If the immediate value is too big for the immoffset field, put the value
7152 // and -4096 into the immoffset field so that the value that is copied/added
7153 // for the voffset field is a multiple of 4096, and it stands more chance
7154 // of being CSEd with the copy/add for another similar load/store.
7155 // However, do not do that rounding down to a multiple of 4096 if that is a
7156 // negative number, as it appears to be illegal to have a negative offset
7157 // in the vgpr, even if adding the immediate offset makes it positive.
7158 unsigned Overflow = ImmOffset & ~MaxImm;
7159 ImmOffset -= Overflow;
7160 if ((int32_t)Overflow < 0) {
7161 Overflow += ImmOffset;
7164 C1 = cast<ConstantSDNode>(DAG.getTargetConstant(ImmOffset, DL, MVT::i32));
7166 auto OverflowVal = DAG.getConstant(Overflow, DL, MVT::i32);
7170 SDValue Ops[] = { N0, OverflowVal };
7171 N0 = DAG.getNode(ISD::ADD, DL, MVT::i32, Ops);
7176 N0 = DAG.getConstant(0, DL, MVT::i32);
7178 C1 = cast<ConstantSDNode>(DAG.getTargetConstant(0, DL, MVT::i32));
7179 return {N0, SDValue(C1, 0)};
7182 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
7183 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
7184 // pointed to by Offsets.
7185 unsigned SITargetLowering::setBufferOffsets(SDValue CombinedOffset,
7186 SelectionDAG &DAG, SDValue *Offsets,
7187 unsigned Align) const {
7188 SDLoc DL(CombinedOffset);
7189 if (auto C = dyn_cast<ConstantSDNode>(CombinedOffset)) {
7190 uint32_t Imm = C->getZExtValue();
7191 uint32_t SOffset, ImmOffset;
7192 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, Align)) {
7193 Offsets[0] = DAG.getConstant(0, DL, MVT::i32);
7194 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32);
7195 Offsets[2] = DAG.getTargetConstant(ImmOffset, DL, MVT::i32);
7196 return SOffset + ImmOffset;
7199 if (DAG.isBaseWithConstantOffset(CombinedOffset)) {
7200 SDValue N0 = CombinedOffset.getOperand(0);
7201 SDValue N1 = CombinedOffset.getOperand(1);
7202 uint32_t SOffset, ImmOffset;
7203 int Offset = cast<ConstantSDNode>(N1)->getSExtValue();
7204 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset,
7205 Subtarget, Align)) {
7207 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32);
7208 Offsets[2] = DAG.getTargetConstant(ImmOffset, DL, MVT::i32);
7212 Offsets[0] = CombinedOffset;
7213 Offsets[1] = DAG.getConstant(0, DL, MVT::i32);
7214 Offsets[2] = DAG.getTargetConstant(0, DL, MVT::i32);
7218 // Handle 8 bit and 16 bit buffer loads
7219 SDValue SITargetLowering::handleByteShortBufferLoads(SelectionDAG &DAG,
7220 EVT LoadVT, SDLoc DL,
7221 ArrayRef<SDValue> Ops,
7222 MemSDNode *M) const {
7223 EVT IntVT = LoadVT.changeTypeToInteger();
7224 unsigned Opc = (LoadVT.getScalarType() == MVT::i8) ?
7225 AMDGPUISD::BUFFER_LOAD_UBYTE : AMDGPUISD::BUFFER_LOAD_USHORT;
7227 SDVTList ResList = DAG.getVTList(MVT::i32, MVT::Other);
7228 SDValue BufferLoad = DAG.getMemIntrinsicNode(Opc, DL, ResList,
7230 M->getMemOperand());
7231 SDValue LoadVal = DAG.getNode(ISD::TRUNCATE, DL, IntVT, BufferLoad);
7232 LoadVal = DAG.getNode(ISD::BITCAST, DL, LoadVT, LoadVal);
7234 return DAG.getMergeValues({LoadVal, BufferLoad.getValue(1)}, DL);
7237 // Handle 8 bit and 16 bit buffer stores
7238 SDValue SITargetLowering::handleByteShortBufferStores(SelectionDAG &DAG,
7239 EVT VDataType, SDLoc DL,
7241 MemSDNode *M) const {
7242 if (VDataType == MVT::f16)
7243 Ops[1] = DAG.getNode(ISD::BITCAST, DL, MVT::i16, Ops[1]);
7245 SDValue BufferStoreExt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Ops[1]);
7246 Ops[1] = BufferStoreExt;
7247 unsigned Opc = (VDataType == MVT::i8) ? AMDGPUISD::BUFFER_STORE_BYTE :
7248 AMDGPUISD::BUFFER_STORE_SHORT;
7249 ArrayRef<SDValue> OpsRef = makeArrayRef(&Ops[0], 9);
7250 return DAG.getMemIntrinsicNode(Opc, DL, M->getVTList(), OpsRef, VDataType,
7251 M->getMemOperand());
7254 static SDValue getLoadExtOrTrunc(SelectionDAG &DAG,
7255 ISD::LoadExtType ExtType, SDValue Op,
7256 const SDLoc &SL, EVT VT) {
7257 if (VT.bitsLT(Op.getValueType()))
7258 return DAG.getNode(ISD::TRUNCATE, SL, VT, Op);
7262 return DAG.getNode(ISD::SIGN_EXTEND, SL, VT, Op);
7264 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, Op);
7266 return DAG.getNode(ISD::ANY_EXTEND, SL, VT, Op);
7267 case ISD::NON_EXTLOAD:
7271 llvm_unreachable("invalid ext type");
7274 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const {
7275 SelectionDAG &DAG = DCI.DAG;
7276 if (Ld->getAlignment() < 4 || Ld->isDivergent())
7279 // FIXME: Constant loads should all be marked invariant.
7280 unsigned AS = Ld->getAddressSpace();
7281 if (AS != AMDGPUAS::CONSTANT_ADDRESS &&
7282 AS != AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
7283 (AS != AMDGPUAS::GLOBAL_ADDRESS || !Ld->isInvariant()))
7286 // Don't do this early, since it may interfere with adjacent load merging for
7287 // illegal types. We can avoid losing alignment information for exotic types
7289 EVT MemVT = Ld->getMemoryVT();
7290 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) ||
7291 MemVT.getSizeInBits() >= 32)
7296 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) &&
7297 "unexpected vector extload");
7299 // TODO: Drop only high part of range.
7300 SDValue Ptr = Ld->getBasePtr();
7301 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
7302 MVT::i32, SL, Ld->getChain(), Ptr,
7304 Ld->getPointerInfo(), MVT::i32,
7306 Ld->getMemOperand()->getFlags(),
7308 nullptr); // Drop ranges
7310 EVT TruncVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
7311 if (MemVT.isFloatingPoint()) {
7312 assert(Ld->getExtensionType() == ISD::NON_EXTLOAD &&
7313 "unexpected fp extload");
7314 TruncVT = MemVT.changeTypeToInteger();
7317 SDValue Cvt = NewLoad;
7318 if (Ld->getExtensionType() == ISD::SEXTLOAD) {
7319 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad,
7320 DAG.getValueType(TruncVT));
7321 } else if (Ld->getExtensionType() == ISD::ZEXTLOAD ||
7322 Ld->getExtensionType() == ISD::NON_EXTLOAD) {
7323 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT);
7325 assert(Ld->getExtensionType() == ISD::EXTLOAD);
7328 EVT VT = Ld->getValueType(0);
7329 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7331 DCI.AddToWorklist(Cvt.getNode());
7333 // We may need to handle exotic cases, such as i16->i64 extloads, so insert
7334 // the appropriate extension from the 32-bit load.
7335 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT);
7336 DCI.AddToWorklist(Cvt.getNode());
7338 // Handle conversion back to floating point if necessary.
7339 Cvt = DAG.getNode(ISD::BITCAST, SL, VT, Cvt);
7341 return DAG.getMergeValues({ Cvt, NewLoad.getValue(1) }, SL);
7344 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
7346 LoadSDNode *Load = cast<LoadSDNode>(Op);
7347 ISD::LoadExtType ExtType = Load->getExtensionType();
7348 EVT MemVT = Load->getMemoryVT();
7350 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
7351 if (MemVT == MVT::i16 && isTypeLegal(MVT::i16))
7354 // FIXME: Copied from PPC
7355 // First, load into 32 bits, then truncate to 1 bit.
7357 SDValue Chain = Load->getChain();
7358 SDValue BasePtr = Load->getBasePtr();
7359 MachineMemOperand *MMO = Load->getMemOperand();
7361 EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
7363 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
7364 BasePtr, RealMemVT, MMO);
7366 if (!MemVT.isVector()) {
7368 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD),
7372 return DAG.getMergeValues(Ops, DL);
7375 SmallVector<SDValue, 3> Elts;
7376 for (unsigned I = 0, N = MemVT.getVectorNumElements(); I != N; ++I) {
7377 SDValue Elt = DAG.getNode(ISD::SRL, DL, MVT::i32, NewLD,
7378 DAG.getConstant(I, DL, MVT::i32));
7380 Elts.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Elt));
7384 DAG.getBuildVector(MemVT, DL, Elts),
7388 return DAG.getMergeValues(Ops, DL);
7391 if (!MemVT.isVector())
7394 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
7395 "Custom lowering for non-i32 vectors hasn't been implemented.");
7397 if (!allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
7398 MemVT, *Load->getMemOperand())) {
7400 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
7401 return DAG.getMergeValues(Ops, DL);
7404 unsigned Alignment = Load->getAlignment();
7405 unsigned AS = Load->getAddressSpace();
7406 if (Subtarget->hasLDSMisalignedBug() &&
7407 AS == AMDGPUAS::FLAT_ADDRESS &&
7408 Alignment < MemVT.getStoreSize() && MemVT.getSizeInBits() > 32) {
7409 return SplitVectorLoad(Op, DAG);
7412 MachineFunction &MF = DAG.getMachineFunction();
7413 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
7414 // If there is a possibilty that flat instruction access scratch memory
7415 // then we need to use the same legalization rules we use for private.
7416 if (AS == AMDGPUAS::FLAT_ADDRESS)
7417 AS = MFI->hasFlatScratchInit() ?
7418 AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
7420 unsigned NumElements = MemVT.getVectorNumElements();
7422 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
7423 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
7424 if (!Op->isDivergent() && Alignment >= 4 && NumElements < 32) {
7425 if (MemVT.isPow2VectorType())
7427 if (NumElements == 3)
7428 return WidenVectorLoad(Op, DAG);
7429 return SplitVectorLoad(Op, DAG);
7431 // Non-uniform loads will be selected to MUBUF instructions, so they
7432 // have the same legalization requirements as global and private
7437 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
7438 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
7439 AS == AMDGPUAS::GLOBAL_ADDRESS) {
7440 if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&
7441 !Load->isVolatile() && isMemOpHasNoClobberedMemOperand(Load) &&
7442 Alignment >= 4 && NumElements < 32) {
7443 if (MemVT.isPow2VectorType())
7445 if (NumElements == 3)
7446 return WidenVectorLoad(Op, DAG);
7447 return SplitVectorLoad(Op, DAG);
7449 // Non-uniform loads will be selected to MUBUF instructions, so they
7450 // have the same legalization requirements as global and private
7454 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
7455 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
7456 AS == AMDGPUAS::GLOBAL_ADDRESS ||
7457 AS == AMDGPUAS::FLAT_ADDRESS) {
7458 if (NumElements > 4)
7459 return SplitVectorLoad(Op, DAG);
7460 // v3 loads not supported on SI.
7461 if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores())
7462 return WidenVectorLoad(Op, DAG);
7463 // v3 and v4 loads are supported for private and global memory.
7466 if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
7467 // Depending on the setting of the private_element_size field in the
7468 // resource descriptor, we can only make private accesses up to a certain
7470 switch (Subtarget->getMaxPrivateElementSize()) {
7473 std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(Load, DAG);
7474 return DAG.getMergeValues(Ops, DL);
7477 if (NumElements > 2)
7478 return SplitVectorLoad(Op, DAG);
7481 // Same as global/flat
7482 if (NumElements > 4)
7483 return SplitVectorLoad(Op, DAG);
7484 // v3 loads not supported on SI.
7485 if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores())
7486 return WidenVectorLoad(Op, DAG);
7489 llvm_unreachable("unsupported private_element_size");
7491 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
7492 // Use ds_read_b128 if possible.
7493 if (Subtarget->useDS128() && Load->getAlignment() >= 16 &&
7494 MemVT.getStoreSize() == 16)
7497 if (NumElements > 2)
7498 return SplitVectorLoad(Op, DAG);
7500 // SI has a hardware bug in the LDS / GDS boounds checking: if the base
7501 // address is negative, then the instruction is incorrectly treated as
7502 // out-of-bounds even if base + offsets is in bounds. Split vectorized
7503 // loads here to avoid emitting ds_read2_b32. We may re-combine the
7504 // load later in the SILoadStoreOptimizer.
7505 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
7506 NumElements == 2 && MemVT.getStoreSize() == 8 &&
7507 Load->getAlignment() < 8) {
7508 return SplitVectorLoad(Op, DAG);
7514 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7515 EVT VT = Op.getValueType();
7516 assert(VT.getSizeInBits() == 64);
7519 SDValue Cond = Op.getOperand(0);
7521 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
7522 SDValue One = DAG.getConstant(1, DL, MVT::i32);
7524 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
7525 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
7527 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
7528 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
7530 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
7532 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
7533 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
7535 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
7537 SDValue Res = DAG.getBuildVector(MVT::v2i32, DL, {Lo, Hi});
7538 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
7541 // Catch division cases where we can use shortcuts with rcp and rsq
7543 SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
7544 SelectionDAG &DAG) const {
7546 SDValue LHS = Op.getOperand(0);
7547 SDValue RHS = Op.getOperand(1);
7548 EVT VT = Op.getValueType();
7549 const SDNodeFlags Flags = Op->getFlags();
7550 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath || Flags.hasAllowReciprocal();
7552 if (!Unsafe && VT == MVT::f32 && hasFP32Denormals(DAG.getMachineFunction()))
7555 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
7556 if (Unsafe || VT == MVT::f32 || VT == MVT::f16) {
7557 if (CLHS->isExactlyValue(1.0)) {
7558 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
7559 // the CI documentation has a worst case error of 1 ulp.
7560 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
7561 // use it as long as we aren't trying to use denormals.
7563 // v_rcp_f16 and v_rsq_f16 DO support denormals.
7565 // 1.0 / sqrt(x) -> rsq(x)
7567 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
7568 // error seems really high at 2^29 ULP.
7569 if (RHS.getOpcode() == ISD::FSQRT)
7570 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
7572 // 1.0 / x -> rcp(x)
7573 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
7576 // Same as for 1.0, but expand the sign out of the constant.
7577 if (CLHS->isExactlyValue(-1.0)) {
7578 // -1.0 / x -> rcp (fneg x)
7579 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
7580 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS);
7586 // Turn into multiply by the reciprocal.
7587 // x / y -> x * (1.0 / y)
7588 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
7589 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags);
7595 static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
7596 EVT VT, SDValue A, SDValue B, SDValue GlueChain) {
7597 if (GlueChain->getNumValues() <= 1) {
7598 return DAG.getNode(Opcode, SL, VT, A, B);
7601 assert(GlueChain->getNumValues() == 3);
7603 SDVTList VTList = DAG.getVTList(VT, MVT::Other, MVT::Glue);
7605 default: llvm_unreachable("no chain equivalent for opcode");
7607 Opcode = AMDGPUISD::FMUL_W_CHAIN;
7611 return DAG.getNode(Opcode, SL, VTList, GlueChain.getValue(1), A, B,
7612 GlueChain.getValue(2));
7615 static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
7616 EVT VT, SDValue A, SDValue B, SDValue C,
7617 SDValue GlueChain) {
7618 if (GlueChain->getNumValues() <= 1) {
7619 return DAG.getNode(Opcode, SL, VT, A, B, C);
7622 assert(GlueChain->getNumValues() == 3);
7624 SDVTList VTList = DAG.getVTList(VT, MVT::Other, MVT::Glue);
7626 default: llvm_unreachable("no chain equivalent for opcode");
7628 Opcode = AMDGPUISD::FMA_W_CHAIN;
7632 return DAG.getNode(Opcode, SL, VTList, GlueChain.getValue(1), A, B, C,
7633 GlueChain.getValue(2));
7636 SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
7637 if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
7641 SDValue Src0 = Op.getOperand(0);
7642 SDValue Src1 = Op.getOperand(1);
7644 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
7645 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
7647 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1);
7648 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
7650 SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32);
7651 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
7653 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
7656 // Faster 2.5 ULP division that does not support denormals.
7657 SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
7659 SDValue LHS = Op.getOperand(1);
7660 SDValue RHS = Op.getOperand(2);
7662 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
7664 const APFloat K0Val(BitsToFloat(0x6f800000));
7665 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
7667 const APFloat K1Val(BitsToFloat(0x2f800000));
7668 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
7670 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
7673 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
7675 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
7677 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
7679 // TODO: Should this propagate fast-math-flags?
7680 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
7682 // rcp does not support denormals.
7683 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
7685 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
7687 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
7690 // Returns immediate value for setting the F32 denorm mode when using the
7691 // S_DENORM_MODE instruction.
7692 static const SDValue getSPDenormModeValue(int SPDenormMode, SelectionDAG &DAG,
7693 const SDLoc &SL, const GCNSubtarget *ST) {
7694 assert(ST->hasDenormModeInst() && "Requires S_DENORM_MODE");
7695 int DPDenormModeDefault = hasFP64FP16Denormals(DAG.getMachineFunction())
7696 ? FP_DENORM_FLUSH_NONE
7697 : FP_DENORM_FLUSH_IN_FLUSH_OUT;
7699 int Mode = SPDenormMode | (DPDenormModeDefault << 2);
7700 return DAG.getTargetConstant(Mode, SL, MVT::i32);
7703 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
7704 if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
7708 SDValue LHS = Op.getOperand(0);
7709 SDValue RHS = Op.getOperand(1);
7711 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
7713 SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
7715 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
7717 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
7720 // Denominator is scaled to not be denormal, so using rcp is ok.
7721 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32,
7723 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
7726 const unsigned Denorm32Reg = AMDGPU::Hwreg::ID_MODE |
7727 (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) |
7728 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_);
7729 const SDValue BitField = DAG.getTargetConstant(Denorm32Reg, SL, MVT::i16);
7731 const bool HasFP32Denormals = hasFP32Denormals(DAG.getMachineFunction());
7733 if (!HasFP32Denormals) {
7734 SDVTList BindParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
7736 SDValue EnableDenorm;
7737 if (Subtarget->hasDenormModeInst()) {
7738 const SDValue EnableDenormValue =
7739 getSPDenormModeValue(FP_DENORM_FLUSH_NONE, DAG, SL, Subtarget);
7741 EnableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, BindParamVTs,
7742 DAG.getEntryNode(), EnableDenormValue);
7744 const SDValue EnableDenormValue = DAG.getConstant(FP_DENORM_FLUSH_NONE,
7746 EnableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, BindParamVTs,
7747 DAG.getEntryNode(), EnableDenormValue,
7753 EnableDenorm.getValue(0),
7754 EnableDenorm.getValue(1)
7757 NegDivScale0 = DAG.getMergeValues(Ops, SL);
7760 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
7761 ApproxRcp, One, NegDivScale0);
7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp,
7766 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled,
7769 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul,
7770 NumeratorScaled, Mul);
7772 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul, Fma2);
7774 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
7775 NumeratorScaled, Fma3);
7777 if (!HasFP32Denormals) {
7778 SDValue DisableDenorm;
7779 if (Subtarget->hasDenormModeInst()) {
7780 const SDValue DisableDenormValue =
7781 getSPDenormModeValue(FP_DENORM_FLUSH_IN_FLUSH_OUT, DAG, SL, Subtarget);
7783 DisableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, MVT::Other,
7784 Fma4.getValue(1), DisableDenormValue,
7787 const SDValue DisableDenormValue =
7788 DAG.getConstant(FP_DENORM_FLUSH_IN_FLUSH_OUT, SL, MVT::i32);
7790 DisableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, MVT::Other,
7791 Fma4.getValue(1), DisableDenormValue,
7792 BitField, Fma4.getValue(2));
7795 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
7796 DisableDenorm, DAG.getRoot());
7797 DAG.setRoot(OutputChain);
7800 SDValue Scale = NumeratorScaled.getValue(1);
7801 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32,
7802 Fma4, Fma1, Fma3, Scale);
7804 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
7807 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
7808 if (DAG.getTarget().Options.UnsafeFPMath)
7809 return lowerFastUnsafeFDIV(Op, DAG);
7812 SDValue X = Op.getOperand(0);
7813 SDValue Y = Op.getOperand(1);
7815 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
7817 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
7819 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
7821 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
7823 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
7825 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
7827 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
7829 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
7831 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
7833 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
7834 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
7836 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
7837 NegDivScale0, Mul, DivScale1);
7841 if (!Subtarget->hasUsableDivScaleConditionOutput()) {
7842 // Workaround a hardware bug on SI where the condition output from div_scale
7845 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
7847 // Figure out if the scale to use for div_fmas.
7848 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
7849 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
7850 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
7851 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
7853 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
7854 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
7857 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
7859 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
7861 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
7862 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
7863 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
7865 Scale = DivScale1.getValue(1);
7868 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
7869 Fma4, Fma3, Mul, Scale);
7871 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
7874 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
7875 EVT VT = Op.getValueType();
7878 return LowerFDIV32(Op, DAG);
7881 return LowerFDIV64(Op, DAG);
7884 return LowerFDIV16(Op, DAG);
7886 llvm_unreachable("Unexpected type for fdiv");
7889 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
7891 StoreSDNode *Store = cast<StoreSDNode>(Op);
7892 EVT VT = Store->getMemoryVT();
7894 if (VT == MVT::i1) {
7895 return DAG.getTruncStore(Store->getChain(), DL,
7896 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
7897 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
7900 assert(VT.isVector() &&
7901 Store->getValue().getValueType().getScalarType() == MVT::i32);
7903 if (!allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
7904 VT, *Store->getMemOperand())) {
7905 return expandUnalignedStore(Store, DAG);
7908 unsigned AS = Store->getAddressSpace();
7909 if (Subtarget->hasLDSMisalignedBug() &&
7910 AS == AMDGPUAS::FLAT_ADDRESS &&
7911 Store->getAlignment() < VT.getStoreSize() && VT.getSizeInBits() > 32) {
7912 return SplitVectorStore(Op, DAG);
7915 MachineFunction &MF = DAG.getMachineFunction();
7916 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
7917 // If there is a possibilty that flat instruction access scratch memory
7918 // then we need to use the same legalization rules we use for private.
7919 if (AS == AMDGPUAS::FLAT_ADDRESS)
7920 AS = MFI->hasFlatScratchInit() ?
7921 AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
7923 unsigned NumElements = VT.getVectorNumElements();
7924 if (AS == AMDGPUAS::GLOBAL_ADDRESS ||
7925 AS == AMDGPUAS::FLAT_ADDRESS) {
7926 if (NumElements > 4)
7927 return SplitVectorStore(Op, DAG);
7928 // v3 stores not supported on SI.
7929 if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores())
7930 return SplitVectorStore(Op, DAG);
7932 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
7933 switch (Subtarget->getMaxPrivateElementSize()) {
7935 return scalarizeVectorStore(Store, DAG);
7937 if (NumElements > 2)
7938 return SplitVectorStore(Op, DAG);
7941 if (NumElements > 4 || NumElements == 3)
7942 return SplitVectorStore(Op, DAG);
7945 llvm_unreachable("unsupported private_element_size");
7947 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
7948 // Use ds_write_b128 if possible.
7949 if (Subtarget->useDS128() && Store->getAlignment() >= 16 &&
7950 VT.getStoreSize() == 16 && NumElements != 3)
7953 if (NumElements > 2)
7954 return SplitVectorStore(Op, DAG);
7956 // SI has a hardware bug in the LDS / GDS boounds checking: if the base
7957 // address is negative, then the instruction is incorrectly treated as
7958 // out-of-bounds even if base + offsets is in bounds. Split vectorized
7959 // stores here to avoid emitting ds_write2_b32. We may re-combine the
7960 // store later in the SILoadStoreOptimizer.
7961 if (!Subtarget->hasUsableDSOffset() &&
7962 NumElements == 2 && VT.getStoreSize() == 8 &&
7963 Store->getAlignment() < 8) {
7964 return SplitVectorStore(Op, DAG);
7969 llvm_unreachable("unhandled address space");
7973 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
7975 EVT VT = Op.getValueType();
7976 SDValue Arg = Op.getOperand(0);
7979 // TODO: Should this propagate fast-math-flags?
7981 SDValue OneOver2Pi = DAG.getConstantFP(0.5 / M_PI, DL, VT);
7983 if (Subtarget->hasTrigReducedRange()) {
7984 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi);
7985 TrigVal = DAG.getNode(AMDGPUISD::FRACT, DL, VT, MulVal);
7987 TrigVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi);
7990 switch (Op.getOpcode()) {
7992 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, TrigVal);
7994 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, TrigVal);
7996 llvm_unreachable("Wrong trig opcode");
8000 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8001 AtomicSDNode *AtomicNode = cast<AtomicSDNode>(Op);
8002 assert(AtomicNode->isCompareAndSwap());
8003 unsigned AS = AtomicNode->getAddressSpace();
8005 // No custom lowering required for local address space
8006 if (!isFlatGlobalAddrSpace(AS))
8009 // Non-local address space requires custom lowering for atomic compare
8010 // and swap; cmp and swap should be in a v2i32 or v2i64 in case of _X2
8012 SDValue ChainIn = Op.getOperand(0);
8013 SDValue Addr = Op.getOperand(1);
8014 SDValue Old = Op.getOperand(2);
8015 SDValue New = Op.getOperand(3);
8016 EVT VT = Op.getValueType();
8017 MVT SimpleVT = VT.getSimpleVT();
8018 MVT VecType = MVT::getVectorVT(SimpleVT, 2);
8020 SDValue NewOld = DAG.getBuildVector(VecType, DL, {New, Old});
8021 SDValue Ops[] = { ChainIn, Addr, NewOld };
8023 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
8024 Ops, VT, AtomicNode->getMemOperand());
8027 //===----------------------------------------------------------------------===//
8028 // Custom DAG optimizations
8029 //===----------------------------------------------------------------------===//
8031 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
8032 DAGCombinerInfo &DCI) const {
8033 EVT VT = N->getValueType(0);
8034 EVT ScalarVT = VT.getScalarType();
8035 if (ScalarVT != MVT::f32)
8038 SelectionDAG &DAG = DCI.DAG;
8041 SDValue Src = N->getOperand(0);
8042 EVT SrcVT = Src.getValueType();
8044 // TODO: We could try to match extracting the higher bytes, which would be
8045 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
8046 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
8047 // about in practice.
8048 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) {
8049 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
8050 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
8051 DCI.AddToWorklist(Cvt.getNode());
8059 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
8061 // This is a variant of
8062 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
8064 // The normal DAG combiner will do this, but only if the add has one use since
8065 // that would increase the number of instructions.
8067 // This prevents us from seeing a constant offset that can be folded into a
8068 // memory instruction's addressing mode. If we know the resulting add offset of
8069 // a pointer can be folded into an addressing offset, we can replace the pointer
8070 // operand with the add of new constant offset. This eliminates one of the uses,
8071 // and may allow the remaining use to also be simplified.
8073 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
8076 DAGCombinerInfo &DCI) const {
8077 SDValue N0 = N->getOperand(0);
8078 SDValue N1 = N->getOperand(1);
8080 // We only do this to handle cases where it's profitable when there are
8081 // multiple uses of the add, so defer to the standard combine.
8082 if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
8086 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
8090 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
8094 // If the resulting offset is too large, we can't fold it into the addressing
8096 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
8097 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext());
8100 AM.HasBaseReg = true;
8101 AM.BaseOffs = Offset.getSExtValue();
8102 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace))
8105 SelectionDAG &DAG = DCI.DAG;
8107 EVT VT = N->getValueType(0);
8109 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
8110 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
8113 Flags.setNoUnsignedWrap(N->getFlags().hasNoUnsignedWrap() &&
8114 (N0.getOpcode() == ISD::OR ||
8115 N0->getFlags().hasNoUnsignedWrap()));
8117 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset, Flags);
8120 SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
8121 DAGCombinerInfo &DCI) const {
8122 SDValue Ptr = N->getBasePtr();
8123 SelectionDAG &DAG = DCI.DAG;
8126 // TODO: We could also do this for multiplies.
8127 if (Ptr.getOpcode() == ISD::SHL) {
8128 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), N->getAddressSpace(),
8129 N->getMemoryVT(), DCI);
8131 SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
8133 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
8134 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
8141 static bool bitOpWithConstantIsReducible(unsigned Opc, uint32_t Val) {
8142 return (Opc == ISD::AND && (Val == 0 || Val == 0xffffffff)) ||
8143 (Opc == ISD::OR && (Val == 0xffffffff || Val == 0)) ||
8144 (Opc == ISD::XOR && Val == 0);
8147 // Break up 64-bit bit operation of a constant into two 32-bit and/or/xor. This
8148 // will typically happen anyway for a VALU 64-bit and. This exposes other 32-bit
8149 // integer combine opportunities since most 64-bit operations are decomposed
8150 // this way. TODO: We won't want this for SALU especially if it is an inline
8152 SDValue SITargetLowering::splitBinaryBitConstantOp(
8153 DAGCombinerInfo &DCI,
8155 unsigned Opc, SDValue LHS,
8156 const ConstantSDNode *CRHS) const {
8157 uint64_t Val = CRHS->getZExtValue();
8158 uint32_t ValLo = Lo_32(Val);
8159 uint32_t ValHi = Hi_32(Val);
8160 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
8162 if ((bitOpWithConstantIsReducible(Opc, ValLo) ||
8163 bitOpWithConstantIsReducible(Opc, ValHi)) ||
8164 (CRHS->hasOneUse() && !TII->isInlineConstant(CRHS->getAPIntValue()))) {
8165 // If we need to materialize a 64-bit immediate, it will be split up later
8166 // anyway. Avoid creating the harder to understand 64-bit immediate
8168 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi);
8174 // Returns true if argument is a boolean value which is not serialized into
8175 // memory or argument and does not require v_cmdmask_b32 to be deserialized.
8176 static bool isBoolSGPR(SDValue V) {
8177 if (V.getValueType() != MVT::i1)
8179 switch (V.getOpcode()) {
8185 case AMDGPUISD::FP_CLASS:
8191 // If a constant has all zeroes or all ones within each byte return it.
8192 // Otherwise return 0.
8193 static uint32_t getConstantPermuteMask(uint32_t C) {
8194 // 0xff for any zero byte in the mask
8195 uint32_t ZeroByteMask = 0;
8196 if (!(C & 0x000000ff)) ZeroByteMask |= 0x000000ff;
8197 if (!(C & 0x0000ff00)) ZeroByteMask |= 0x0000ff00;
8198 if (!(C & 0x00ff0000)) ZeroByteMask |= 0x00ff0000;
8199 if (!(C & 0xff000000)) ZeroByteMask |= 0xff000000;
8200 uint32_t NonZeroByteMask = ~ZeroByteMask; // 0xff for any non-zero byte
8201 if ((NonZeroByteMask & C) != NonZeroByteMask)
8202 return 0; // Partial bytes selected.
8206 // Check if a node selects whole bytes from its operand 0 starting at a byte
8207 // boundary while masking the rest. Returns select mask as in the v_perm_b32
8208 // or -1 if not succeeded.
8209 // Note byte select encoding:
8210 // value 0-3 selects corresponding source byte;
8211 // value 0xc selects zero;
8212 // value 0xff selects 0xff.
8213 static uint32_t getPermuteMask(SelectionDAG &DAG, SDValue V) {
8214 assert(V.getValueSizeInBits() == 32);
8216 if (V.getNumOperands() != 2)
8219 ConstantSDNode *N1 = dyn_cast<ConstantSDNode>(V.getOperand(1));
8223 uint32_t C = N1->getZExtValue();
8225 switch (V.getOpcode()) {
8229 if (uint32_t ConstMask = getConstantPermuteMask(C)) {
8230 return (0x03020100 & ConstMask) | (0x0c0c0c0c & ~ConstMask);
8235 if (uint32_t ConstMask = getConstantPermuteMask(C)) {
8236 return (0x03020100 & ~ConstMask) | ConstMask;
8244 return uint32_t((0x030201000c0c0c0cull << C) >> 32);
8250 return uint32_t(0x0c0c0c0c03020100ull >> C);
8256 SDValue SITargetLowering::performAndCombine(SDNode *N,
8257 DAGCombinerInfo &DCI) const {
8258 if (DCI.isBeforeLegalize())
8261 SelectionDAG &DAG = DCI.DAG;
8262 EVT VT = N->getValueType(0);
8263 SDValue LHS = N->getOperand(0);
8264 SDValue RHS = N->getOperand(1);
8267 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
8268 if (VT == MVT::i64 && CRHS) {
8270 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
8274 if (CRHS && VT == MVT::i32) {
8275 // and (srl x, c), mask => shl (bfe x, nb + c, mask >> nb), nb
8276 // nb = number of trailing zeroes in mask
8277 // It can be optimized out using SDWA for GFX8+ in the SDWA peephole pass,
8278 // given that we are selecting 8 or 16 bit fields starting at byte boundary.
8279 uint64_t Mask = CRHS->getZExtValue();
8280 unsigned Bits = countPopulation(Mask);
8281 if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &&
8282 (Bits == 8 || Bits == 16) && isShiftedMask_64(Mask) && !(Mask & 1)) {
8283 if (auto *CShift = dyn_cast<ConstantSDNode>(LHS->getOperand(1))) {
8284 unsigned Shift = CShift->getZExtValue();
8285 unsigned NB = CRHS->getAPIntValue().countTrailingZeros();
8286 unsigned Offset = NB + Shift;
8287 if ((Offset & (Bits - 1)) == 0) { // Starts at a byte or word boundary.
8289 SDValue BFE = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
8291 DAG.getConstant(Offset, SL, MVT::i32),
8292 DAG.getConstant(Bits, SL, MVT::i32));
8293 EVT NarrowVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
8294 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE,
8295 DAG.getValueType(NarrowVT));
8296 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(LHS), VT, Ext,
8297 DAG.getConstant(NB, SDLoc(CRHS), MVT::i32));
8303 // and (perm x, y, c1), c2 -> perm x, y, permute_mask(c1, c2)
8304 if (LHS.hasOneUse() && LHS.getOpcode() == AMDGPUISD::PERM &&
8305 isa<ConstantSDNode>(LHS.getOperand(2))) {
8306 uint32_t Sel = getConstantPermuteMask(Mask);
8310 // Select 0xc for all zero bytes
8311 Sel = (LHS.getConstantOperandVal(2) & Sel) | (~Sel & 0x0c0c0c0c);
8313 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, LHS.getOperand(0),
8314 LHS.getOperand(1), DAG.getConstant(Sel, DL, MVT::i32));
8318 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
8319 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
8320 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
8321 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
8322 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
8324 SDValue X = LHS.getOperand(0);
8325 SDValue Y = RHS.getOperand(0);
8326 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
8329 if (LCC == ISD::SETO) {
8330 if (X != LHS.getOperand(1))
8333 if (RCC == ISD::SETUNE) {
8334 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
8335 if (!C1 || !C1->isInfinity() || C1->isNegative())
8338 const uint32_t Mask = SIInstrFlags::N_NORMAL |
8339 SIInstrFlags::N_SUBNORMAL |
8340 SIInstrFlags::N_ZERO |
8341 SIInstrFlags::P_ZERO |
8342 SIInstrFlags::P_SUBNORMAL |
8343 SIInstrFlags::P_NORMAL;
8345 static_assert(((~(SIInstrFlags::S_NAN |
8346 SIInstrFlags::Q_NAN |
8347 SIInstrFlags::N_INFINITY |
8348 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
8352 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
8353 X, DAG.getConstant(Mask, DL, MVT::i32));
8358 if (RHS.getOpcode() == ISD::SETCC && LHS.getOpcode() == AMDGPUISD::FP_CLASS)
8359 std::swap(LHS, RHS);
8361 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == AMDGPUISD::FP_CLASS &&
8363 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
8364 // and (fcmp seto), (fp_class x, mask) -> fp_class x, mask & ~(p_nan | n_nan)
8365 // and (fcmp setuo), (fp_class x, mask) -> fp_class x, mask & (p_nan | n_nan)
8366 const ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
8367 if ((LCC == ISD::SETO || LCC == ISD::SETUO) && Mask &&
8368 (RHS.getOperand(0) == LHS.getOperand(0) &&
8369 LHS.getOperand(0) == LHS.getOperand(1))) {
8370 const unsigned OrdMask = SIInstrFlags::S_NAN | SIInstrFlags::Q_NAN;
8371 unsigned NewMask = LCC == ISD::SETO ?
8372 Mask->getZExtValue() & ~OrdMask :
8373 Mask->getZExtValue() & OrdMask;
8376 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, RHS.getOperand(0),
8377 DAG.getConstant(NewMask, DL, MVT::i32));
8381 if (VT == MVT::i32 &&
8382 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
8383 // and x, (sext cc from i1) => select cc, x, 0
8384 if (RHS.getOpcode() != ISD::SIGN_EXTEND)
8385 std::swap(LHS, RHS);
8386 if (isBoolSGPR(RHS.getOperand(0)))
8387 return DAG.getSelect(SDLoc(N), MVT::i32, RHS.getOperand(0),
8388 LHS, DAG.getConstant(0, SDLoc(N), MVT::i32));
8391 // and (op x, c1), (op y, c2) -> perm x, y, permute_mask(c1, c2)
8392 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
8393 if (VT == MVT::i32 && LHS.hasOneUse() && RHS.hasOneUse() &&
8394 N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32) != -1) {
8395 uint32_t LHSMask = getPermuteMask(DAG, LHS);
8396 uint32_t RHSMask = getPermuteMask(DAG, RHS);
8397 if (LHSMask != ~0u && RHSMask != ~0u) {
8398 // Canonicalize the expression in an attempt to have fewer unique masks
8399 // and therefore fewer registers used to hold the masks.
8400 if (LHSMask > RHSMask) {
8401 std::swap(LHSMask, RHSMask);
8402 std::swap(LHS, RHS);
8405 // Select 0xc for each lane used from source operand. Zero has 0xc mask
8406 // set, 0xff have 0xff in the mask, actual lanes are in the 0-3 range.
8407 uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
8408 uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
8410 // Check of we need to combine values from two sources within a byte.
8411 if (!(LHSUsedLanes & RHSUsedLanes) &&
8412 // If we select high and lower word keep it for SDWA.
8413 // TODO: teach SDWA to work with v_perm_b32 and remove the check.
8414 !(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
8415 // Each byte in each mask is either selector mask 0-3, or has higher
8416 // bits set in either of masks, which can be 0xff for 0xff or 0x0c for
8417 // zero. If 0x0c is in either mask it shall always be 0x0c. Otherwise
8418 // mask which is not 0xff wins. By anding both masks we have a correct
8419 // result except that 0x0c shall be corrected to give 0x0c only.
8420 uint32_t Mask = LHSMask & RHSMask;
8421 for (unsigned I = 0; I < 32; I += 8) {
8422 uint32_t ByteSel = 0xff << I;
8423 if ((LHSMask & ByteSel) == 0x0c || (RHSMask & ByteSel) == 0x0c)
8424 Mask &= (0x0c << I) & 0xffffffff;
8427 // Add 4 to each active LHS lane. It will not affect any existing 0xff
8429 uint32_t Sel = Mask | (LHSUsedLanes & 0x04040404);
8432 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
8433 LHS.getOperand(0), RHS.getOperand(0),
8434 DAG.getConstant(Sel, DL, MVT::i32));
8442 SDValue SITargetLowering::performOrCombine(SDNode *N,
8443 DAGCombinerInfo &DCI) const {
8444 SelectionDAG &DAG = DCI.DAG;
8445 SDValue LHS = N->getOperand(0);
8446 SDValue RHS = N->getOperand(1);
8448 EVT VT = N->getValueType(0);
8449 if (VT == MVT::i1) {
8450 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
8451 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
8452 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
8453 SDValue Src = LHS.getOperand(0);
8454 if (Src != RHS.getOperand(0))
8457 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
8458 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
8462 // Only 10 bits are used.
8463 static const uint32_t MaxMask = 0x3ff;
8465 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
8467 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
8468 Src, DAG.getConstant(NewMask, DL, MVT::i32));
8474 // or (perm x, y, c1), c2 -> perm x, y, permute_mask(c1, c2)
8475 if (isa<ConstantSDNode>(RHS) && LHS.hasOneUse() &&
8476 LHS.getOpcode() == AMDGPUISD::PERM &&
8477 isa<ConstantSDNode>(LHS.getOperand(2))) {
8478 uint32_t Sel = getConstantPermuteMask(N->getConstantOperandVal(1));
8482 Sel |= LHS.getConstantOperandVal(2);
8484 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, LHS.getOperand(0),
8485 LHS.getOperand(1), DAG.getConstant(Sel, DL, MVT::i32));
8488 // or (op x, c1), (op y, c2) -> perm x, y, permute_mask(c1, c2)
8489 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
8490 if (VT == MVT::i32 && LHS.hasOneUse() && RHS.hasOneUse() &&
8491 N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32) != -1) {
8492 uint32_t LHSMask = getPermuteMask(DAG, LHS);
8493 uint32_t RHSMask = getPermuteMask(DAG, RHS);
8494 if (LHSMask != ~0u && RHSMask != ~0u) {
8495 // Canonicalize the expression in an attempt to have fewer unique masks
8496 // and therefore fewer registers used to hold the masks.
8497 if (LHSMask > RHSMask) {
8498 std::swap(LHSMask, RHSMask);
8499 std::swap(LHS, RHS);
8502 // Select 0xc for each lane used from source operand. Zero has 0xc mask
8503 // set, 0xff have 0xff in the mask, actual lanes are in the 0-3 range.
8504 uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
8505 uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
8507 // Check of we need to combine values from two sources within a byte.
8508 if (!(LHSUsedLanes & RHSUsedLanes) &&
8509 // If we select high and lower word keep it for SDWA.
8510 // TODO: teach SDWA to work with v_perm_b32 and remove the check.
8511 !(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
8512 // Kill zero bytes selected by other mask. Zero value is 0xc.
8513 LHSMask &= ~RHSUsedLanes;
8514 RHSMask &= ~LHSUsedLanes;
8515 // Add 4 to each active LHS lane
8516 LHSMask |= LHSUsedLanes & 0x04040404;
8518 uint32_t Sel = LHSMask | RHSMask;
8521 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
8522 LHS.getOperand(0), RHS.getOperand(0),
8523 DAG.getConstant(Sel, DL, MVT::i32));
8531 // TODO: This could be a generic combine with a predicate for extracting the
8532 // high half of an integer being free.
8534 // (or i64:x, (zero_extend i32:y)) ->
8535 // i64 (bitcast (v2i32 build_vector (or i32:y, lo_32(x)), hi_32(x)))
8536 if (LHS.getOpcode() == ISD::ZERO_EXTEND &&
8537 RHS.getOpcode() != ISD::ZERO_EXTEND)
8538 std::swap(LHS, RHS);
8540 if (RHS.getOpcode() == ISD::ZERO_EXTEND) {
8541 SDValue ExtSrc = RHS.getOperand(0);
8542 EVT SrcVT = ExtSrc.getValueType();
8543 if (SrcVT == MVT::i32) {
8545 SDValue LowLHS, HiBits;
8546 std::tie(LowLHS, HiBits) = split64BitValue(LHS, DAG);
8547 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc);
8549 DCI.AddToWorklist(LowOr.getNode());
8550 DCI.AddToWorklist(HiBits.getNode());
8552 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
8554 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
8558 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
8561 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, LHS, CRHS))
8568 SDValue SITargetLowering::performXorCombine(SDNode *N,
8569 DAGCombinerInfo &DCI) const {
8570 EVT VT = N->getValueType(0);
8574 SDValue LHS = N->getOperand(0);
8575 SDValue RHS = N->getOperand(1);
8577 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
8580 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
8587 // Instructions that will be lowered with a final instruction that zeros the
8588 // high result bits.
8589 // XXX - probably only need to list legal operations.
8590 static bool fp16SrcZerosHighBits(unsigned Opc) {
8599 case ISD::FCANONICALIZE:
8601 case ISD::UINT_TO_FP:
8602 case ISD::SINT_TO_FP:
8604 // Fabs is lowered to a bit operation, but it's an and which will clear the
8605 // high bits anyway.
8619 case ISD::FNEARBYINT:
8624 case AMDGPUISD::FRACT:
8625 case AMDGPUISD::CLAMP:
8626 case AMDGPUISD::COS_HW:
8627 case AMDGPUISD::SIN_HW:
8628 case AMDGPUISD::FMIN3:
8629 case AMDGPUISD::FMAX3:
8630 case AMDGPUISD::FMED3:
8631 case AMDGPUISD::FMAD_FTZ:
8632 case AMDGPUISD::RCP:
8633 case AMDGPUISD::RSQ:
8634 case AMDGPUISD::RCP_IFLAG:
8635 case AMDGPUISD::LDEXP:
8638 // fcopysign, select and others may be lowered to 32-bit bit operations
8639 // which don't zero the high bits.
8644 SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,
8645 DAGCombinerInfo &DCI) const {
8646 if (!Subtarget->has16BitInsts() ||
8647 DCI.getDAGCombineLevel() < AfterLegalizeDAG)
8650 EVT VT = N->getValueType(0);
8654 SDValue Src = N->getOperand(0);
8655 if (Src.getValueType() != MVT::i16)
8658 // (i32 zext (i16 (bitcast f16:$src))) -> fp16_zext $src
8659 // FIXME: It is not universally true that the high bits are zeroed on gfx9.
8660 if (Src.getOpcode() == ISD::BITCAST) {
8661 SDValue BCSrc = Src.getOperand(0);
8662 if (BCSrc.getValueType() == MVT::f16 &&
8663 fp16SrcZerosHighBits(BCSrc.getOpcode()))
8664 return DCI.DAG.getNode(AMDGPUISD::FP16_ZEXT, SDLoc(N), VT, BCSrc);
8670 SDValue SITargetLowering::performSignExtendInRegCombine(SDNode *N,
8671 DAGCombinerInfo &DCI)
8673 SDValue Src = N->getOperand(0);
8674 auto *VTSign = cast<VTSDNode>(N->getOperand(1));
8676 if (((Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE &&
8677 VTSign->getVT() == MVT::i8) ||
8678 (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_USHORT &&
8679 VTSign->getVT() == MVT::i16)) &&
8681 auto *M = cast<MemSDNode>(Src);
8683 Src.getOperand(0), // Chain
8684 Src.getOperand(1), // rsrc
8685 Src.getOperand(2), // vindex
8686 Src.getOperand(3), // voffset
8687 Src.getOperand(4), // soffset
8688 Src.getOperand(5), // offset
8692 // replace with BUFFER_LOAD_BYTE/SHORT
8693 SDVTList ResList = DCI.DAG.getVTList(MVT::i32,
8694 Src.getOperand(0).getValueType());
8695 unsigned Opc = (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE) ?
8696 AMDGPUISD::BUFFER_LOAD_BYTE : AMDGPUISD::BUFFER_LOAD_SHORT;
8697 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc, SDLoc(N),
8699 Ops, M->getMemoryVT(),
8700 M->getMemOperand());
8701 return DCI.DAG.getMergeValues({BufferLoadSignExt,
8702 BufferLoadSignExt.getValue(1)}, SDLoc(N));
8707 SDValue SITargetLowering::performClassCombine(SDNode *N,
8708 DAGCombinerInfo &DCI) const {
8709 SelectionDAG &DAG = DCI.DAG;
8710 SDValue Mask = N->getOperand(1);
8712 // fp_class x, 0 -> false
8713 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
8714 if (CMask->isNullValue())
8715 return DAG.getConstant(0, SDLoc(N), MVT::i1);
8718 if (N->getOperand(0).isUndef())
8719 return DAG.getUNDEF(MVT::i1);
8724 SDValue SITargetLowering::performRcpCombine(SDNode *N,
8725 DAGCombinerInfo &DCI) const {
8726 EVT VT = N->getValueType(0);
8727 SDValue N0 = N->getOperand(0);
8732 if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
8733 N0.getOpcode() == ISD::SINT_TO_FP)) {
8734 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0,
8738 return AMDGPUTargetLowering::performRcpCombine(N, DCI);
8741 bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
8742 unsigned MaxDepth) const {
8743 unsigned Opcode = Op.getOpcode();
8744 if (Opcode == ISD::FCANONICALIZE)
8747 if (auto *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
8748 auto F = CFP->getValueAPF();
8749 if (F.isNaN() && F.isSignaling())
8751 return !F.isDenormal() || denormalsEnabledForType(DAG, Op.getValueType());
8754 // If source is a result of another standard FP operation it is already in
8760 // These will flush denorms if required.
8772 case ISD::FP_EXTEND:
8773 case AMDGPUISD::FMUL_LEGACY:
8774 case AMDGPUISD::FMAD_FTZ:
8775 case AMDGPUISD::RCP:
8776 case AMDGPUISD::RSQ:
8777 case AMDGPUISD::RSQ_CLAMP:
8778 case AMDGPUISD::RCP_LEGACY:
8779 case AMDGPUISD::RSQ_LEGACY:
8780 case AMDGPUISD::RCP_IFLAG:
8781 case AMDGPUISD::TRIG_PREOP:
8782 case AMDGPUISD::DIV_SCALE:
8783 case AMDGPUISD::DIV_FMAS:
8784 case AMDGPUISD::DIV_FIXUP:
8785 case AMDGPUISD::FRACT:
8786 case AMDGPUISD::LDEXP:
8787 case AMDGPUISD::CVT_PKRTZ_F16_F32:
8788 case AMDGPUISD::CVT_F32_UBYTE0:
8789 case AMDGPUISD::CVT_F32_UBYTE1:
8790 case AMDGPUISD::CVT_F32_UBYTE2:
8791 case AMDGPUISD::CVT_F32_UBYTE3:
8794 // It can/will be lowered or combined as a bit operation.
8795 // Need to check their input recursively to handle.
8798 case ISD::FCOPYSIGN:
8799 return isCanonicalized(DAG, Op.getOperand(0), MaxDepth - 1);
8804 return Op.getValueType().getScalarType() != MVT::f16;
8808 case ISD::FMINNUM_IEEE:
8809 case ISD::FMAXNUM_IEEE:
8810 case AMDGPUISD::CLAMP:
8811 case AMDGPUISD::FMED3:
8812 case AMDGPUISD::FMAX3:
8813 case AMDGPUISD::FMIN3: {
8814 // FIXME: Shouldn't treat the generic operations different based these.
8815 // However, we aren't really required to flush the result from
8818 // snans will be quieted, so we only need to worry about denormals.
8819 if (Subtarget->supportsMinMaxDenormModes() ||
8820 denormalsEnabledForType(DAG, Op.getValueType()))
8823 // Flushing may be required.
8824 // In pre-GFX9 targets V_MIN_F32 and others do not flush denorms. For such
8825 // targets need to check their input recursively.
8827 // FIXME: Does this apply with clamp? It's implemented with max.
8828 for (unsigned I = 0, E = Op.getNumOperands(); I != E; ++I) {
8829 if (!isCanonicalized(DAG, Op.getOperand(I), MaxDepth - 1))
8836 return isCanonicalized(DAG, Op.getOperand(1), MaxDepth - 1) &&
8837 isCanonicalized(DAG, Op.getOperand(2), MaxDepth - 1);
8839 case ISD::BUILD_VECTOR: {
8840 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
8841 SDValue SrcOp = Op.getOperand(i);
8842 if (!isCanonicalized(DAG, SrcOp, MaxDepth - 1))
8848 case ISD::EXTRACT_VECTOR_ELT:
8849 case ISD::EXTRACT_SUBVECTOR: {
8850 return isCanonicalized(DAG, Op.getOperand(0), MaxDepth - 1);
8852 case ISD::INSERT_VECTOR_ELT: {
8853 return isCanonicalized(DAG, Op.getOperand(0), MaxDepth - 1) &&
8854 isCanonicalized(DAG, Op.getOperand(1), MaxDepth - 1);
8857 // Could be anything.
8860 case ISD::BITCAST: {
8861 // Hack round the mess we make when legalizing extract_vector_elt
8862 SDValue Src = Op.getOperand(0);
8863 if (Src.getValueType() == MVT::i16 &&
8864 Src.getOpcode() == ISD::TRUNCATE) {
8865 SDValue TruncSrc = Src.getOperand(0);
8866 if (TruncSrc.getValueType() == MVT::i32 &&
8867 TruncSrc.getOpcode() == ISD::BITCAST &&
8868 TruncSrc.getOperand(0).getValueType() == MVT::v2f16) {
8869 return isCanonicalized(DAG, TruncSrc.getOperand(0), MaxDepth - 1);
8875 case ISD::INTRINSIC_WO_CHAIN: {
8876 unsigned IntrinsicID
8877 = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8878 // TODO: Handle more intrinsics
8879 switch (IntrinsicID) {
8880 case Intrinsic::amdgcn_cvt_pkrtz:
8881 case Intrinsic::amdgcn_cubeid:
8882 case Intrinsic::amdgcn_frexp_mant:
8883 case Intrinsic::amdgcn_fdot2:
8892 return denormalsEnabledForType(DAG, Op.getValueType()) &&
8893 DAG.isKnownNeverSNaN(Op);
8896 llvm_unreachable("invalid operation");
8899 // Constant fold canonicalize.
8900 SDValue SITargetLowering::getCanonicalConstantFP(
8901 SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const {
8902 // Flush denormals to 0 if not enabled.
8903 if (C.isDenormal() && !denormalsEnabledForType(DAG, VT))
8904 return DAG.getConstantFP(0.0, SL, VT);
8907 APFloat CanonicalQNaN = APFloat::getQNaN(C.getSemantics());
8908 if (C.isSignaling()) {
8909 // Quiet a signaling NaN.
8910 // FIXME: Is this supposed to preserve payload bits?
8911 return DAG.getConstantFP(CanonicalQNaN, SL, VT);
8914 // Make sure it is the canonical NaN bitpattern.
8916 // TODO: Can we use -1 as the canonical NaN value since it's an inline
8918 if (C.bitcastToAPInt() != CanonicalQNaN.bitcastToAPInt())
8919 return DAG.getConstantFP(CanonicalQNaN, SL, VT);
8922 // Already canonical.
8923 return DAG.getConstantFP(C, SL, VT);
8926 static bool vectorEltWillFoldAway(SDValue Op) {
8927 return Op.isUndef() || isa<ConstantFPSDNode>(Op);
8930 SDValue SITargetLowering::performFCanonicalizeCombine(
8932 DAGCombinerInfo &DCI) const {
8933 SelectionDAG &DAG = DCI.DAG;
8934 SDValue N0 = N->getOperand(0);
8935 EVT VT = N->getValueType(0);
8937 // fcanonicalize undef -> qnan
8939 APFloat QNaN = APFloat::getQNaN(SelectionDAG::EVTToAPFloatSemantics(VT));
8940 return DAG.getConstantFP(QNaN, SDLoc(N), VT);
8943 if (ConstantFPSDNode *CFP = isConstOrConstSplatFP(N0)) {
8944 EVT VT = N->getValueType(0);
8945 return getCanonicalConstantFP(DAG, SDLoc(N), VT, CFP->getValueAPF());
8948 // fcanonicalize (build_vector x, k) -> build_vector (fcanonicalize x),
8949 // (fcanonicalize k)
8951 // fcanonicalize (build_vector x, undef) -> build_vector (fcanonicalize x), 0
8953 // TODO: This could be better with wider vectors that will be split to v2f16,
8954 // and to consider uses since there aren't that many packed operations.
8955 if (N0.getOpcode() == ISD::BUILD_VECTOR && VT == MVT::v2f16 &&
8956 isTypeLegal(MVT::v2f16)) {
8959 SDValue Lo = N0.getOperand(0);
8960 SDValue Hi = N0.getOperand(1);
8961 EVT EltVT = Lo.getValueType();
8963 if (vectorEltWillFoldAway(Lo) || vectorEltWillFoldAway(Hi)) {
8964 for (unsigned I = 0; I != 2; ++I) {
8965 SDValue Op = N0.getOperand(I);
8966 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
8967 NewElts[I] = getCanonicalConstantFP(DAG, SL, EltVT,
8968 CFP->getValueAPF());
8969 } else if (Op.isUndef()) {
8970 // Handled below based on what the other operand is.
8973 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op);
8977 // If one half is undef, and one is constant, perfer a splat vector rather
8978 // than the normal qNaN. If it's a register, prefer 0.0 since that's
8979 // cheaper to use and may be free with a packed operation.
8980 if (NewElts[0].isUndef()) {
8981 if (isa<ConstantFPSDNode>(NewElts[1]))
8982 NewElts[0] = isa<ConstantFPSDNode>(NewElts[1]) ?
8983 NewElts[1]: DAG.getConstantFP(0.0f, SL, EltVT);
8986 if (NewElts[1].isUndef()) {
8987 NewElts[1] = isa<ConstantFPSDNode>(NewElts[0]) ?
8988 NewElts[0] : DAG.getConstantFP(0.0f, SL, EltVT);
8991 return DAG.getBuildVector(VT, SL, NewElts);
8995 unsigned SrcOpc = N0.getOpcode();
8997 // If it's free to do so, push canonicalizes further up the source, which may
8998 // find a canonical source.
9000 // TODO: More opcodes. Note this is unsafe for the the _ieee minnum/maxnum for
9002 if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) {
9003 auto *CRHS = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
9004 if (CRHS && N0.hasOneUse()) {
9006 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT,
9008 SDValue Canon1 = getCanonicalConstantFP(DAG, SL, VT, CRHS->getValueAPF());
9009 DCI.AddToWorklist(Canon0.getNode());
9011 return DAG.getNode(N0.getOpcode(), SL, VT, Canon0, Canon1);
9015 return isCanonicalized(DAG, N0) ? N0 : SDValue();
9018 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
9021 case ISD::FMAXNUM_IEEE:
9022 return AMDGPUISD::FMAX3;
9024 return AMDGPUISD::SMAX3;
9026 return AMDGPUISD::UMAX3;
9028 case ISD::FMINNUM_IEEE:
9029 return AMDGPUISD::FMIN3;
9031 return AMDGPUISD::SMIN3;
9033 return AMDGPUISD::UMIN3;
9035 llvm_unreachable("Not a min/max opcode");
9039 SDValue SITargetLowering::performIntMed3ImmCombine(
9040 SelectionDAG &DAG, const SDLoc &SL,
9041 SDValue Op0, SDValue Op1, bool Signed) const {
9042 ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
9046 ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
9051 if (K0->getAPIntValue().sge(K1->getAPIntValue()))
9054 if (K0->getAPIntValue().uge(K1->getAPIntValue()))
9058 EVT VT = K0->getValueType(0);
9059 unsigned Med3Opc = Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3;
9060 if (VT == MVT::i32 || (VT == MVT::i16 && Subtarget->hasMed3_16())) {
9061 return DAG.getNode(Med3Opc, SL, VT,
9062 Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
9065 // If there isn't a 16-bit med3 operation, convert to 32-bit.
9067 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
9069 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
9070 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
9071 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
9073 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
9074 return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3);
9077 static ConstantFPSDNode *getSplatConstantFP(SDValue Op) {
9078 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
9081 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op)) {
9082 if (ConstantFPSDNode *C = BV->getConstantFPSplatNode())
9089 SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG,
9092 SDValue Op1) const {
9093 ConstantFPSDNode *K1 = getSplatConstantFP(Op1);
9097 ConstantFPSDNode *K0 = getSplatConstantFP(Op0.getOperand(1));
9101 // Ordered >= (although NaN inputs should have folded away by now).
9102 APFloat::cmpResult Cmp = K0->getValueAPF().compare(K1->getValueAPF());
9103 if (Cmp == APFloat::cmpGreaterThan)
9106 const MachineFunction &MF = DAG.getMachineFunction();
9107 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
9109 // TODO: Check IEEE bit enabled?
9110 EVT VT = Op0.getValueType();
9111 if (Info->getMode().DX10Clamp) {
9112 // If dx10_clamp is enabled, NaNs clamp to 0.0. This is the same as the
9113 // hardware fmed3 behavior converting to a min.
9114 // FIXME: Should this be allowing -0.0?
9115 if (K1->isExactlyValue(1.0) && K0->isExactlyValue(0.0))
9116 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Op0.getOperand(0));
9119 // med3 for f16 is only available on gfx9+, and not available for v2f16.
9120 if (VT == MVT::f32 || (VT == MVT::f16 && Subtarget->hasMed3_16())) {
9121 // This isn't safe with signaling NaNs because in IEEE mode, min/max on a
9122 // signaling NaN gives a quiet NaN. The quiet NaN input to the min would
9123 // then give the other result, which is different from med3 with a NaN
9125 SDValue Var = Op0.getOperand(0);
9126 if (!DAG.isKnownNeverSNaN(Var))
9129 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
9131 if ((!K0->hasOneUse() ||
9132 TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) &&
9133 (!K1->hasOneUse() ||
9134 TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) {
9135 return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0),
9136 Var, SDValue(K0, 0), SDValue(K1, 0));
9143 SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
9144 DAGCombinerInfo &DCI) const {
9145 SelectionDAG &DAG = DCI.DAG;
9147 EVT VT = N->getValueType(0);
9148 unsigned Opc = N->getOpcode();
9149 SDValue Op0 = N->getOperand(0);
9150 SDValue Op1 = N->getOperand(1);
9152 // Only do this if the inner op has one use since this will just increases
9153 // register pressure for no benefit.
9155 if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
9157 (VT == MVT::i32 || VT == MVT::f32 ||
9158 ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->hasMin3Max3_16()))) {
9159 // max(max(a, b), c) -> max3(a, b, c)
9160 // min(min(a, b), c) -> min3(a, b, c)
9161 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
9163 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
9172 // max(a, max(b, c)) -> max3(a, b, c)
9173 // min(a, min(b, c)) -> min3(a, b, c)
9174 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
9176 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
9185 // min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
9186 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
9187 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, true))
9191 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
9192 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, false))
9196 // fminnum(fmaxnum(x, K0), K1), K0 < K1 && !is_snan(x) -> fmed3(x, K0, K1)
9197 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) ||
9198 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) ||
9199 (Opc == AMDGPUISD::FMIN_LEGACY &&
9200 Op0.getOpcode() == AMDGPUISD::FMAX_LEGACY)) &&
9201 (VT == MVT::f32 || VT == MVT::f64 ||
9202 (VT == MVT::f16 && Subtarget->has16BitInsts()) ||
9203 (VT == MVT::v2f16 && Subtarget->hasVOP3PInsts())) &&
9205 if (SDValue Res = performFPMed3ImmCombine(DAG, SDLoc(N), Op0, Op1))
9212 static bool isClampZeroToOne(SDValue A, SDValue B) {
9213 if (ConstantFPSDNode *CA = dyn_cast<ConstantFPSDNode>(A)) {
9214 if (ConstantFPSDNode *CB = dyn_cast<ConstantFPSDNode>(B)) {
9215 // FIXME: Should this be allowing -0.0?
9216 return (CA->isExactlyValue(0.0) && CB->isExactlyValue(1.0)) ||
9217 (CA->isExactlyValue(1.0) && CB->isExactlyValue(0.0));
9224 // FIXME: Should only worry about snans for version with chain.
9225 SDValue SITargetLowering::performFMed3Combine(SDNode *N,
9226 DAGCombinerInfo &DCI) const {
9227 EVT VT = N->getValueType(0);
9228 // v_med3_f32 and v_max_f32 behave identically wrt denorms, exceptions and
9229 // NaNs. With a NaN input, the order of the operands may change the result.
9231 SelectionDAG &DAG = DCI.DAG;
9234 SDValue Src0 = N->getOperand(0);
9235 SDValue Src1 = N->getOperand(1);
9236 SDValue Src2 = N->getOperand(2);
9238 if (isClampZeroToOne(Src0, Src1)) {
9239 // const_a, const_b, x -> clamp is safe in all cases including signaling
9241 // FIXME: Should this be allowing -0.0?
9242 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src2);
9245 const MachineFunction &MF = DAG.getMachineFunction();
9246 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
9248 // FIXME: dx10_clamp behavior assumed in instcombine. Should we really bother
9249 // handling no dx10-clamp?
9250 if (Info->getMode().DX10Clamp) {
9251 // If NaNs is clamped to 0, we are free to reorder the inputs.
9253 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
9254 std::swap(Src0, Src1);
9256 if (isa<ConstantFPSDNode>(Src1) && !isa<ConstantFPSDNode>(Src2))
9257 std::swap(Src1, Src2);
9259 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
9260 std::swap(Src0, Src1);
9262 if (isClampZeroToOne(Src1, Src2))
9263 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0);
9269 SDValue SITargetLowering::performCvtPkRTZCombine(SDNode *N,
9270 DAGCombinerInfo &DCI) const {
9271 SDValue Src0 = N->getOperand(0);
9272 SDValue Src1 = N->getOperand(1);
9273 if (Src0.isUndef() && Src1.isUndef())
9274 return DCI.DAG.getUNDEF(N->getValueType(0));
9278 SDValue SITargetLowering::performExtractVectorEltCombine(
9279 SDNode *N, DAGCombinerInfo &DCI) const {
9280 SDValue Vec = N->getOperand(0);
9281 SelectionDAG &DAG = DCI.DAG;
9283 EVT VecVT = Vec.getValueType();
9284 EVT EltVT = VecVT.getVectorElementType();
9286 if ((Vec.getOpcode() == ISD::FNEG ||
9287 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) {
9289 EVT EltVT = N->getValueType(0);
9290 SDValue Idx = N->getOperand(1);
9291 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
9292 Vec.getOperand(0), Idx);
9293 return DAG.getNode(Vec.getOpcode(), SL, EltVT, Elt);
9296 // ScalarRes = EXTRACT_VECTOR_ELT ((vector-BINOP Vec1, Vec2), Idx)
9298 // Vec1Elt = EXTRACT_VECTOR_ELT(Vec1, Idx)
9299 // Vec2Elt = EXTRACT_VECTOR_ELT(Vec2, Idx)
9300 // ScalarRes = scalar-BINOP Vec1Elt, Vec2Elt
9301 if (Vec.hasOneUse() && DCI.isBeforeLegalize()) {
9303 EVT EltVT = N->getValueType(0);
9304 SDValue Idx = N->getOperand(1);
9305 unsigned Opc = Vec.getOpcode();
9310 // TODO: Support other binary operations.
9321 case ISD::FMAXNUM_IEEE:
9322 case ISD::FMINNUM_IEEE: {
9323 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
9324 Vec.getOperand(0), Idx);
9325 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
9326 Vec.getOperand(1), Idx);
9328 DCI.AddToWorklist(Elt0.getNode());
9329 DCI.AddToWorklist(Elt1.getNode());
9330 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags());
9335 unsigned VecSize = VecVT.getSizeInBits();
9336 unsigned EltSize = EltVT.getSizeInBits();
9338 // EXTRACT_VECTOR_ELT (<n x e>, var-idx) => n x select (e, const-idx)
9339 // This elminates non-constant index and subsequent movrel or scratch access.
9340 // Sub-dword vectors of size 2 dword or less have better implementation.
9341 // Vectors of size bigger than 8 dwords would yield too many v_cndmask_b32
9343 if (VecSize <= 256 && (VecSize > 64 || EltSize >= 32) &&
9344 !isa<ConstantSDNode>(N->getOperand(1))) {
9346 SDValue Idx = N->getOperand(1);
9347 EVT IdxVT = Idx.getValueType();
9349 for (unsigned I = 0, E = VecVT.getVectorNumElements(); I < E; ++I) {
9350 SDValue IC = DAG.getConstant(I, SL, IdxVT);
9351 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);
9355 V = DAG.getSelectCC(SL, Idx, IC, Elt, V, ISD::SETEQ);
9360 if (!DCI.isBeforeLegalize())
9363 // Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
9364 // elements. This exposes more load reduction opportunities by replacing
9365 // multiple small extract_vector_elements with a single 32-bit extract.
9366 auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
9367 if (isa<MemSDNode>(Vec) &&
9369 EltVT.isByteSized() &&
9371 VecSize % 32 == 0 &&
9373 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT);
9375 unsigned BitIndex = Idx->getZExtValue() * EltSize;
9376 unsigned EltIdx = BitIndex / 32;
9377 unsigned LeftoverBitIdx = BitIndex % 32;
9380 SDValue Cast = DAG.getNode(ISD::BITCAST, SL, NewVT, Vec);
9381 DCI.AddToWorklist(Cast.getNode());
9383 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Cast,
9384 DAG.getConstant(EltIdx, SL, MVT::i32));
9385 DCI.AddToWorklist(Elt.getNode());
9386 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt,
9387 DAG.getConstant(LeftoverBitIdx, SL, MVT::i32));
9388 DCI.AddToWorklist(Srl.getNode());
9390 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl);
9391 DCI.AddToWorklist(Trunc.getNode());
9392 return DAG.getNode(ISD::BITCAST, SL, EltVT, Trunc);
9399 SITargetLowering::performInsertVectorEltCombine(SDNode *N,
9400 DAGCombinerInfo &DCI) const {
9401 SDValue Vec = N->getOperand(0);
9402 SDValue Idx = N->getOperand(2);
9403 EVT VecVT = Vec.getValueType();
9404 EVT EltVT = VecVT.getVectorElementType();
9405 unsigned VecSize = VecVT.getSizeInBits();
9406 unsigned EltSize = EltVT.getSizeInBits();
9408 // INSERT_VECTOR_ELT (<n x e>, var-idx)
9409 // => BUILD_VECTOR n x select (e, const-idx)
9410 // This elminates non-constant index and subsequent movrel or scratch access.
9411 // Sub-dword vectors of size 2 dword or less have better implementation.
9412 // Vectors of size bigger than 8 dwords would yield too many v_cndmask_b32
9414 if (isa<ConstantSDNode>(Idx) ||
9415 VecSize > 256 || (VecSize <= 64 && EltSize < 32))
9418 SelectionDAG &DAG = DCI.DAG;
9420 SDValue Ins = N->getOperand(1);
9421 EVT IdxVT = Idx.getValueType();
9423 SmallVector<SDValue, 16> Ops;
9424 for (unsigned I = 0, E = VecVT.getVectorNumElements(); I < E; ++I) {
9425 SDValue IC = DAG.getConstant(I, SL, IdxVT);
9426 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);
9427 SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ);
9431 return DAG.getBuildVector(VecVT, SL, Ops);
9434 unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
9436 const SDNode *N1) const {
9437 EVT VT = N0->getValueType(0);
9439 // Only do this if we are not trying to support denormals. v_mad_f32 does not
9440 // support denormals ever.
9441 if (((VT == MVT::f32 && !hasFP32Denormals(DAG.getMachineFunction())) ||
9442 (VT == MVT::f16 && !hasFP64FP16Denormals(DAG.getMachineFunction()) &&
9443 getSubtarget()->hasMadF16())) &&
9444 isOperationLegal(ISD::FMAD, VT))
9447 const TargetOptions &Options = DAG.getTarget().Options;
9448 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath ||
9449 (N0->getFlags().hasAllowContract() &&
9450 N1->getFlags().hasAllowContract())) &&
9451 isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) {
9458 // For a reassociatable opcode perform:
9459 // op x, (op y, z) -> op (op x, z), y, if x and z are uniform
9460 SDValue SITargetLowering::reassociateScalarOps(SDNode *N,
9461 SelectionDAG &DAG) const {
9462 EVT VT = N->getValueType(0);
9463 if (VT != MVT::i32 && VT != MVT::i64)
9466 unsigned Opc = N->getOpcode();
9467 SDValue Op0 = N->getOperand(0);
9468 SDValue Op1 = N->getOperand(1);
9470 if (!(Op0->isDivergent() ^ Op1->isDivergent()))
9473 if (Op0->isDivergent())
9474 std::swap(Op0, Op1);
9476 if (Op1.getOpcode() != Opc || !Op1.hasOneUse())
9479 SDValue Op2 = Op1.getOperand(1);
9480 Op1 = Op1.getOperand(0);
9481 if (!(Op1->isDivergent() ^ Op2->isDivergent()))
9484 if (Op1->isDivergent())
9485 std::swap(Op1, Op2);
9487 // If either operand is constant this will conflict with
9488 // DAGCombiner::ReassociateOps().
9489 if (DAG.isConstantIntBuildVectorOrConstantInt(Op0) ||
9490 DAG.isConstantIntBuildVectorOrConstantInt(Op1))
9494 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1);
9495 return DAG.getNode(Opc, SL, VT, Add1, Op2);
9498 static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL,
9500 SDValue N0, SDValue N1, SDValue N2,
9502 unsigned MadOpc = Signed ? AMDGPUISD::MAD_I64_I32 : AMDGPUISD::MAD_U64_U32;
9503 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i1);
9504 SDValue Mad = DAG.getNode(MadOpc, SL, VTs, N0, N1, N2);
9505 return DAG.getNode(ISD::TRUNCATE, SL, VT, Mad);
9508 SDValue SITargetLowering::performAddCombine(SDNode *N,
9509 DAGCombinerInfo &DCI) const {
9510 SelectionDAG &DAG = DCI.DAG;
9511 EVT VT = N->getValueType(0);
9513 SDValue LHS = N->getOperand(0);
9514 SDValue RHS = N->getOperand(1);
9516 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL)
9517 && Subtarget->hasMad64_32() &&
9518 !VT.isVector() && VT.getScalarSizeInBits() > 32 &&
9519 VT.getScalarSizeInBits() <= 64) {
9520 if (LHS.getOpcode() != ISD::MUL)
9521 std::swap(LHS, RHS);
9523 SDValue MulLHS = LHS.getOperand(0);
9524 SDValue MulRHS = LHS.getOperand(1);
9525 SDValue AddRHS = RHS;
9527 // TODO: Maybe restrict if SGPR inputs.
9528 if (numBitsUnsigned(MulLHS, DAG) <= 32 &&
9529 numBitsUnsigned(MulRHS, DAG) <= 32) {
9530 MulLHS = DAG.getZExtOrTrunc(MulLHS, SL, MVT::i32);
9531 MulRHS = DAG.getZExtOrTrunc(MulRHS, SL, MVT::i32);
9532 AddRHS = DAG.getZExtOrTrunc(AddRHS, SL, MVT::i64);
9533 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, false);
9536 if (numBitsSigned(MulLHS, DAG) < 32 && numBitsSigned(MulRHS, DAG) < 32) {
9537 MulLHS = DAG.getSExtOrTrunc(MulLHS, SL, MVT::i32);
9538 MulRHS = DAG.getSExtOrTrunc(MulRHS, SL, MVT::i32);
9539 AddRHS = DAG.getSExtOrTrunc(AddRHS, SL, MVT::i64);
9540 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, true);
9546 if (SDValue V = reassociateScalarOps(N, DAG)) {
9550 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
9553 // add x, zext (setcc) => addcarry x, 0, setcc
9554 // add x, sext (setcc) => subcarry x, 0, setcc
9555 unsigned Opc = LHS.getOpcode();
9556 if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND ||
9557 Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY)
9558 std::swap(RHS, LHS);
9560 Opc = RHS.getOpcode();
9563 case ISD::ZERO_EXTEND:
9564 case ISD::SIGN_EXTEND:
9565 case ISD::ANY_EXTEND: {
9566 auto Cond = RHS.getOperand(0);
9567 // If this won't be a real VOPC output, we would still need to insert an
9568 // extra instruction anyway.
9569 if (!isBoolSGPR(Cond))
9571 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1);
9572 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond };
9573 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
9574 return DAG.getNode(Opc, SL, VTList, Args);
9576 case ISD::ADDCARRY: {
9577 // add x, (addcarry y, 0, cc) => addcarry x, y, cc
9578 auto C = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
9579 if (!C || C->getZExtValue() != 0) break;
9580 SDValue Args[] = { LHS, RHS.getOperand(0), RHS.getOperand(2) };
9581 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args);
9587 SDValue SITargetLowering::performSubCombine(SDNode *N,
9588 DAGCombinerInfo &DCI) const {
9589 SelectionDAG &DAG = DCI.DAG;
9590 EVT VT = N->getValueType(0);
9596 SDValue LHS = N->getOperand(0);
9597 SDValue RHS = N->getOperand(1);
9599 // sub x, zext (setcc) => subcarry x, 0, setcc
9600 // sub x, sext (setcc) => addcarry x, 0, setcc
9601 unsigned Opc = RHS.getOpcode();
9604 case ISD::ZERO_EXTEND:
9605 case ISD::SIGN_EXTEND:
9606 case ISD::ANY_EXTEND: {
9607 auto Cond = RHS.getOperand(0);
9608 // If this won't be a real VOPC output, we would still need to insert an
9609 // extra instruction anyway.
9610 if (!isBoolSGPR(Cond))
9612 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1);
9613 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond };
9614 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::ADDCARRY : ISD::SUBCARRY;
9615 return DAG.getNode(Opc, SL, VTList, Args);
9619 if (LHS.getOpcode() == ISD::SUBCARRY) {
9620 // sub (subcarry x, 0, cc), y => subcarry x, y, cc
9621 auto C = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
9622 if (!C || !C->isNullValue())
9624 SDValue Args[] = { LHS.getOperand(0), RHS, LHS.getOperand(2) };
9625 return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);
9630 SDValue SITargetLowering::performAddCarrySubCarryCombine(SDNode *N,
9631 DAGCombinerInfo &DCI) const {
9633 if (N->getValueType(0) != MVT::i32)
9636 auto C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9637 if (!C || C->getZExtValue() != 0)
9640 SelectionDAG &DAG = DCI.DAG;
9641 SDValue LHS = N->getOperand(0);
9643 // addcarry (add x, y), 0, cc => addcarry x, y, cc
9644 // subcarry (sub x, y), 0, cc => subcarry x, y, cc
9645 unsigned LHSOpc = LHS.getOpcode();
9646 unsigned Opc = N->getOpcode();
9647 if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) ||
9648 (LHSOpc == ISD::SUB && Opc == ISD::SUBCARRY)) {
9649 SDValue Args[] = { LHS.getOperand(0), LHS.getOperand(1), N->getOperand(2) };
9650 return DAG.getNode(Opc, SDLoc(N), N->getVTList(), Args);
9655 SDValue SITargetLowering::performFAddCombine(SDNode *N,
9656 DAGCombinerInfo &DCI) const {
9657 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
9660 SelectionDAG &DAG = DCI.DAG;
9661 EVT VT = N->getValueType(0);
9664 SDValue LHS = N->getOperand(0);
9665 SDValue RHS = N->getOperand(1);
9667 // These should really be instruction patterns, but writing patterns with
9668 // source modiifiers is a pain.
9670 // fadd (fadd (a, a), b) -> mad 2.0, a, b
9671 if (LHS.getOpcode() == ISD::FADD) {
9672 SDValue A = LHS.getOperand(0);
9673 if (A == LHS.getOperand(1)) {
9674 unsigned FusedOp = getFusedOpcode(DAG, N, LHS.getNode());
9676 const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
9677 return DAG.getNode(FusedOp, SL, VT, A, Two, RHS);
9682 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
9683 if (RHS.getOpcode() == ISD::FADD) {
9684 SDValue A = RHS.getOperand(0);
9685 if (A == RHS.getOperand(1)) {
9686 unsigned FusedOp = getFusedOpcode(DAG, N, RHS.getNode());
9688 const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
9689 return DAG.getNode(FusedOp, SL, VT, A, Two, LHS);
9697 SDValue SITargetLowering::performFSubCombine(SDNode *N,
9698 DAGCombinerInfo &DCI) const {
9699 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
9702 SelectionDAG &DAG = DCI.DAG;
9704 EVT VT = N->getValueType(0);
9705 assert(!VT.isVector());
9707 // Try to get the fneg to fold into the source modifier. This undoes generic
9708 // DAG combines and folds them into the mad.
9710 // Only do this if we are not trying to support denormals. v_mad_f32 does
9711 // not support denormals ever.
9712 SDValue LHS = N->getOperand(0);
9713 SDValue RHS = N->getOperand(1);
9714 if (LHS.getOpcode() == ISD::FADD) {
9715 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
9716 SDValue A = LHS.getOperand(0);
9717 if (A == LHS.getOperand(1)) {
9718 unsigned FusedOp = getFusedOpcode(DAG, N, LHS.getNode());
9720 const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
9721 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
9723 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS);
9728 if (RHS.getOpcode() == ISD::FADD) {
9729 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
9731 SDValue A = RHS.getOperand(0);
9732 if (A == RHS.getOperand(1)) {
9733 unsigned FusedOp = getFusedOpcode(DAG, N, RHS.getNode());
9735 const SDValue NegTwo = DAG.getConstantFP(-2.0, SL, VT);
9736 return DAG.getNode(FusedOp, SL, VT, A, NegTwo, LHS);
9744 SDValue SITargetLowering::performFMACombine(SDNode *N,
9745 DAGCombinerInfo &DCI) const {
9746 SelectionDAG &DAG = DCI.DAG;
9747 EVT VT = N->getValueType(0);
9750 if (!Subtarget->hasDot2Insts() || VT != MVT::f32)
9753 // FMA((F32)S0.x, (F32)S1. x, FMA((F32)S0.y, (F32)S1.y, (F32)z)) ->
9754 // FDOT2((V2F16)S0, (V2F16)S1, (F32)z))
9755 SDValue Op1 = N->getOperand(0);
9756 SDValue Op2 = N->getOperand(1);
9757 SDValue FMA = N->getOperand(2);
9759 if (FMA.getOpcode() != ISD::FMA ||
9760 Op1.getOpcode() != ISD::FP_EXTEND ||
9761 Op2.getOpcode() != ISD::FP_EXTEND)
9764 // fdot2_f32_f16 always flushes fp32 denormal operand and output to zero,
9765 // regardless of the denorm mode setting. Therefore, unsafe-fp-math/fp-contract
9766 // is sufficient to allow generaing fdot2.
9767 const TargetOptions &Options = DAG.getTarget().Options;
9768 if (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath ||
9769 (N->getFlags().hasAllowContract() &&
9770 FMA->getFlags().hasAllowContract())) {
9771 Op1 = Op1.getOperand(0);
9772 Op2 = Op2.getOperand(0);
9773 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9774 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9777 SDValue Vec1 = Op1.getOperand(0);
9778 SDValue Idx1 = Op1.getOperand(1);
9779 SDValue Vec2 = Op2.getOperand(0);
9781 SDValue FMAOp1 = FMA.getOperand(0);
9782 SDValue FMAOp2 = FMA.getOperand(1);
9783 SDValue FMAAcc = FMA.getOperand(2);
9785 if (FMAOp1.getOpcode() != ISD::FP_EXTEND ||
9786 FMAOp2.getOpcode() != ISD::FP_EXTEND)
9789 FMAOp1 = FMAOp1.getOperand(0);
9790 FMAOp2 = FMAOp2.getOperand(0);
9791 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9792 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9795 SDValue Vec3 = FMAOp1.getOperand(0);
9796 SDValue Vec4 = FMAOp2.getOperand(0);
9797 SDValue Idx2 = FMAOp1.getOperand(1);
9799 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) ||
9800 // Idx1 and Idx2 cannot be the same.
9804 if (Vec1 == Vec2 || Vec3 == Vec4)
9807 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16)
9810 if ((Vec1 == Vec3 && Vec2 == Vec4) ||
9811 (Vec1 == Vec4 && Vec2 == Vec3)) {
9812 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc,
9813 DAG.getTargetConstant(0, SL, MVT::i1));
9819 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
9820 DAGCombinerInfo &DCI) const {
9821 SelectionDAG &DAG = DCI.DAG;
9824 SDValue LHS = N->getOperand(0);
9825 SDValue RHS = N->getOperand(1);
9826 EVT VT = LHS.getValueType();
9827 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
9829 auto CRHS = dyn_cast<ConstantSDNode>(RHS);
9831 CRHS = dyn_cast<ConstantSDNode>(LHS);
9833 std::swap(LHS, RHS);
9834 CC = getSetCCSwappedOperands(CC);
9839 if (VT == MVT::i32 && LHS.getOpcode() == ISD::SIGN_EXTEND &&
9840 isBoolSGPR(LHS.getOperand(0))) {
9841 // setcc (sext from i1 cc), -1, ne|sgt|ult) => not cc => xor cc, -1
9842 // setcc (sext from i1 cc), -1, eq|sle|uge) => cc
9843 // setcc (sext from i1 cc), 0, eq|sge|ule) => not cc => xor cc, -1
9844 // setcc (sext from i1 cc), 0, ne|ugt|slt) => cc
9845 if ((CRHS->isAllOnesValue() &&
9846 (CC == ISD::SETNE || CC == ISD::SETGT || CC == ISD::SETULT)) ||
9847 (CRHS->isNullValue() &&
9848 (CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
9849 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
9850 DAG.getConstant(-1, SL, MVT::i1));
9851 if ((CRHS->isAllOnesValue() &&
9852 (CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
9853 (CRHS->isNullValue() &&
9854 (CC == ISD::SETNE || CC == ISD::SETUGT || CC == ISD::SETLT)))
9855 return LHS.getOperand(0);
9858 uint64_t CRHSVal = CRHS->getZExtValue();
9859 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9860 LHS.getOpcode() == ISD::SELECT &&
9861 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9862 isa<ConstantSDNode>(LHS.getOperand(2)) &&
9863 LHS.getConstantOperandVal(1) != LHS.getConstantOperandVal(2) &&
9864 isBoolSGPR(LHS.getOperand(0))) {
9866 // setcc (select cc, CT, CF), CF, eq => xor cc, -1
9867 // setcc (select cc, CT, CF), CF, ne => cc
9868 // setcc (select cc, CT, CF), CT, ne => xor cc, -1
9869 // setcc (select cc, CT, CF), CT, eq => cc
9870 uint64_t CT = LHS.getConstantOperandVal(1);
9871 uint64_t CF = LHS.getConstantOperandVal(2);
9873 if ((CF == CRHSVal && CC == ISD::SETEQ) ||
9874 (CT == CRHSVal && CC == ISD::SETNE))
9875 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
9876 DAG.getConstant(-1, SL, MVT::i1));
9877 if ((CF == CRHSVal && CC == ISD::SETNE) ||
9878 (CT == CRHSVal && CC == ISD::SETEQ))
9879 return LHS.getOperand(0);
9883 if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&
9887 // Match isinf/isfinite pattern
9888 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
9889 // (fcmp one (fabs x), inf) -> (fp_class x,
9890 // (p_normal | n_normal | p_subnormal | n_subnormal | p_zero | n_zero)
9891 if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {
9892 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
9896 const APFloat &APF = CRHS->getValueAPF();
9897 if (APF.isInfinity() && !APF.isNegative()) {
9898 const unsigned IsInfMask = SIInstrFlags::P_INFINITY |
9899 SIInstrFlags::N_INFINITY;
9900 const unsigned IsFiniteMask = SIInstrFlags::N_ZERO |
9901 SIInstrFlags::P_ZERO |
9902 SIInstrFlags::N_NORMAL |
9903 SIInstrFlags::P_NORMAL |
9904 SIInstrFlags::N_SUBNORMAL |
9905 SIInstrFlags::P_SUBNORMAL;
9906 unsigned Mask = CC == ISD::SETOEQ ? IsInfMask : IsFiniteMask;
9907 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
9908 DAG.getConstant(Mask, SL, MVT::i32));
9915 SDValue SITargetLowering::performCvtF32UByteNCombine(SDNode *N,
9916 DAGCombinerInfo &DCI) const {
9917 SelectionDAG &DAG = DCI.DAG;
9919 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
9921 SDValue Src = N->getOperand(0);
9922 SDValue Srl = N->getOperand(0);
9923 if (Srl.getOpcode() == ISD::ZERO_EXTEND)
9924 Srl = Srl.getOperand(0);
9926 // TODO: Handle (or x, (srl y, 8)) pattern when known bits are zero.
9927 if (Srl.getOpcode() == ISD::SRL) {
9928 // cvt_f32_ubyte0 (srl x, 16) -> cvt_f32_ubyte2 x
9929 // cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x
9930 // cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x
9932 if (const ConstantSDNode *C =
9933 dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
9934 Srl = DAG.getZExtOrTrunc(Srl.getOperand(0), SDLoc(Srl.getOperand(0)),
9937 unsigned SrcOffset = C->getZExtValue() + 8 * Offset;
9938 if (SrcOffset < 32 && SrcOffset % 8 == 0) {
9939 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, SL,
9945 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
9948 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9949 !DCI.isBeforeLegalizeOps());
9950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9951 if (TLI.SimplifyDemandedBits(Src, Demanded, Known, TLO)) {
9952 DCI.CommitTargetLoweringOpt(TLO);
9958 SDValue SITargetLowering::performClampCombine(SDNode *N,
9959 DAGCombinerInfo &DCI) const {
9960 ConstantFPSDNode *CSrc = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
9964 const MachineFunction &MF = DCI.DAG.getMachineFunction();
9965 const APFloat &F = CSrc->getValueAPF();
9966 APFloat Zero = APFloat::getZero(F.getSemantics());
9967 APFloat::cmpResult Cmp0 = F.compare(Zero);
9968 if (Cmp0 == APFloat::cmpLessThan ||
9969 (Cmp0 == APFloat::cmpUnordered &&
9970 MF.getInfo<SIMachineFunctionInfo>()->getMode().DX10Clamp)) {
9971 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0));
9974 APFloat One(F.getSemantics(), "1.0");
9975 APFloat::cmpResult Cmp1 = F.compare(One);
9976 if (Cmp1 == APFloat::cmpGreaterThan)
9977 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0));
9979 return SDValue(CSrc, 0);
9983 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
9984 DAGCombinerInfo &DCI) const {
9985 if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
9987 switch (N->getOpcode()) {
9989 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
9991 return performAddCombine(N, DCI);
9993 return performSubCombine(N, DCI);
9996 return performAddCarrySubCarryCombine(N, DCI);
9998 return performFAddCombine(N, DCI);
10000 return performFSubCombine(N, DCI);
10002 return performSetCCCombine(N, DCI);
10005 case ISD::FMAXNUM_IEEE:
10006 case ISD::FMINNUM_IEEE:
10011 case AMDGPUISD::FMIN_LEGACY:
10012 case AMDGPUISD::FMAX_LEGACY:
10013 return performMinMaxCombine(N, DCI);
10015 return performFMACombine(N, DCI);
10017 if (SDValue Widended = widenLoad(cast<LoadSDNode>(N), DCI))
10022 case ISD::ATOMIC_LOAD:
10023 case ISD::ATOMIC_STORE:
10024 case ISD::ATOMIC_CMP_SWAP:
10025 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
10026 case ISD::ATOMIC_SWAP:
10027 case ISD::ATOMIC_LOAD_ADD:
10028 case ISD::ATOMIC_LOAD_SUB:
10029 case ISD::ATOMIC_LOAD_AND:
10030 case ISD::ATOMIC_LOAD_OR:
10031 case ISD::ATOMIC_LOAD_XOR:
10032 case ISD::ATOMIC_LOAD_NAND:
10033 case ISD::ATOMIC_LOAD_MIN:
10034 case ISD::ATOMIC_LOAD_MAX:
10035 case ISD::ATOMIC_LOAD_UMIN:
10036 case ISD::ATOMIC_LOAD_UMAX:
10037 case ISD::ATOMIC_LOAD_FADD:
10038 case AMDGPUISD::ATOMIC_INC:
10039 case AMDGPUISD::ATOMIC_DEC:
10040 case AMDGPUISD::ATOMIC_LOAD_FMIN:
10041 case AMDGPUISD::ATOMIC_LOAD_FMAX: // TODO: Target mem intrinsics.
10042 if (DCI.isBeforeLegalize())
10044 return performMemSDNodeCombine(cast<MemSDNode>(N), DCI);
10046 return performAndCombine(N, DCI);
10048 return performOrCombine(N, DCI);
10050 return performXorCombine(N, DCI);
10051 case ISD::ZERO_EXTEND:
10052 return performZeroExtendCombine(N, DCI);
10053 case ISD::SIGN_EXTEND_INREG:
10054 return performSignExtendInRegCombine(N , DCI);
10055 case AMDGPUISD::FP_CLASS:
10056 return performClassCombine(N, DCI);
10057 case ISD::FCANONICALIZE:
10058 return performFCanonicalizeCombine(N, DCI);
10059 case AMDGPUISD::RCP:
10060 return performRcpCombine(N, DCI);
10061 case AMDGPUISD::FRACT:
10062 case AMDGPUISD::RSQ:
10063 case AMDGPUISD::RCP_LEGACY:
10064 case AMDGPUISD::RSQ_LEGACY:
10065 case AMDGPUISD::RCP_IFLAG:
10066 case AMDGPUISD::RSQ_CLAMP:
10067 case AMDGPUISD::LDEXP: {
10068 SDValue Src = N->getOperand(0);
10073 case ISD::SINT_TO_FP:
10074 case ISD::UINT_TO_FP:
10075 return performUCharToFloatCombine(N, DCI);
10076 case AMDGPUISD::CVT_F32_UBYTE0:
10077 case AMDGPUISD::CVT_F32_UBYTE1:
10078 case AMDGPUISD::CVT_F32_UBYTE2:
10079 case AMDGPUISD::CVT_F32_UBYTE3:
10080 return performCvtF32UByteNCombine(N, DCI);
10081 case AMDGPUISD::FMED3:
10082 return performFMed3Combine(N, DCI);
10083 case AMDGPUISD::CVT_PKRTZ_F16_F32:
10084 return performCvtPkRTZCombine(N, DCI);
10085 case AMDGPUISD::CLAMP:
10086 return performClampCombine(N, DCI);
10087 case ISD::SCALAR_TO_VECTOR: {
10088 SelectionDAG &DAG = DCI.DAG;
10089 EVT VT = N->getValueType(0);
10091 // v2i16 (scalar_to_vector i16:x) -> v2i16 (bitcast (any_extend i16:x))
10092 if (VT == MVT::v2i16 || VT == MVT::v2f16) {
10094 SDValue Src = N->getOperand(0);
10095 EVT EltVT = Src.getValueType();
10096 if (EltVT == MVT::f16)
10097 Src = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Src);
10099 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Src);
10100 return DAG.getNode(ISD::BITCAST, SL, VT, Ext);
10105 case ISD::EXTRACT_VECTOR_ELT:
10106 return performExtractVectorEltCombine(N, DCI);
10107 case ISD::INSERT_VECTOR_ELT:
10108 return performInsertVectorEltCombine(N, DCI);
10110 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
10113 /// Helper function for adjustWritemask
10114 static unsigned SubIdx2Lane(unsigned Idx) {
10117 case AMDGPU::sub0: return 0;
10118 case AMDGPU::sub1: return 1;
10119 case AMDGPU::sub2: return 2;
10120 case AMDGPU::sub3: return 3;
10121 case AMDGPU::sub4: return 4; // Possible with TFE/LWE
10125 /// Adjust the writemask of MIMG instructions
10126 SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
10127 SelectionDAG &DAG) const {
10128 unsigned Opcode = Node->getMachineOpcode();
10130 // Subtract 1 because the vdata output is not a MachineSDNode operand.
10131 int D16Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::d16) - 1;
10132 if (D16Idx >= 0 && Node->getConstantOperandVal(D16Idx))
10133 return Node; // not implemented for D16
10135 SDNode *Users[5] = { nullptr };
10137 unsigned DmaskIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::dmask) - 1;
10138 unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx);
10139 unsigned NewDmask = 0;
10140 unsigned TFEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::tfe) - 1;
10141 unsigned LWEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::lwe) - 1;
10142 bool UsesTFC = (Node->getConstantOperandVal(TFEIdx) ||
10143 Node->getConstantOperandVal(LWEIdx)) ? 1 : 0;
10144 unsigned TFCLane = 0;
10145 bool HasChain = Node->getNumValues() > 1;
10147 if (OldDmask == 0) {
10148 // These are folded out, but on the chance it happens don't assert.
10152 unsigned OldBitsSet = countPopulation(OldDmask);
10153 // Work out which is the TFE/LWE lane if that is enabled.
10155 TFCLane = OldBitsSet;
10158 // Try to figure out the used register components
10159 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
10162 // Don't look at users of the chain.
10163 if (I.getUse().getResNo() != 0)
10166 // Abort if we can't understand the usage
10167 if (!I->isMachineOpcode() ||
10168 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
10171 // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used.
10172 // Note that subregs are packed, i.e. Lane==0 is the first bit set
10173 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
10175 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
10177 // Check if the use is for the TFE/LWE generated result at VGPRn+1.
10178 if (UsesTFC && Lane == TFCLane) {
10181 // Set which texture component corresponds to the lane.
10183 for (unsigned i = 0, Dmask = OldDmask; (i <= Lane) && (Dmask != 0); i++) {
10184 Comp = countTrailingZeros(Dmask);
10185 Dmask &= ~(1 << Comp);
10188 // Abort if we have more than one user per component.
10193 NewDmask |= 1 << Comp;
10197 // Don't allow 0 dmask, as hardware assumes one channel enabled.
10198 bool NoChannels = !NewDmask;
10201 // No uses of the result and not using TFC. Then do nothing.
10204 // If the original dmask has one channel - then nothing to do
10205 if (OldBitsSet == 1)
10207 // Use an arbitrary dmask - required for the instruction to work
10210 // Abort if there's no change
10211 if (NewDmask == OldDmask)
10214 unsigned BitsSet = countPopulation(NewDmask);
10216 // Check for TFE or LWE - increase the number of channels by one to account
10217 // for the extra return value
10218 // This will need adjustment for D16 if this is also included in
10219 // adjustWriteMask (this function) but at present D16 are excluded.
10220 unsigned NewChannels = BitsSet + UsesTFC;
10223 AMDGPU::getMaskedMIMGOp(Node->getMachineOpcode(), NewChannels);
10224 assert(NewOpcode != -1 &&
10225 NewOpcode != static_cast<int>(Node->getMachineOpcode()) &&
10226 "failed to find equivalent MIMG op");
10228 // Adjust the writemask in the node
10229 SmallVector<SDValue, 12> Ops;
10230 Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
10231 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
10232 Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
10234 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();
10236 MVT ResultVT = NewChannels == 1 ?
10237 SVT : MVT::getVectorVT(SVT, NewChannels == 3 ? 4 :
10238 NewChannels == 5 ? 8 : NewChannels);
10239 SDVTList NewVTList = HasChain ?
10240 DAG.getVTList(ResultVT, MVT::Other) : DAG.getVTList(ResultVT);
10243 MachineSDNode *NewNode = DAG.getMachineNode(NewOpcode, SDLoc(Node),
10248 DAG.setNodeMemRefs(NewNode, Node->memoperands());
10249 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(NewNode, 1));
10252 if (NewChannels == 1) {
10253 assert(Node->hasNUsesOfValue(1, 0));
10254 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY,
10255 SDLoc(Node), Users[Lane]->getValueType(0),
10256 SDValue(NewNode, 0));
10257 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
10261 // Update the users of the node with the new indices
10262 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 5; ++i) {
10263 SDNode *User = Users[i];
10265 // Handle the special case of NoChannels. We set NewDmask to 1 above, but
10266 // Users[0] is still nullptr because channel 0 doesn't really have a use.
10267 if (i || !NoChannels)
10270 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
10271 DAG.UpdateNodeOperands(User, SDValue(NewNode, 0), Op);
10276 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
10277 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
10278 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
10279 case AMDGPU::sub3: Idx = AMDGPU::sub4; break;
10283 DAG.RemoveDeadNode(Node);
10287 static bool isFrameIndexOp(SDValue Op) {
10288 if (Op.getOpcode() == ISD::AssertZext)
10289 Op = Op.getOperand(0);
10291 return isa<FrameIndexSDNode>(Op);
10294 /// Legalize target independent instructions (e.g. INSERT_SUBREG)
10295 /// with frame index operands.
10296 /// LLVM assumes that inputs are to these instructions are registers.
10297 SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
10298 SelectionDAG &DAG) const {
10299 if (Node->getOpcode() == ISD::CopyToReg) {
10300 RegisterSDNode *DestReg = cast<RegisterSDNode>(Node->getOperand(1));
10301 SDValue SrcVal = Node->getOperand(2);
10303 // Insert a copy to a VReg_1 virtual register so LowerI1Copies doesn't have
10304 // to try understanding copies to physical registers.
10305 if (SrcVal.getValueType() == MVT::i1 &&
10306 Register::isPhysicalRegister(DestReg->getReg())) {
10308 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
10309 SDValue VReg = DAG.getRegister(
10310 MRI.createVirtualRegister(&AMDGPU::VReg_1RegClass), MVT::i1);
10312 SDNode *Glued = Node->getGluedNode();
10314 = DAG.getCopyToReg(Node->getOperand(0), SL, VReg, SrcVal,
10315 SDValue(Glued, Glued ? Glued->getNumValues() - 1 : 0));
10316 SDValue ToResultReg
10317 = DAG.getCopyToReg(ToVReg, SL, SDValue(DestReg, 0),
10318 VReg, ToVReg.getValue(1));
10319 DAG.ReplaceAllUsesWith(Node, ToResultReg.getNode());
10320 DAG.RemoveDeadNode(Node);
10321 return ToResultReg.getNode();
10325 SmallVector<SDValue, 8> Ops;
10326 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
10327 if (!isFrameIndexOp(Node->getOperand(i))) {
10328 Ops.push_back(Node->getOperand(i));
10333 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
10334 Node->getOperand(i).getValueType(),
10335 Node->getOperand(i)), 0));
10338 return DAG.UpdateNodeOperands(Node, Ops);
10341 /// Fold the instructions after selecting them.
10342 /// Returns null if users were already updated.
10343 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
10344 SelectionDAG &DAG) const {
10345 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
10346 unsigned Opcode = Node->getMachineOpcode();
10348 if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
10349 !TII->isGather4(Opcode)) {
10350 return adjustWritemask(Node, DAG);
10353 if (Opcode == AMDGPU::INSERT_SUBREG ||
10354 Opcode == AMDGPU::REG_SEQUENCE) {
10355 legalizeTargetIndependentNode(Node, DAG);
10360 case AMDGPU::V_DIV_SCALE_F32:
10361 case AMDGPU::V_DIV_SCALE_F64: {
10362 // Satisfy the operand register constraint when one of the inputs is
10363 // undefined. Ordinarily each undef value will have its own implicit_def of
10364 // a vreg, so force these to use a single register.
10365 SDValue Src0 = Node->getOperand(0);
10366 SDValue Src1 = Node->getOperand(1);
10367 SDValue Src2 = Node->getOperand(2);
10369 if ((Src0.isMachineOpcode() &&
10370 Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
10371 (Src0 == Src1 || Src0 == Src2))
10374 MVT VT = Src0.getValueType().getSimpleVT();
10375 const TargetRegisterClass *RC =
10376 getRegClassFor(VT, Src0.getNode()->isDivergent());
10378 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
10379 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT);
10381 SDValue ImpDef = DAG.getCopyToReg(DAG.getEntryNode(), SDLoc(Node),
10382 UndefReg, Src0, SDValue());
10384 // src0 must be the same register as src1 or src2, even if the value is
10385 // undefined, so make sure we don't violate this constraint.
10386 if (Src0.isMachineOpcode() &&
10387 Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
10388 if (Src1.isMachineOpcode() &&
10389 Src1.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
10391 else if (Src2.isMachineOpcode() &&
10392 Src2.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
10395 assert(Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF);
10402 SmallVector<SDValue, 4> Ops = { Src0, Src1, Src2 };
10403 for (unsigned I = 3, N = Node->getNumOperands(); I != N; ++I)
10404 Ops.push_back(Node->getOperand(I));
10406 Ops.push_back(ImpDef.getValue(1));
10407 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
10409 case AMDGPU::V_PERMLANE16_B32:
10410 case AMDGPU::V_PERMLANEX16_B32: {
10411 ConstantSDNode *FI = cast<ConstantSDNode>(Node->getOperand(0));
10412 ConstantSDNode *BC = cast<ConstantSDNode>(Node->getOperand(2));
10413 if (!FI->getZExtValue() && !BC->getZExtValue())
10415 SDValue VDstIn = Node->getOperand(6);
10416 if (VDstIn.isMachineOpcode()
10417 && VDstIn.getMachineOpcode() == AMDGPU::IMPLICIT_DEF)
10419 MachineSDNode *ImpDef = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
10420 SDLoc(Node), MVT::i32);
10421 SmallVector<SDValue, 8> Ops = { SDValue(FI, 0), Node->getOperand(1),
10422 SDValue(BC, 0), Node->getOperand(3),
10423 Node->getOperand(4), Node->getOperand(5),
10424 SDValue(ImpDef, 0), Node->getOperand(7) };
10425 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
10434 /// Assign the register class depending on the number of
10435 /// bits set in the writemask
10436 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
10437 SDNode *Node) const {
10438 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
10440 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
10442 if (TII->isVOP3(MI.getOpcode())) {
10443 // Make sure constant bus requirements are respected.
10444 TII->legalizeOperandsVOP3(MRI, MI);
10446 // Prefer VGPRs over AGPRs in mAI instructions where possible.
10447 // This saves a chain-copy of registers and better ballance register
10448 // use between vgpr and agpr as agpr tuples tend to be big.
10449 if (const MCOperandInfo *OpInfo = MI.getDesc().OpInfo) {
10450 unsigned Opc = MI.getOpcode();
10451 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10452 for (auto I : { AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
10453 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) }) {
10456 MachineOperand &Op = MI.getOperand(I);
10457 if ((OpInfo[I].RegClass != llvm::AMDGPU::AV_64RegClassID &&
10458 OpInfo[I].RegClass != llvm::AMDGPU::AV_32RegClassID) ||
10459 !Register::isVirtualRegister(Op.getReg()) ||
10460 !TRI->isAGPR(MRI, Op.getReg()))
10462 auto *Src = MRI.getUniqueVRegDef(Op.getReg());
10463 if (!Src || !Src->isCopy() ||
10464 !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg()))
10466 auto *RC = TRI->getRegClassForReg(MRI, Op.getReg());
10467 auto *NewRC = TRI->getEquivalentVGPRClass(RC);
10468 // All uses of agpr64 and agpr32 can also accept vgpr except for
10469 // v_accvgpr_read, but we do not produce agpr reads during selection,
10470 // so no use checks are needed.
10471 MRI.setRegClass(Op.getReg(), NewRC);
10478 // Replace unused atomics with the no return version.
10479 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode());
10480 if (NoRetAtomicOp != -1) {
10481 if (!Node->hasAnyUseOfValue(0)) {
10482 MI.setDesc(TII->get(NoRetAtomicOp));
10483 MI.RemoveOperand(0);
10487 // For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
10488 // instruction, because the return type of these instructions is a vec2 of
10489 // the memory type, so it can be tied to the input operand.
10490 // This means these instructions always have a use, so we need to add a
10491 // special case to check if the atomic has only one extract_subreg use,
10492 // which itself has no uses.
10493 if ((Node->hasNUsesOfValue(1, 0) &&
10494 Node->use_begin()->isMachineOpcode() &&
10495 Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
10496 !Node->use_begin()->hasAnyUseOfValue(0))) {
10497 Register Def = MI.getOperand(0).getReg();
10499 // Change this into a noret atomic.
10500 MI.setDesc(TII->get(NoRetAtomicOp));
10501 MI.RemoveOperand(0);
10503 // If we only remove the def operand from the atomic instruction, the
10504 // extract_subreg will be left with a use of a vreg without a def.
10505 // So we need to insert an implicit_def to avoid machine verifier
10507 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
10508 TII->get(AMDGPU::IMPLICIT_DEF), Def);
10514 static SDValue buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL,
10516 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
10517 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
10520 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
10522 SDValue Ptr) const {
10523 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
10525 // Build the half of the subregister with the constants before building the
10526 // full 128-bit register. If we are building multiple resource descriptors,
10527 // this will allow CSEing of the 2-component register.
10528 const SDValue Ops0[] = {
10529 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
10530 buildSMovImm32(DAG, DL, 0),
10531 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
10532 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
10533 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
10536 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
10537 MVT::v2i32, Ops0), 0);
10539 // Combine the constants and the pointer.
10540 const SDValue Ops1[] = {
10541 DAG.getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32),
10543 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
10545 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
10548 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
10551 /// Return a resource descriptor with the 'Add TID' bit enabled
10552 /// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
10553 /// of the resource descriptor) to create an offset, which is added to
10554 /// the resource pointer.
10555 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
10556 SDValue Ptr, uint32_t RsrcDword1,
10557 uint64_t RsrcDword2And3) const {
10558 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
10559 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
10561 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
10562 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
10566 SDValue DataLo = buildSMovImm32(DAG, DL,
10567 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
10568 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
10570 const SDValue Ops[] = {
10571 DAG.getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32),
10573 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
10575 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
10577 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
10579 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
10582 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
10585 //===----------------------------------------------------------------------===//
10586 // SI Inline Assembly Support
10587 //===----------------------------------------------------------------------===//
10589 std::pair<unsigned, const TargetRegisterClass *>
10590 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10591 StringRef Constraint,
10593 const TargetRegisterClass *RC = nullptr;
10594 if (Constraint.size() == 1) {
10595 switch (Constraint[0]) {
10597 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10600 switch (VT.getSizeInBits()) {
10602 return std::make_pair(0U, nullptr);
10605 RC = &AMDGPU::SReg_32RegClass;
10608 RC = &AMDGPU::SGPR_64RegClass;
10611 RC = &AMDGPU::SReg_96RegClass;
10614 RC = &AMDGPU::SGPR_128RegClass;
10617 RC = &AMDGPU::SReg_160RegClass;
10620 RC = &AMDGPU::SReg_256RegClass;
10623 RC = &AMDGPU::SReg_512RegClass;
10628 switch (VT.getSizeInBits()) {
10630 return std::make_pair(0U, nullptr);
10633 RC = &AMDGPU::VGPR_32RegClass;
10636 RC = &AMDGPU::VReg_64RegClass;
10639 RC = &AMDGPU::VReg_96RegClass;
10642 RC = &AMDGPU::VReg_128RegClass;
10645 RC = &AMDGPU::VReg_160RegClass;
10648 RC = &AMDGPU::VReg_256RegClass;
10651 RC = &AMDGPU::VReg_512RegClass;
10656 if (!Subtarget->hasMAIInsts())
10658 switch (VT.getSizeInBits()) {
10660 return std::make_pair(0U, nullptr);
10663 RC = &AMDGPU::AGPR_32RegClass;
10666 RC = &AMDGPU::AReg_64RegClass;
10669 RC = &AMDGPU::AReg_128RegClass;
10672 RC = &AMDGPU::AReg_512RegClass;
10675 RC = &AMDGPU::AReg_1024RegClass;
10676 // v32 types are not legal but we support them here.
10677 return std::make_pair(0U, RC);
10681 // We actually support i128, i16 and f16 as inline parameters
10682 // even if they are not reported as legal
10683 if (RC && (isTypeLegal(VT) || VT.SimpleTy == MVT::i128 ||
10684 VT.SimpleTy == MVT::i16 || VT.SimpleTy == MVT::f16))
10685 return std::make_pair(0U, RC);
10688 if (Constraint.size() > 1) {
10689 if (Constraint[1] == 'v') {
10690 RC = &AMDGPU::VGPR_32RegClass;
10691 } else if (Constraint[1] == 's') {
10692 RC = &AMDGPU::SGPR_32RegClass;
10693 } else if (Constraint[1] == 'a') {
10694 RC = &AMDGPU::AGPR_32RegClass;
10699 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
10700 if (!Failed && Idx < RC->getNumRegs())
10701 return std::make_pair(RC->getRegister(Idx), RC);
10704 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10707 SITargetLowering::ConstraintType
10708 SITargetLowering::getConstraintType(StringRef Constraint) const {
10709 if (Constraint.size() == 1) {
10710 switch (Constraint[0]) {
10715 return C_RegisterClass;
10718 return TargetLowering::getConstraintType(Constraint);
10721 // Figure out which registers should be reserved for stack access. Only after
10722 // the function is legalized do we know all of the non-spill stack objects or if
10723 // calls are present.
10724 void SITargetLowering::finalizeLowering(MachineFunction &MF) const {
10725 MachineRegisterInfo &MRI = MF.getRegInfo();
10726 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
10727 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
10728 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10730 if (Info->isEntryFunction()) {
10731 // Callable functions have fixed registers used for stack access.
10732 reservePrivateMemoryRegs(getTargetMachine(), MF, *TRI, *Info);
10735 assert(!TRI->isSubRegister(Info->getScratchRSrcReg(),
10736 Info->getStackPtrOffsetReg()));
10737 if (Info->getStackPtrOffsetReg() != AMDGPU::SP_REG)
10738 MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());
10740 // We need to worry about replacing the default register with itself in case
10741 // of MIR testcases missing the MFI.
10742 if (Info->getScratchRSrcReg() != AMDGPU::PRIVATE_RSRC_REG)
10743 MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());
10745 if (Info->getFrameOffsetReg() != AMDGPU::FP_REG)
10746 MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());
10748 if (Info->getScratchWaveOffsetReg() != AMDGPU::SCRATCH_WAVE_OFFSET_REG) {
10749 MRI.replaceRegWith(AMDGPU::SCRATCH_WAVE_OFFSET_REG,
10750 Info->getScratchWaveOffsetReg());
10753 Info->limitOccupancy(MF);
10755 if (ST.isWave32() && !MF.empty()) {
10756 // Add VCC_HI def because many instructions marked as imp-use VCC where
10757 // we may only define VCC_LO. If nothing defines VCC_HI we may end up
10758 // having a use of undef.
10760 const SIInstrInfo *TII = ST.getInstrInfo();
10763 MachineBasicBlock &MBB = MF.front();
10764 MachineBasicBlock::iterator I = MBB.getFirstNonDebugInstr();
10765 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), AMDGPU::VCC_HI);
10767 for (auto &MBB : MF) {
10768 for (auto &MI : MBB) {
10769 TII->fixImplicitOperands(MI);
10774 TargetLoweringBase::finalizeLowering(MF);
10777 void SITargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
10779 const APInt &DemandedElts,
10780 const SelectionDAG &DAG,
10781 unsigned Depth) const {
10782 TargetLowering::computeKnownBitsForFrameIndex(Op, Known, DemandedElts,
10785 // Set the high bits to zero based on the maximum allowed scratch size per
10786 // wave. We can't use vaddr in MUBUF instructions if we don't know the address
10787 // calculation won't overflow, so assume the sign bit is never set.
10788 Known.Zero.setHighBits(getSubtarget()->getKnownHighZeroBitsForFrameIndex());
10791 Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10792 const Align PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
10793 const Align CacheLineAlign = Align(64);
10795 // Pre-GFX10 target did not benefit from loop alignment
10796 if (!ML || DisableLoopAlignment ||
10797 (getSubtarget()->getGeneration() < AMDGPUSubtarget::GFX10) ||
10798 getSubtarget()->hasInstFwdPrefetchBug())
10801 // On GFX10 I$ is 4 x 64 bytes cache lines.
10802 // By default prefetcher keeps one cache line behind and reads two ahead.
10803 // We can modify it with S_INST_PREFETCH for larger loops to have two lines
10804 // behind and one ahead.
10805 // Therefor we can benefit from aligning loop headers if loop fits 192 bytes.
10806 // If loop fits 64 bytes it always spans no more than two cache lines and
10807 // does not need an alignment.
10808 // Else if loop is less or equal 128 bytes we do not need to modify prefetch,
10809 // Else if loop is less or equal 192 bytes we need two lines behind.
10811 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
10812 const MachineBasicBlock *Header = ML->getHeader();
10813 if (Header->getAlignment() != PrefAlign)
10814 return Header->getAlignment(); // Already processed.
10816 unsigned LoopSize = 0;
10817 for (const MachineBasicBlock *MBB : ML->blocks()) {
10818 // If inner loop block is aligned assume in average half of the alignment
10819 // size to be added as nops.
10821 LoopSize += MBB->getAlignment().value() / 2;
10823 for (const MachineInstr &MI : *MBB) {
10824 LoopSize += TII->getInstSizeInBytes(MI);
10825 if (LoopSize > 192)
10830 if (LoopSize <= 64)
10833 if (LoopSize <= 128)
10834 return CacheLineAlign;
10836 // If any of parent loops is surrounded by prefetch instructions do not
10837 // insert new for inner loop, which would reset parent's settings.
10838 for (MachineLoop *P = ML->getParentLoop(); P; P = P->getParentLoop()) {
10839 if (MachineBasicBlock *Exit = P->getExitBlock()) {
10840 auto I = Exit->getFirstNonDebugInstr();
10841 if (I != Exit->end() && I->getOpcode() == AMDGPU::S_INST_PREFETCH)
10842 return CacheLineAlign;
10846 MachineBasicBlock *Pre = ML->getLoopPreheader();
10847 MachineBasicBlock *Exit = ML->getExitBlock();
10850 BuildMI(*Pre, Pre->getFirstTerminator(), DebugLoc(),
10851 TII->get(AMDGPU::S_INST_PREFETCH))
10852 .addImm(1); // prefetch 2 lines behind PC
10854 BuildMI(*Exit, Exit->getFirstNonDebugInstr(), DebugLoc(),
10855 TII->get(AMDGPU::S_INST_PREFETCH))
10856 .addImm(2); // prefetch 1 line behind PC
10859 return CacheLineAlign;
10862 LLVM_ATTRIBUTE_UNUSED
10863 static bool isCopyFromRegOfInlineAsm(const SDNode *N) {
10864 assert(N->getOpcode() == ISD::CopyFromReg);
10866 // Follow the chain until we find an INLINEASM node.
10867 N = N->getOperand(0).getNode();
10868 if (N->getOpcode() == ISD::INLINEASM ||
10869 N->getOpcode() == ISD::INLINEASM_BR)
10871 } while (N->getOpcode() == ISD::CopyFromReg);
10875 bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
10876 FunctionLoweringInfo * FLI, LegacyDivergenceAnalysis * KDA) const
10878 switch (N->getOpcode()) {
10879 case ISD::CopyFromReg:
10881 const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
10882 const MachineFunction * MF = FLI->MF;
10883 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
10884 const MachineRegisterInfo &MRI = MF->getRegInfo();
10885 const SIRegisterInfo &TRI = ST.getInstrInfo()->getRegisterInfo();
10886 unsigned Reg = R->getReg();
10887 if (Register::isPhysicalRegister(Reg))
10888 return !TRI.isSGPRReg(MRI, Reg);
10890 if (MRI.isLiveIn(Reg)) {
10891 // workitem.id.x workitem.id.y workitem.id.z
10892 // Any VGPR formal argument is also considered divergent
10893 if (!TRI.isSGPRReg(MRI, Reg))
10895 // Formal arguments of non-entry functions
10896 // are conservatively considered divergent
10897 else if (!AMDGPU::isEntryFunctionCC(FLI->Fn->getCallingConv()))
10901 const Value *V = FLI->getValueFromVirtualReg(Reg);
10903 return KDA->isDivergent(V);
10904 assert(Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N));
10905 return !TRI.isSGPRReg(MRI, Reg);
10909 const LoadSDNode *L = cast<LoadSDNode>(N);
10910 unsigned AS = L->getAddressSpace();
10911 // A flat load may access private memory.
10912 return AS == AMDGPUAS::PRIVATE_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS;
10914 case ISD::CALLSEQ_END:
10917 case ISD::INTRINSIC_WO_CHAIN:
10921 return AMDGPU::isIntrinsicSourceOfDivergence(
10922 cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
10923 case ISD::INTRINSIC_W_CHAIN:
10924 return AMDGPU::isIntrinsicSourceOfDivergence(
10925 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
10930 bool SITargetLowering::denormalsEnabledForType(const SelectionDAG &DAG,
10932 switch (VT.getScalarType().getSimpleVT().SimpleTy) {
10934 return hasFP32Denormals(DAG.getMachineFunction());
10937 return hasFP64FP16Denormals(DAG.getMachineFunction());
10943 bool SITargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
10944 const SelectionDAG &DAG,
10946 unsigned Depth) const {
10947 if (Op.getOpcode() == AMDGPUISD::CLAMP) {
10948 const MachineFunction &MF = DAG.getMachineFunction();
10949 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
10951 if (Info->getMode().DX10Clamp)
10952 return true; // Clamped to 0.
10953 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
10956 return AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(Op, DAG,
10960 TargetLowering::AtomicExpansionKind
10961 SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
10962 switch (RMW->getOperation()) {
10963 case AtomicRMWInst::FAdd: {
10964 Type *Ty = RMW->getType();
10966 // We don't have a way to support 16-bit atomics now, so just leave them
10968 if (Ty->isHalfTy())
10969 return AtomicExpansionKind::None;
10971 if (!Ty->isFloatTy())
10972 return AtomicExpansionKind::CmpXChg;
10974 // TODO: Do have these for flat. Older targets also had them for buffers.
10975 unsigned AS = RMW->getPointerAddressSpace();
10977 if (AS == AMDGPUAS::GLOBAL_ADDRESS && Subtarget->hasAtomicFaddInsts()) {
10978 return RMW->use_empty() ? AtomicExpansionKind::None :
10979 AtomicExpansionKind::CmpXChg;
10982 return (AS == AMDGPUAS::LOCAL_ADDRESS && Subtarget->hasLDSFPAtomics()) ?
10983 AtomicExpansionKind::None : AtomicExpansionKind::CmpXChg;
10989 return AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(RMW);
10992 const TargetRegisterClass *
10993 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
10994 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);
10995 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10996 if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)
10997 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass
10998 : &AMDGPU::SReg_32RegClass;
10999 if (!TRI->isSGPRClass(RC) && !isDivergent)
11000 return TRI->getEquivalentSGPRClass(RC);
11001 else if (TRI->isSGPRClass(RC) && isDivergent)
11002 return TRI->getEquivalentVGPRClass(RC);
11007 static bool hasCFUser(const Value *V, SmallPtrSet<const Value *, 16> &Visited) {
11008 if (!isa<Instruction>(V))
11010 if (!Visited.insert(V).second)
11012 bool Result = false;
11013 for (auto U : V->users()) {
11014 if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(U)) {
11015 if (V == U->getOperand(1)) {
11016 switch (Intrinsic->getIntrinsicID()) {
11020 case Intrinsic::amdgcn_if_break:
11021 case Intrinsic::amdgcn_if:
11022 case Intrinsic::amdgcn_else:
11027 if (V == U->getOperand(0)) {
11028 switch (Intrinsic->getIntrinsicID()) {
11032 case Intrinsic::amdgcn_end_cf:
11033 case Intrinsic::amdgcn_loop:
11039 Result = hasCFUser(U, Visited);
11047 bool SITargetLowering::requiresUniformRegister(MachineFunction &MF,
11048 const Value *V) const {
11049 if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
11050 switch (Intrinsic->getIntrinsicID()) {
11053 case Intrinsic::amdgcn_if_break:
11057 if (const ExtractValueInst *ExtValue = dyn_cast<ExtractValueInst>(V)) {
11058 if (const IntrinsicInst *Intrinsic =
11059 dyn_cast<IntrinsicInst>(ExtValue->getOperand(0))) {
11060 switch (Intrinsic->getIntrinsicID()) {
11063 case Intrinsic::amdgcn_if:
11064 case Intrinsic::amdgcn_else: {
11065 ArrayRef<unsigned> Indices = ExtValue->getIndices();
11066 if (Indices.size() == 1 && Indices[0] == 1) {
11073 if (const CallInst *CI = dyn_cast<CallInst>(V)) {
11074 if (isa<InlineAsm>(CI->getCalledValue())) {
11075 const SIRegisterInfo *SIRI = Subtarget->getRegisterInfo();
11076 ImmutableCallSite CS(CI);
11077 TargetLowering::AsmOperandInfoVector TargetConstraints = ParseConstraints(
11078 MF.getDataLayout(), Subtarget->getRegisterInfo(), CS);
11079 for (auto &TC : TargetConstraints) {
11080 if (TC.Type == InlineAsm::isOutput) {
11081 ComputeConstraintToUse(TC, SDValue());
11082 unsigned AssignedReg;
11083 const TargetRegisterClass *RC;
11084 std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint(
11085 SIRI, TC.ConstraintCode, TC.ConstraintVT);
11087 MachineRegisterInfo &MRI = MF.getRegInfo();
11088 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg))
11090 else if (SIRI->isSGPRClass(RC))
11097 SmallPtrSet<const Value *, 16> Visited;
11098 return hasCFUser(V, Visited);