1 //===- SIPreAllocateWWMRegs.cpp - WWM Register Pre-allocation -------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Pass to pre-allocated WWM registers
12 //===----------------------------------------------------------------------===//
15 #include "AMDGPUSubtarget.h"
16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
17 #include "SIInstrInfo.h"
18 #include "SIMachineFunctionInfo.h"
19 #include "SIRegisterInfo.h"
20 #include "llvm/ADT/PostOrderIterator.h"
21 #include "llvm/CodeGen/LiveInterval.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LiveRegMatrix.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/RegisterClassInfo.h"
27 #include "llvm/CodeGen/VirtRegMap.h"
28 #include "llvm/InitializePasses.h"
32 #define DEBUG_TYPE "si-pre-allocate-wwm-regs"
36 class SIPreAllocateWWMRegs : public MachineFunctionPass {
38 const SIInstrInfo *TII;
39 const SIRegisterInfo *TRI;
40 MachineRegisterInfo *MRI;
42 LiveRegMatrix *Matrix;
44 RegisterClassInfo RegClassInfo;
46 std::vector<unsigned> RegsToRewrite;
51 SIPreAllocateWWMRegs() : MachineFunctionPass(ID) {
52 initializeSIPreAllocateWWMRegsPass(*PassRegistry::getPassRegistry());
55 bool runOnMachineFunction(MachineFunction &MF) override;
57 void getAnalysisUsage(AnalysisUsage &AU) const override {
58 AU.addRequired<LiveIntervals>();
59 AU.addPreserved<LiveIntervals>();
60 AU.addRequired<VirtRegMap>();
61 AU.addRequired<LiveRegMatrix>();
62 AU.addPreserved<SlotIndexes>();
64 MachineFunctionPass::getAnalysisUsage(AU);
68 bool processDef(MachineOperand &MO);
69 void rewriteRegs(MachineFunction &MF);
72 } // End anonymous namespace.
74 INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegs, DEBUG_TYPE,
75 "SI Pre-allocate WWM Registers", false, false)
76 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
77 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
78 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
79 INITIALIZE_PASS_END(SIPreAllocateWWMRegs, DEBUG_TYPE,
80 "SI Pre-allocate WWM Registers", false, false)
82 char SIPreAllocateWWMRegs::ID = 0;
84 char &llvm::SIPreAllocateWWMRegsID = SIPreAllocateWWMRegs::ID;
86 FunctionPass *llvm::createSIPreAllocateWWMRegsPass() {
87 return new SIPreAllocateWWMRegs();
90 bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) {
94 Register Reg = MO.getReg();
96 if (!TRI->isVGPR(*MRI, Reg))
99 if (Register::isPhysicalRegister(Reg))
102 if (VRM->hasPhys(Reg))
105 LiveInterval &LI = LIS->getInterval(Reg);
107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
108 if (!MRI->isPhysRegUsed(PhysReg) &&
109 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) {
110 Matrix->assign(LI, PhysReg);
111 assert(PhysReg != 0);
112 RegsToRewrite.push_back(Reg);
117 llvm_unreachable("physreg not found for WWM expression");
121 void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) {
122 for (MachineBasicBlock &MBB : MF) {
123 for (MachineInstr &MI : MBB) {
124 for (MachineOperand &MO : MI.operands()) {
128 const Register VirtReg = MO.getReg();
129 if (Register::isPhysicalRegister(VirtReg))
132 if (!VRM->hasPhys(VirtReg))
135 Register PhysReg = VRM->getPhys(VirtReg);
136 const unsigned SubReg = MO.getSubReg();
138 PhysReg = TRI->getSubReg(PhysReg, SubReg);
143 MO.setIsRenamable(false);
148 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
150 for (unsigned Reg : RegsToRewrite) {
151 LIS->removeInterval(Reg);
153 const Register PhysReg = VRM->getPhys(Reg);
154 assert(PhysReg != 0);
155 MFI->ReserveWWMRegister(PhysReg);
158 RegsToRewrite.clear();
160 // Update the set of reserved registers to include WWM ones.
161 MRI->freezeReservedRegs(MF);
164 bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
165 LLVM_DEBUG(dbgs() << "SIPreAllocateWWMRegs: function " << MF.getName() << "\n");
167 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
169 TII = ST.getInstrInfo();
170 TRI = &TII->getRegisterInfo();
171 MRI = &MF.getRegInfo();
173 LIS = &getAnalysis<LiveIntervals>();
174 Matrix = &getAnalysis<LiveRegMatrix>();
175 VRM = &getAnalysis<VirtRegMap>();
177 RegClassInfo.runOnMachineFunction(MF);
179 bool RegsAssigned = false;
181 // We use a reverse post-order traversal of the control-flow graph to
182 // guarantee that we visit definitions in dominance order. Since WWM
183 // expressions are guaranteed to never involve phi nodes, and we can only
184 // escape WWM through the special WWM instruction, this means that this is a
185 // perfect elimination order, so we can never do any better.
186 ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);
188 for (MachineBasicBlock *MBB : RPOT) {
190 for (MachineInstr &MI : *MBB) {
191 if (MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B32 ||
192 MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64)
193 RegsAssigned |= processDef(MI.getOperand(0));
195 if (MI.getOpcode() == AMDGPU::ENTER_WWM) {
196 LLVM_DEBUG(dbgs() << "entering WWM region: " << MI << "\n");
201 if (MI.getOpcode() == AMDGPU::EXIT_WWM) {
202 LLVM_DEBUG(dbgs() << "exiting WWM region: " << MI << "\n");
209 LLVM_DEBUG(dbgs() << "processing " << MI << "\n");
211 for (MachineOperand &DefOpnd : MI.defs()) {
212 RegsAssigned |= processDef(DefOpnd);