1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print
14 //===----------------------------------------------------------------------===//
17 #include "AMDGPUPALMetadata.h"
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "SIDefines.h"
22 #include "llvm/BinaryFormat/ELF.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Module.h"
26 #include "llvm/Support/AMDGPUMetadata.h"
27 #include "llvm/Support/EndianStream.h"
30 using namespace llvm::AMDGPU;
32 // Read the PAL metadata from IR metadata, where it was put by the frontend.
33 void AMDGPUPALMetadata::readFromIR(Module &M) {
34 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
35 if (NamedMD && NamedMD->getNumOperands()) {
36 // This is the new msgpack format for metadata. It is a NamedMD containing
37 // an MDTuple containing an MDString containing the msgpack data.
38 BlobType = ELF::NT_AMDGPU_METADATA;
39 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
40 if (MDN && MDN->getNumOperands()) {
41 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
42 setFromMsgPackBlob(MDS->getString());
46 BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
47 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
48 if (!NamedMD || !NamedMD->getNumOperands())
50 // This is the old reg=value pair format for metadata. It is a NamedMD
51 // containing an MDTuple containing a number of MDNodes each of which is an
52 // integer value, and each two integer values forms a key=value pair that we
53 // store as Registers[key]=value in the map.
54 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
57 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
58 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
59 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
62 setRegister(Key->getZExtValue(), Val->getZExtValue());
66 // Set PAL metadata from a binary blob from the applicable .note record.
67 // Returns false if bad format. Blob must remain valid for the lifetime of the
69 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
71 if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
72 return setFromLegacyBlob(Blob);
73 return setFromMsgPackBlob(Blob);
76 // Set PAL metadata from legacy (array of key=value pairs) blob.
77 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
78 auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
79 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
80 setRegister(Data[I * 2], Data[I * 2 + 1]);
84 // Set PAL metadata from msgpack blob.
85 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
86 msgpack::Reader Reader(Blob);
87 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
90 // Given the calling convention, calculate the register number for rsrc1. In
91 // principle the register number could change in future hardware, but we know
92 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
93 // we can use fixed values.
94 static unsigned getRsrc1Reg(CallingConv::ID CC) {
97 return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
98 case CallingConv::AMDGPU_LS:
99 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
100 case CallingConv::AMDGPU_HS:
101 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
102 case CallingConv::AMDGPU_ES:
103 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
104 case CallingConv::AMDGPU_GS:
105 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
106 case CallingConv::AMDGPU_VS:
107 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
108 case CallingConv::AMDGPU_PS:
109 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
113 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
114 // with a constant offset to access any non-register shader-specific PAL
116 static unsigned getScratchSizeKey(CallingConv::ID CC) {
118 case CallingConv::AMDGPU_PS:
119 return PALMD::Key::PS_SCRATCH_SIZE;
120 case CallingConv::AMDGPU_VS:
121 return PALMD::Key::VS_SCRATCH_SIZE;
122 case CallingConv::AMDGPU_GS:
123 return PALMD::Key::GS_SCRATCH_SIZE;
124 case CallingConv::AMDGPU_ES:
125 return PALMD::Key::ES_SCRATCH_SIZE;
126 case CallingConv::AMDGPU_HS:
127 return PALMD::Key::HS_SCRATCH_SIZE;
128 case CallingConv::AMDGPU_LS:
129 return PALMD::Key::LS_SCRATCH_SIZE;
131 return PALMD::Key::CS_SCRATCH_SIZE;
135 // Set the rsrc1 register in the metadata for a particular shader stage.
136 // In fact this ORs the value into any previous setting of the register.
137 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
138 setRegister(getRsrc1Reg(CC), Val);
141 // Set the rsrc2 register in the metadata for a particular shader stage.
142 // In fact this ORs the value into any previous setting of the register.
143 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
144 setRegister(getRsrc1Reg(CC) + 1, Val);
147 // Set the SPI_PS_INPUT_ENA register in the metadata.
148 // In fact this ORs the value into any previous setting of the register.
149 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
150 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
153 // Set the SPI_PS_INPUT_ADDR register in the metadata.
154 // In fact this ORs the value into any previous setting of the register.
155 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
156 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
159 // Get a register from the metadata, or 0 if not currently set.
160 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
161 auto Regs = getRegisters();
162 auto It = Regs.find(MsgPackDoc.getNode(Reg));
163 if (It == Regs.end())
166 if (N.getKind() != msgpack::Type::UInt)
171 // Set a register in the metadata.
172 // In fact this ORs the value into any previous setting of the register.
173 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
175 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
176 // is a PAL ABI pseudo-register in the old non-MsgPack format.
177 if (Reg >= 0x10000000)
180 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
181 if (N.getKind() == msgpack::Type::UInt)
183 N = N.getDocument()->getNode(Val);
186 // Set the entry point name for one shader.
187 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
191 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
194 // Set the number of used vgprs in the metadata. This is an optional
195 // advisory record for logging etc; wave dispatch actually uses the rsrc1
196 // register for the shader stage to determine the number of vgprs to
198 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
200 // Old non-msgpack format.
201 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
202 PALMD::Key::VS_NUM_USED_VGPRS -
203 PALMD::Key::VS_SCRATCH_SIZE;
204 setRegister(NumUsedVgprsKey, Val);
208 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
211 // Set the number of used sgprs in the metadata. This is an optional advisory
212 // record for logging etc; wave dispatch actually uses the rsrc1 register for
213 // the shader stage to determine the number of sgprs to allocate.
214 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
216 // Old non-msgpack format.
217 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
218 PALMD::Key::VS_NUM_USED_SGPRS -
219 PALMD::Key::VS_SCRATCH_SIZE;
220 setRegister(NumUsedSgprsKey, Val);
224 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
227 // Set the scratch size in the metadata.
228 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
230 // Old non-msgpack format.
231 setRegister(getScratchSizeKey(CC), Val);
235 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
238 // Set the hardware register bit in PAL metadata to enable wave32 on the
239 // shader of the given calling convention.
240 void AMDGPUPALMetadata::setWave32(unsigned CC) {
242 case CallingConv::AMDGPU_HS:
243 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
245 case CallingConv::AMDGPU_GS:
246 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
248 case CallingConv::AMDGPU_VS:
249 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
251 case CallingConv::AMDGPU_PS:
252 setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
254 case CallingConv::AMDGPU_CS:
255 setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
256 S_00B800_CS_W32_EN(1));
261 // Convert a register number to name, for display by toString().
262 // Returns nullptr if none.
263 static const char *getRegisterName(unsigned RegNum) {
264 // Table of registers.
265 static const struct RegInfo {
269 // Registers that code generation sets/modifies metadata for.
270 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
271 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
272 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
273 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
274 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
275 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
276 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
277 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
278 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
279 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
280 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
281 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
282 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
283 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
284 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
285 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
286 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
287 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
288 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
290 // Registers not known to code generation.
291 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
292 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
293 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
294 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
295 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
296 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
298 {0xa1c3, "SPI_SHADER_POS_FORMAT"},
299 {0xa1b1, "SPI_VS_OUT_CONFIG"},
300 {0xa207, "PA_CL_VS_OUT_CNTL"},
301 {0xa204, "PA_CL_CLIP_CNTL"},
302 {0xa206, "PA_CL_VTE_CNTL"},
303 {0xa2f9, "PA_SU_VTX_CNTL"},
304 {0xa293, "PA_SC_MODE_CNTL_1"},
305 {0xa2a1, "VGT_PRIMITIVEID_EN"},
306 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
307 {0x2e18, "COMPUTE_TMPRING_SIZE"},
308 {0xa1b5, "SPI_INTERP_CONTROL_0"},
309 {0xa1ba, "SPI_TMPRING_SIZE"},
310 {0xa1c4, "SPI_SHADER_Z_FORMAT"},
311 {0xa1c5, "SPI_SHADER_COL_FORMAT"},
312 {0xa203, "DB_SHADER_CONTROL"},
313 {0xa08f, "CB_SHADER_MASK"},
314 {0xa191, "SPI_PS_INPUT_CNTL_0"},
315 {0xa192, "SPI_PS_INPUT_CNTL_1"},
316 {0xa193, "SPI_PS_INPUT_CNTL_2"},
317 {0xa194, "SPI_PS_INPUT_CNTL_3"},
318 {0xa195, "SPI_PS_INPUT_CNTL_4"},
319 {0xa196, "SPI_PS_INPUT_CNTL_5"},
320 {0xa197, "SPI_PS_INPUT_CNTL_6"},
321 {0xa198, "SPI_PS_INPUT_CNTL_7"},
322 {0xa199, "SPI_PS_INPUT_CNTL_8"},
323 {0xa19a, "SPI_PS_INPUT_CNTL_9"},
324 {0xa19b, "SPI_PS_INPUT_CNTL_10"},
325 {0xa19c, "SPI_PS_INPUT_CNTL_11"},
326 {0xa19d, "SPI_PS_INPUT_CNTL_12"},
327 {0xa19e, "SPI_PS_INPUT_CNTL_13"},
328 {0xa19f, "SPI_PS_INPUT_CNTL_14"},
329 {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
330 {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
331 {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
332 {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
333 {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
334 {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
335 {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
336 {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
337 {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
338 {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
339 {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
340 {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
341 {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
342 {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
343 {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
344 {0xa1af, "SPI_PS_INPUT_CNTL_30"},
345 {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
347 {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
348 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
349 {0xa290, "VGT_GS_MODE"},
350 {0xa291, "VGT_GS_ONCHIP_CNTL"},
351 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
352 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
353 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
354 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
355 {0xa298, "VGT_GSVS_RING_OFFSET_1"},
356 {0xa299, "VGT_GSVS_RING_OFFSET_2"},
357 {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
359 {0xa2e4, "VGT_GS_INSTANCE_CNT"},
360 {0xa297, "VGT_GS_PER_VS"},
361 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
362 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
364 {0xa2ad, "VGT_REUSE_OFF"},
365 {0xa1b8, "SPI_BARYC_CNTL"},
367 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
368 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
369 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
370 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
371 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
372 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
373 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
374 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
375 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
376 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
377 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
378 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
379 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
380 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
381 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
382 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
383 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
384 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
385 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
386 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
387 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
388 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
389 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
390 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
391 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
392 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
393 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
394 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
395 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
396 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
397 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
398 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
400 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
401 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
402 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
403 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
404 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
405 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
406 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
407 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
408 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
409 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
410 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
411 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
412 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
413 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
414 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
415 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
416 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
417 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
418 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
419 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
420 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
421 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
422 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
423 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
424 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
425 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
426 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
427 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
428 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
429 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
430 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
431 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
433 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
434 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
435 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
436 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
437 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
438 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
439 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
440 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
441 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
442 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
443 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
444 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
445 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
446 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
447 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
448 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
449 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
450 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
451 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
452 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
453 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
454 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
455 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
456 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
457 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
458 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
459 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
460 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
461 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
462 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
463 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
464 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
466 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
467 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
468 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
469 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
470 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
471 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
472 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
473 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
474 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
475 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
476 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
477 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
478 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
479 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
480 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
481 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
482 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
483 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
484 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
485 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
486 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
487 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
488 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
489 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
490 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
491 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
492 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
493 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
494 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
495 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
496 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
497 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
499 {0x2e40, "COMPUTE_USER_DATA_0"},
500 {0x2e41, "COMPUTE_USER_DATA_1"},
501 {0x2e42, "COMPUTE_USER_DATA_2"},
502 {0x2e43, "COMPUTE_USER_DATA_3"},
503 {0x2e44, "COMPUTE_USER_DATA_4"},
504 {0x2e45, "COMPUTE_USER_DATA_5"},
505 {0x2e46, "COMPUTE_USER_DATA_6"},
506 {0x2e47, "COMPUTE_USER_DATA_7"},
507 {0x2e48, "COMPUTE_USER_DATA_8"},
508 {0x2e49, "COMPUTE_USER_DATA_9"},
509 {0x2e4a, "COMPUTE_USER_DATA_10"},
510 {0x2e4b, "COMPUTE_USER_DATA_11"},
511 {0x2e4c, "COMPUTE_USER_DATA_12"},
512 {0x2e4d, "COMPUTE_USER_DATA_13"},
513 {0x2e4e, "COMPUTE_USER_DATA_14"},
514 {0x2e4f, "COMPUTE_USER_DATA_15"},
516 {0x2e07, "COMPUTE_NUM_THREAD_X"},
517 {0x2e08, "COMPUTE_NUM_THREAD_Y"},
518 {0x2e09, "COMPUTE_NUM_THREAD_Z"},
519 {0xa2db, "VGT_TF_PARAM"},
520 {0xa2d6, "VGT_LS_HS_CONFIG"},
521 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
522 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
523 {0xa2f8, "PA_SC_AA_CONFIG"},
524 {0xa310, "PA_SC_SHADER_CONTROL"},
525 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
527 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
528 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
529 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
530 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
531 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
532 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
533 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
534 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
535 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
536 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
537 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
538 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
539 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
540 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
541 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
542 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
543 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
544 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
545 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
546 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
547 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
548 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
549 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
550 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
551 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
552 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
553 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
554 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
555 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
556 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
557 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
558 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
560 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
561 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
562 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
563 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
564 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
565 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
566 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
567 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
568 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
569 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
570 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
571 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
572 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
573 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
574 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
575 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
577 {0xa2aa, "IA_MULTI_VGT_PARAM"},
578 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
579 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
580 {0xa2e5, "VGT_STRMOUT_CONFIG"},
581 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
582 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
583 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
584 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
585 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
588 auto Entry = RegInfoTable;
589 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
594 // Convert the accumulated PAL metadata into an asm directive.
595 void AMDGPUPALMetadata::toString(std::string &String) {
599 raw_string_ostream Stream(String);
601 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
603 // Old linear reg=val format.
604 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
605 auto Regs = getRegisters();
606 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
607 if (I != Regs.begin())
609 unsigned Reg = I->first.getUInt();
610 unsigned Val = I->second.getUInt();
611 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
617 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
618 // but first change the registers map to use names.
619 MsgPackDoc.setHexMode();
620 auto &RegsObj = refRegisters();
621 auto OrigRegs = RegsObj.getMap();
622 RegsObj = MsgPackDoc.getMapNode();
623 for (auto I : OrigRegs) {
625 if (const char *RegName = getRegisterName(Key.getUInt())) {
626 std::string KeyName = Key.toString();
630 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
632 RegsObj.getMap()[Key] = I.second;
636 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
637 MsgPackDoc.toYAML(Stream);
638 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
640 // Restore original registers map.
644 // Convert the accumulated PAL metadata into a binary blob for writing as
645 // a .note record of the specified AMD type. Returns an empty blob if
646 // there is no PAL metadata,
647 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
648 if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
654 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
656 auto Registers = getRegisters();
657 if (Registers.getMap().empty())
659 raw_string_ostream OS(Blob);
660 support::endian::Writer EW(OS, support::endianness::little);
661 for (auto I : Registers.getMap()) {
662 EW.write(uint32_t(I.first.getUInt()));
663 EW.write(uint32_t(I.second.getUInt()));
667 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
669 MsgPackDoc.writeToBlob(Blob);
672 // Set PAL metadata from YAML text. Returns false if failed.
673 bool AMDGPUPALMetadata::setFromString(StringRef S) {
674 BlobType = ELF::NT_AMDGPU_METADATA;
675 if (!MsgPackDoc.fromYAML(S))
678 // In the registers map, some keys may be of the form "0xa191
679 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
680 // string. We need to turn it into a number.
681 auto &RegsObj = refRegisters();
682 auto OrigRegs = RegsObj;
683 RegsObj = MsgPackDoc.getMapNode();
684 Registers = RegsObj.getMap();
686 for (auto I : OrigRegs.getMap()) {
688 if (Key.getKind() == msgpack::Type::String) {
689 StringRef S = Key.getString();
691 if (S.consumeInteger(0, Val)) {
693 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
696 Key = MsgPackDoc.getNode(uint64_t(Val));
698 Registers.getMap()[Key] = I.second;
703 // Reference (create if necessary) the node for the registers map.
704 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
707 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
708 .getArray(/*Convert=*/true)[0]
709 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
710 N.getMap(/*Convert=*/true);
714 // Get (create if necessary) the registers map.
715 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
716 if (Registers.isEmpty())
717 Registers = refRegisters();
718 return Registers.getMap();
721 // Return the PAL metadata hardware shader stage name.
722 static const char *getStageName(CallingConv::ID CC) {
724 case CallingConv::AMDGPU_PS:
726 case CallingConv::AMDGPU_VS:
728 case CallingConv::AMDGPU_GS:
730 case CallingConv::AMDGPU_ES:
732 case CallingConv::AMDGPU_HS:
734 case CallingConv::AMDGPU_LS:
741 // Get (create if necessary) the .hardware_stages entry for the given calling
743 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
744 if (HwStages.isEmpty())
745 HwStages = MsgPackDoc.getRoot()
746 .getMap(/*Convert=*/true)["amdpal.pipelines"]
747 .getArray(/*Convert=*/true)[0]
748 .getMap(/*Convert=*/true)[".hardware_stages"]
749 .getMap(/*Convert=*/true);
750 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
753 // Get .note record vendor name of metadata blob to be emitted.
754 const char *AMDGPUPALMetadata::getVendor() const {
755 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
758 // Get .note record type of metadata blob to be emitted:
759 // ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
760 // ELF::NT_AMDGPU_METADATA (MsgPack format), or
761 // 0 (no PAL metadata).
762 unsigned AMDGPUPALMetadata::getType() const {
766 // Return whether the blob type is legacy PAL metadata.
767 bool AMDGPUPALMetadata::isLegacy() const {
768 return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA;
771 // Set legacy PAL metadata format.
772 void AMDGPUPALMetadata::setLegacy() {
773 BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;