contrib/llvm-project/llvm/lib/Target/AMDGPU/VOPCInstructions.td

   1 //===-- VOPCInstructions.td - Vector Instruction Definitions --------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // Encodings
  11 //===----------------------------------------------------------------------===//
  12
  13 class VOPCe <bits<8> op> : Enc32 {
  14   bits<9> src0;
  15   bits<8> src1;
  16
  17   let Inst{8-0} = src0;
  18   let Inst{16-9} = src1;
  19   let Inst{24-17} = op;
  20   let Inst{31-25} = 0x3e;
  21 }
  22
  23 class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
  24   bits<8> src1;
  25
  26   let Inst{8-0}   = 0xf9; // sdwa
  27   let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
  28   let Inst{24-17} = op;
  29   let Inst{31-25} = 0x3e; // encoding
  30 }
  31
  32 class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
  33   bits<9> src1;
  34
  35   let Inst{8-0}   = 0xf9; // sdwa
  36   let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
  37   let Inst{24-17} = op;
  38   let Inst{31-25} = 0x3e; // encoding
  39   let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
  40 }
  41
  42
  43 //===----------------------------------------------------------------------===//
  44 // VOPC classes
  45 //===----------------------------------------------------------------------===//
  46
  47 // VOPC instructions are a special case because for the 32-bit
  48 // encoding, we want to display the implicit vcc write as if it were
  49 // an explicit $dst.
  50 class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> :
  51   VOPProfile <[i1, vt0, vt1, untyped]> {
  52   // We want to exclude instructions with 64bit operands
  53   let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
  54   let Asm32 = "$src0, $src1";
  55
  56   let AsmDPP = !if (HasModifiers,
  57                     "$src0_modifiers, $src1_modifiers "
  58                     "$dpp_ctrl$row_mask$bank_mask$bound_ctrl",
  59                     "$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl");
  60   let AsmDPP8 = "$src0, $src1 $dpp8$fi";
  61   let AsmDPP16 = AsmDPP#"$fi";
  62   // VOPC DPP Instructions do not need an old operand
  63   let TieRegDPP = "";
  64   let InsDPP = getInsDPP<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
  65                          NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
  66                          Src2ModDPP, 0/*HasOld*/>.ret;
  67   let InsDPP16 = getInsDPP16<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
  68                              NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
  69                              Src2ModDPP, 0/*HasOld*/>.ret;
  70   let InsDPP8 = getInsDPP8<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
  71                            NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
  72                            Src2ModDPP, 0/*HasOld*/>.ret;
  73
  74   // The destination for 32-bit encoding is implicit.
  75   let HasDst32 = 0;
  76   // VOPC disallows dst_sel and dst_unused as they have no effect on destination
  77   let EmitDstSel = 0;
  78   let Outs64 = (outs VOPDstS64orS32:$sdst);
  79   let OutsVOP3DPP = Outs64;
  80   let OutsVOP3DPP8 = Outs64;
  81   let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret;
  82   let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret;
  83   let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret;
  84   list<SchedReadWrite> Schedule = sched;
  85 }
  86
  87 multiclass VOPC_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> {
  88   def NAME : VOPC_Profile<sched, vt0, vt1>;
  89   def _t16 : VOPC_Profile<sched, vt0, vt1> {
  90     let IsTrue16 = 1;
  91     let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
  92     let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
  93     let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
  94     let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
  95     let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
  96     let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
  97     let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
  98   }
  99 }
 100
 101 class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
 102                           ValueType vt1 = vt0> :
 103   VOPC_Profile<sched, vt0, vt1> {
 104   let Outs64 = (outs );
 105   let OutsVOP3DPP = Outs64;
 106   let OutsVOP3DPP8 = Outs64;
 107   let OutsSDWA = (outs );
 108   let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
 109                      Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
 110                      src0_sel:$src0_sel, src1_sel:$src1_sel);
 111   let AsmVOP3Base = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
 112                                            "$src0, $src1");
 113   let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
 114   let EmitDst = 0;
 115 }
 116
 117 multiclass VOPC_NoSdst_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> {
 118   def NAME : VOPC_NoSdst_Profile<sched, vt0, vt1>;
 119   def _t16 : VOPC_NoSdst_Profile<sched, vt0, vt1> {
 120     let IsTrue16 = 1;
 121     let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
 122     let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
 123     let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
 124     let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
 125     let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
 126     let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
 127     let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
 128   }
 129 }
 130
 131 class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
 132                    bit DefVcc = 1> :
 133   InstSI<(outs), P.Ins32, "", pattern>,
 134   VOP <opName>,
 135   SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
 136
 137   let isPseudo = 1;
 138   let isCodeGenOnly = 1;
 139   let UseNamedOperandTable = 1;
 140
 141   string Mnemonic = opName;
 142   string AsmOperands = P.Asm32;
 143
 144   let Size = 4;
 145   let mayLoad = 0;
 146   let mayStore = 0;
 147   let hasSideEffects = 0;
 148
 149   let ReadsModeReg = isFloatType<P.Src0VT>.ret;
 150
 151   let VALU = 1;
 152   let VOPC = 1;
 153   let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
 154   let Defs = !if(DefVcc, [VCC], []);
 155
 156   VOPProfile Pfl = P;
 157 }
 158
 159 class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.PseudoInstr> :
 160   InstSI <ps.OutOperandList, ps.InOperandList, asm_name # " " # ps.AsmOperands, []>,
 161   SIMCInstr <ps.PseudoInstr, EncodingFamily> {
 162
 163   let VALU = 1;
 164   let VOPC = 1;
 165   let isPseudo = 0;
 166   let isCodeGenOnly = 0;
 167
 168   let Constraints     = ps.Constraints;
 169   let DisableEncoding = ps.DisableEncoding;
 170
 171   // copy relevant pseudo op flags
 172   let SubtargetPredicate = ps.SubtargetPredicate;
 173   let AsmMatchConverter  = ps.AsmMatchConverter;
 174   let Constraints        = ps.Constraints;
 175   let DisableEncoding    = ps.DisableEncoding;
 176   let TSFlags            = ps.TSFlags;
 177   let UseNamedOperandTable = ps.UseNamedOperandTable;
 178   let Uses                 = ps.Uses;
 179   let Defs                 = ps.Defs;
 180   let SchedRW              = ps.SchedRW;
 181   let mayLoad              = ps.mayLoad;
 182   let mayStore             = ps.mayStore;
 183 }
 184
 185 class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
 186   VOP_SDWA_Pseudo <OpName, P, pattern> {
 187   let AsmMatchConverter = "cvtSdwaVOPC";
 188 }
 189
 190 // This class is used only with VOPC instructions. Use $sdst for out operand
 191 class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst,
 192                      string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName,
 193                      VOPProfile p = ps.Pfl> :
 194   InstAlias <real_name#" "#Asm32, (inst)>, PredicateControl {
 195
 196   field bit isCompare;
 197   field bit isCommutable;
 198
 199   let ResultInst =
 200     !if (p.HasDst32,
 201       !if (!eq(p.NumSrcArgs, 0),
 202         // 1 dst, 0 src
 203         (inst p.DstRC:$sdst),
 204       !if (!eq(p.NumSrcArgs, 1),
 205         // 1 dst, 1 src
 206         (inst p.DstRC:$sdst, p.Src0RC32:$src0),
 207       !if (!eq(p.NumSrcArgs, 2),
 208         // 1 dst, 2 src
 209         (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
 210       // else - unreachable
 211         (inst)))),
 212     // else
 213       !if (!eq(p.NumSrcArgs, 2),
 214         // 0 dst, 2 src
 215         (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
 216       !if (!eq(p.NumSrcArgs, 1),
 217         // 0 dst, 1 src
 218         (inst p.Src0RC32:$src1),
 219       // else
 220         // 0 dst, 0 src
 221         (inst))));
 222
 223   let AsmVariantName = AMDGPUAsmVariants.Default;
 224   let SubtargetPredicate = AssemblerPredicate;
 225 }
 226
 227 multiclass VOPCInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> {
 228   def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
 229                        !cast<Instruction>(real_name#"_e32_"#Arch),
 230                        !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
 231                        mnemonic_from>;
 232   let WaveSizePredicate = isWave32 in {
 233     def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
 234                          !cast<Instruction>(real_name#"_e32_"#Arch),
 235                          "vcc_lo, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
 236                          mnemonic_from>;
 237   }
 238   let WaveSizePredicate = isWave64 in {
 239     def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
 240                          !cast<Instruction>(real_name#"_e32_"#Arch),
 241                          "vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
 242                          mnemonic_from>;
 243   }
 244 }
 245
 246 multiclass VOPCXInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> {
 247   def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
 248                        !cast<Instruction>(real_name#"_e32_"#Arch),
 249                        !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
 250                        mnemonic_from>;
 251 }
 252
 253 class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies {
 254   list<dag> ret = !if(P.HasModifiers,
 255       [(set i1:$sdst,
 256         (setcc (P.Src0VT
 257                   !if(P.HasOMod,
 258                     (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
 259                     (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
 260                (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
 261                cond))],
 262       [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
 263 }
 264
 265 class VCMPXNoSDstTable <bit has_sdst, string Name> {
 266   bit HasSDst = has_sdst;
 267   string NoSDstOp = Name;
 268 }
 269
 270 class VCMPVCMPXTable <string Name> {
 271   bit IsVCMPX = 0;
 272   string VCMPOp = Name;
 273 }
 274
 275 multiclass VOPC_Pseudos <string opName,
 276                          VOPC_Profile P,
 277                          SDPatternOperator cond = COND_NULL,
 278                          string revOp = opName,
 279                          bit DefExec = 0> {
 280
 281   def _e32 : VOPC_Pseudo <opName, P>,
 282              Commutable_REV<revOp#"_e32", !eq(revOp, opName)>,
 283              VCMPXNoSDstTable<1, opName#"_e32">,
 284              VCMPVCMPXTable<opName#"_e32"> {
 285     let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
 286     let SchedRW = P.Schedule;
 287     let isConvergent = DefExec;
 288     let isCompare = 1;
 289     let isCommutable = 1;
 290   }
 291
 292   def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>,
 293     Commutable_REV<revOp#"_e64", !eq(revOp, opName)>,
 294     VCMPXNoSDstTable<1, opName#"_e64">,
 295     VCMPVCMPXTable<opName#"_e64"> {
 296     let Defs = !if(DefExec, [EXEC], []);
 297     let SchedRW = P.Schedule;
 298     let isCompare = 1;
 299     let isCommutable = 1;
 300   }
 301
 302   foreach _ = BoolToList<P.HasExtSDWA>.ret in
 303   def _sdwa : VOPC_SDWA_Pseudo <opName, P> {
 304     let Defs = !if(DefExec, [EXEC], []);
 305     let SchedRW = P.Schedule;
 306     let isConvergent = DefExec;
 307     let isCompare = 1;
 308   }
 309
 310   let SubtargetPredicate = isGFX11Plus in {
 311   if P.HasExtDPP then
 312       def _e32_dpp : VOP_DPP_Pseudo<opName, P> {
 313         let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
 314         let SchedRW = P.Schedule;
 315         let isConvergent = DefExec;
 316         let isCompare = 1;
 317         let VOPC = 1;
 318         let Constraints = "";
 319       }
 320   if P.HasExtVOP3DPP then
 321       def _e64_dpp : VOP3_DPP_Pseudo<opName, P> {
 322         let Defs = !if(DefExec, [EXEC], []);
 323         let SchedRW = P.Schedule;
 324         let isCompare = 1;
 325         let Constraints = "";
 326     }
 327   } // end SubtargetPredicate = isGFX11Plus
 328
 329 }
 330
 331 let SubtargetPredicate = HasSdstCMPX in {
 332 multiclass VOPCX_Pseudos <string opName,
 333                           VOPC_Profile P, VOPC_Profile P_NoSDst,
 334                           SDPatternOperator cond = COND_NULL,
 335                           string revOp = opName> :
 336            VOPC_Pseudos <opName, P, cond, revOp, 1> {
 337
 338   def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>,
 339              Commutable_REV<revOp#"_nosdst_e32", !eq(revOp, opName)>,
 340              VCMPXNoSDstTable<0, opName#"_e32">,
 341              VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e32")> {
 342     let Defs = [EXEC];
 343     let SchedRW = P_NoSDst.Schedule;
 344     let isConvergent = 1;
 345     let isCompare = 1;
 346     let isCommutable = 1;
 347     let SubtargetPredicate = HasNoSdstCMPX;
 348     let IsVCMPX = 1;
 349   }
 350
 351   def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
 352     Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>,
 353     VCMPXNoSDstTable<0, opName#"_e64">,
 354     VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e64")> {
 355     let Defs = [EXEC];
 356     let SchedRW = P_NoSDst.Schedule;
 357     let isCompare = 1;
 358     let isCommutable = 1;
 359     let SubtargetPredicate = HasNoSdstCMPX;
 360     let IsVCMPX = 1;
 361   }
 362
 363   foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
 364   def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> {
 365     let Defs = [EXEC];
 366     let SchedRW = P_NoSDst.Schedule;
 367     let isConvergent = 1;
 368     let isCompare = 1;
 369     let SubtargetPredicate = HasNoSdstCMPX;
 370   }
 371
 372   let SubtargetPredicate = isGFX11Plus in {
 373   if P.HasExtDPP then
 374       def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
 375         let Defs = [EXEC];
 376         let SchedRW = P_NoSDst.Schedule;
 377         let isConvergent = 1;
 378         let isCompare = 1;
 379         let VOPC = 1;
 380         let Constraints = "";
 381       }
 382   if P.HasExtVOP3DPP then
 383       def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
 384         let Defs = [EXEC];
 385         let SchedRW = P_NoSDst.Schedule;
 386         let isCompare = 1;
 387         let Constraints = "";
 388     }
 389   } // end SubtargetPredicate = isGFX11Plus
 390 }
 391 } // End SubtargetPredicate = HasSdstCMPX
 392
 393 defm VOPC_I1_F16_F16 : VOPC_Profile_t16<[Write32Bit], f16>;
 394 def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>;
 395 def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>;
 396 defm VOPC_I1_I16_I16 : VOPC_Profile_t16<[Write32Bit], i16>;
 397 def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
 398 def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;
 399
 400 defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>;
 401 def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>;
 402 def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>;
 403 defm VOPC_I16_I16 : VOPC_NoSdst_Profile_t16<[Write32Bit], i16>;
 404 def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>;
 405 def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>;
 406
 407 multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL,
 408                      string revOp = opName> {
 409   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
 410     defm NAME : VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>;
 411   }
 412   let OtherPredicates = [HasTrue16BitInsts] in {
 413     defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, cond, revOp#"_t16", 0>;
 414   }
 415 }
 416
 417 multiclass VOPC_F32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
 418   VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>;
 419
 420 multiclass VOPC_F64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
 421   VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>;
 422
 423 multiclass VOPC_I16 <string opName, SDPatternOperator cond = COND_NULL,
 424                      string revOp = opName> {
 425   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
 426     defm NAME : VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>;
 427   }
 428   let OtherPredicates = [HasTrue16BitInsts] in {
 429     defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, cond, revOp#"_t16", 0>;
 430   }
 431 }
 432
 433 multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
 434   VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>;
 435
 436 multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
 437   VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;
 438
 439 multiclass VOPCX_F16<string opName, string revOp = opName> {
 440   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
 441     defm NAME : VOPCX_Pseudos <opName, VOPC_I1_F16_F16, VOPC_F16_F16, COND_NULL, revOp>;
 442   }
 443   let OtherPredicates = [HasTrue16BitInsts] in {
 444     defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, VOPC_F16_F16_t16, COND_NULL, revOp#"_t16">;
 445   }
 446 }
 447
 448 multiclass VOPCX_F32 <string opName, string revOp = opName> :
 449   VOPCX_Pseudos <opName, VOPC_I1_F32_F32, VOPC_F32_F32, COND_NULL, revOp>;
 450
 451 multiclass VOPCX_F64 <string opName, string revOp = opName> :
 452   VOPCX_Pseudos <opName, VOPC_I1_F64_F64, VOPC_F64_F64, COND_NULL, revOp>;
 453
 454 multiclass VOPCX_I16<string opName, string revOp = opName> {
 455   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
 456     defm NAME : VOPCX_Pseudos <opName, VOPC_I1_I16_I16, VOPC_I16_I16, COND_NULL, revOp>;
 457   }
 458   let OtherPredicates = [HasTrue16BitInsts] in {
 459     defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, VOPC_I16_I16_t16, COND_NULL, revOp#"_t16">;
 460   }
 461 }
 462
 463 multiclass VOPCX_I32 <string opName, string revOp = opName> :
 464   VOPCX_Pseudos <opName, VOPC_I1_I32_I32, VOPC_I32_I32, COND_NULL, revOp>;
 465
 466 multiclass VOPCX_I64 <string opName, string revOp = opName> :
 467   VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>;
 468
 469
 470 //===----------------------------------------------------------------------===//
 471 // Compare instructions
 472 //===----------------------------------------------------------------------===//
 473
 474 defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">;
 475 defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
 476 defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>;
 477 defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
 478 defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>;
 479 defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>;
 480 defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>;
 481 defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>;
 482 defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>;
 483 defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32",  COND_ULT, "v_cmp_nle_f32">;
 484 defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>;
 485 defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
 486 defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>;
 487 defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>;
 488 defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>;
 489 defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">;
 490
 491 defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">;
 492 defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">;
 493 defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">;
 494 defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">;
 495 defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">;
 496 defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">;
 497 defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">;
 498 defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">;
 499 defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">;
 500 defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">;
 501 defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">;
 502 defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">;
 503 defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">;
 504 defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">;
 505 defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">;
 506 defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">;
 507
 508 defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">;
 509 defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
 510 defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>;
 511 defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
 512 defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>;
 513 defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>;
 514 defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>;
 515 defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>;
 516 defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>;
 517 defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
 518 defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>;
 519 defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
 520 defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>;
 521 defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>;
 522 defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>;
 523 defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">;
 524
 525 defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">;
 526 defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">;
 527 defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">;
 528 defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">;
 529 defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">;
 530 defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">;
 531 defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">;
 532 defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">;
 533 defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">;
 534 defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">;
 535 defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">;
 536 defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
 537 defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">;
 538 defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">;
 539 defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">;
 540 defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">;
 541
 542 let SubtargetPredicate = isGFX6GFX7 in {
 543
 544 defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">;
 545 defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
 546 defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">;
 547 defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
 548 defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">;
 549 defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">;
 550 defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">;
 551 defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">;
 552 defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">;
 553 defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
 554 defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">;
 555 defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
 556 defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">;
 557 defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">;
 558 defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">;
 559 defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">;
 560
 561 defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">;
 562 defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
 563 defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">;
 564 defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
 565 defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">;
 566 defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">;
 567 defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">;
 568 defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">;
 569 defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">;
 570 defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
 571 defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">;
 572 defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
 573 defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">;
 574 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">;
 575 defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">;
 576 defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">;
 577
 578 defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">;
 579 defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
 580 defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">;
 581 defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
 582 defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">;
 583 defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">;
 584 defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">;
 585 defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">;
 586 defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">;
 587 defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
 588 defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">;
 589 defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
 590 defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">;
 591 defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">;
 592 defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">;
 593 defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">;
 594
 595 defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">;
 596 defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
 597 defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">;
 598 defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
 599 defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">;
 600 defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">;
 601 defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">;
 602 defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">;
 603 defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">;
 604 defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
 605 defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">;
 606 defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
 607 defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">;
 608 defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
 609 defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
 610 defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;
 611
 612 } // End SubtargetPredicate = isGFX6GFX7
 613
 614 let SubtargetPredicate = Has16BitInsts in {
 615
 616 defm V_CMP_F_F16    : VOPC_F16 <"v_cmp_f_f16">;
 617 defm V_CMP_LT_F16   : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">;
 618 defm V_CMP_EQ_F16   : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>;
 619 defm V_CMP_LE_F16   : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">;
 620 defm V_CMP_GT_F16   : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>;
 621 defm V_CMP_LG_F16   : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>;
 622 defm V_CMP_GE_F16   : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>;
 623 defm V_CMP_O_F16    : VOPC_F16 <"v_cmp_o_f16", COND_O>;
 624 defm V_CMP_U_F16    : VOPC_F16 <"v_cmp_u_f16", COND_UO>;
 625 defm V_CMP_NGE_F16  : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">;
 626 defm V_CMP_NLG_F16  : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>;
 627 defm V_CMP_NGT_F16  : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">;
 628 defm V_CMP_NLE_F16  : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>;
 629 defm V_CMP_NEQ_F16  : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>;
 630 defm V_CMP_NLT_F16  : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>;
 631 defm V_CMP_TRU_F16  : VOPC_F16 <"v_cmp_tru_f16">;
 632
 633 defm V_CMPX_F_F16   : VOPCX_F16 <"v_cmpx_f_f16">;
 634 defm V_CMPX_LT_F16  : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">;
 635 defm V_CMPX_EQ_F16  : VOPCX_F16 <"v_cmpx_eq_f16">;
 636 defm V_CMPX_LE_F16  : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">;
 637 defm V_CMPX_GT_F16  : VOPCX_F16 <"v_cmpx_gt_f16">;
 638 defm V_CMPX_LG_F16  : VOPCX_F16 <"v_cmpx_lg_f16">;
 639 defm V_CMPX_GE_F16  : VOPCX_F16 <"v_cmpx_ge_f16">;
 640 defm V_CMPX_O_F16   : VOPCX_F16 <"v_cmpx_o_f16">;
 641 defm V_CMPX_U_F16   : VOPCX_F16 <"v_cmpx_u_f16">;
 642 defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">;
 643 defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">;
 644 defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">;
 645 defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">;
 646 defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">;
 647 defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">;
 648 defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">;
 649
 650 defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">;
 651 defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">;
 652 defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">;
 653 defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">;
 654 defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>;
 655 defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">;
 656 defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>;
 657 defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">;
 658
 659 defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">;
 660 defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">;
 661 defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>;
 662 defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">;
 663 defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>;
 664 defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>;
 665 defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>;
 666 defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">;
 667
 668 defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">;
 669 defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">;
 670 defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">;
 671 defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">;
 672 defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">;
 673 defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">;
 674 defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">;
 675 defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">;
 676
 677 defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">;
 678 defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">;
 679 defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">;
 680 defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">;
 681 defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">;
 682 defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">;
 683 defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">;
 684 defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">;
 685
 686 } // End SubtargetPredicate = Has16BitInsts
 687
 688 defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">;
 689 defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
 690 defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">;
 691 defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
 692 defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>;
 693 defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">;
 694 defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>;
 695 defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">;
 696
 697 defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">;
 698 defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">;
 699 defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">;
 700 defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">;
 701 defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">;
 702 defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">;
 703 defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">;
 704 defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">;
 705
 706 defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">;
 707 defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
 708 defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">;
 709 defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
 710 defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>;
 711 defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">;
 712 defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>;
 713 defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">;
 714
 715 defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">;
 716 defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
 717 defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">;
 718 defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
 719 defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">;
 720 defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">;
 721 defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">;
 722 defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">;
 723
 724 defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">;
 725 defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
 726 defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>;
 727 defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
 728 defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>;
 729 defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>;
 730 defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>;
 731 defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">;
 732
 733 defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">;
 734 defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">;
 735 defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">;
 736 defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">;
 737 defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">;
 738 defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">;
 739 defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">;
 740 defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">;
 741
 742 defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">;
 743 defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
 744 defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>;
 745 defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
 746 defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>;
 747 defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>;
 748 defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>;
 749 defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">;
 750
 751 defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">;
 752 defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">;
 753 defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">;
 754 defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">;
 755 defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">;
 756 defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">;
 757 defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">;
 758 defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;
 759
 760 //===----------------------------------------------------------------------===//
 761 // Class instructions
 762 //===----------------------------------------------------------------------===//
 763
 764 class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> :
 765   VOPC_Profile<sched, src0VT, src1VT> {
 766   let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
 767   let AsmDPP16 = AsmDPP#"$fi";
 768     let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
 769   let InsDPP16 = !con(InsDPP, (ins FI:$fi));
 770   // DPP8 forbids modifiers and can inherit from VOPC_Profile
 771
 772   let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
 773   dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
 774   let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
 775                                                        (ins)));
 776   let AsmVOP3Base = "$sdst, $src0_modifiers, $src1";
 777
 778   let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
 779                      Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
 780                      clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
 781
 782   let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
 783   let HasSrc1Mods = 0;
 784   let HasClamp = 0;
 785   let HasOMod = 0;
 786 }
 787
 788 multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> {
 789   def NAME : VOPC_Class_Profile<sched, f16>;
 790   def _t16 : VOPC_Class_Profile<sched, f16, i16> {
 791     let IsTrue16 = 1;
 792     let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
 793     let Src1RC64 = VSrc_b32;
 794     let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
 795     let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
 796     let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
 797     let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
 798     let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
 799     let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
 800   }
 801 }
 802
 803 class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> :
 804   VOPC_Class_Profile<sched, src0VT, src1VT> {
 805   let Outs64 = (outs );
 806   let OutsSDWA = (outs );
 807   let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
 808                      Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
 809                      src0_sel:$src0_sel, src1_sel:$src1_sel);
 810   let AsmVOP3Base = "$src0_modifiers, $src1";
 811   let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
 812   let EmitDst = 0;
 813 }
 814
 815 multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> {
 816   def NAME : VOPC_Class_NoSdst_Profile<sched, f16>;
 817   def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> {
 818     let IsTrue16 = 1;
 819     let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
 820     let Src1RC64 = VSrc_b32;
 821     let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
 822     let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
 823     let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
 824     let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
 825     let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
 826     let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
 827   }
 828 }
 829
 830 class getVOPCClassPat64 <VOPProfile P> {
 831   list<dag> ret =
 832     [(set i1:$sdst,
 833       (AMDGPUfp_class
 834         (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers)),
 835         i32:$src1))];
 836 }
 837
 838
 839 // Special case for class instructions which only have modifiers on
 840 // the 1st source operand.
 841 multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
 842                                bit DefVcc = 1> {
 843   def _e32 : VOPC_Pseudo <opName, p>,
 844              VCMPXNoSDstTable<1, opName#"_e32"> {
 845     let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
 846                             !if(DefVcc, [VCC], []));
 847     let SchedRW = p.Schedule;
 848     let isConvergent = DefExec;
 849   }
 850
 851   def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>,
 852              VCMPXNoSDstTable<1, opName#"_e64"> {
 853     let Defs = !if(DefExec, [EXEC], []);
 854     let SchedRW = p.Schedule;
 855   }
 856
 857   foreach _ = BoolToList<p.HasExtSDWA>.ret in
 858   def _sdwa : VOPC_SDWA_Pseudo <opName, p> {
 859     let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
 860                             !if(DefVcc, [VCC], []));
 861     let SchedRW = p.Schedule;
 862     let isConvergent = DefExec;
 863   }
 864
 865   let SubtargetPredicate = isGFX11Plus in {
 866   if p.HasExtDPP then
 867       def _e32_dpp : VOP_DPP_Pseudo<opName, p> {
 868         let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
 869                                 !if(DefVcc, [VCC], []));
 870         let SchedRW = p.Schedule;
 871         let isConvergent = DefExec;
 872         let VOPC = 1;
 873         let Constraints = "";
 874       }
 875   if p.HasExtVOP3DPP then
 876       def _e64_dpp : VOP3_DPP_Pseudo<opName, p> {
 877         let Defs = !if(DefExec, [EXEC], []);
 878         let SchedRW = p.Schedule;
 879         let Constraints = "";
 880     }
 881   } // end SubtargetPredicate = isGFX11Plus
 882 }
 883
 884 let SubtargetPredicate = HasSdstCMPX in {
 885 multiclass VOPCX_Class_Pseudos <string opName,
 886                                 VOPC_Profile P,
 887                                 VOPC_Profile P_NoSDst> :
 888            VOPC_Class_Pseudos <opName, P, 1, 1> {
 889
 890   def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>,
 891                     VCMPXNoSDstTable<0, opName#"_e32"> {
 892     let Defs = [EXEC];
 893     let SchedRW = P_NoSDst.Schedule;
 894     let isConvergent = 1;
 895     let SubtargetPredicate = HasNoSdstCMPX;
 896   }
 897
 898   def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
 899                     VCMPXNoSDstTable<0, opName#"_e64"> {
 900     let Defs = [EXEC];
 901     let SchedRW = P_NoSDst.Schedule;
 902     let SubtargetPredicate = HasNoSdstCMPX;
 903   }
 904
 905   foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
 906   def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> {
 907     let Defs = [EXEC];
 908     let SchedRW = P_NoSDst.Schedule;
 909     let isConvergent = 1;
 910     let SubtargetPredicate = HasNoSdstCMPX;
 911   }
 912
 913   let SubtargetPredicate = isGFX11Plus in {
 914   if P.HasExtDPP then
 915       def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
 916         let Defs = [EXEC];
 917         let SchedRW = P_NoSDst.Schedule;
 918         let isConvergent = 1;
 919         let VOPC = 1;
 920         let Constraints = "";
 921       }
 922   if P.HasExtVOP3DPP then
 923       def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
 924         let Defs = [EXEC];
 925         let SchedRW = P_NoSDst.Schedule;
 926         let Constraints = "";
 927     }
 928   } // end SubtargetPredicate = isGFX11Plus
 929 }
 930 } // End SubtargetPredicate = HasSdstCMPX
 931
 932 defm VOPC_I1_F16_I16 : VOPC_Class_Profile_t16<[Write32Bit]>;
 933 def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>;
 934 def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>;
 935
 936 defm VOPC_F16_I16 : VOPC_Class_NoSdst_Profile_t16<[Write32Bit]>;
 937 def VOPC_F32_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f32>;
 938 def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>;
 939
 940 multiclass VOPC_CLASS_F16 <string opName> {
 941   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
 942     defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F16_I16, 0>;
 943   }
 944   let OtherPredicates = [HasTrue16BitInsts] in {
 945     defm _t16 : VOPC_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, 0>;
 946   }
 947 }
 948
 949 multiclass VOPCX_CLASS_F16 <string opName> {
 950   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
 951     defm NAME : VOPCX_Class_Pseudos <opName, VOPC_I1_F16_I16, VOPC_F16_I16>;
 952   }
 953   let OtherPredicates = [HasTrue16BitInsts] in {
 954     defm _t16 : VOPCX_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, VOPC_F16_I16_t16>;
 955   }
 956 }
 957
 958 multiclass VOPC_CLASS_F32 <string opName> :
 959   VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;
 960
 961 multiclass VOPCX_CLASS_F32 <string opName> :
 962   VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>;
 963
 964 multiclass VOPC_CLASS_F64 <string opName> :
 965   VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
 966
 967 multiclass VOPCX_CLASS_F64 <string opName> :
 968   VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>;
 969
 970 // cmp_class ignores the FP mode and faithfully reports the unmodified
 971 // source value.
 972 let ReadsModeReg = 0, mayRaiseFPException = 0 in {
 973 defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
 974 defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
 975 defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
 976 defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
 977
 978 defm V_CMP_CLASS_F16  : VOPC_CLASS_F16 <"v_cmp_class_f16">;
 979 defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
 980 } // End ReadsModeReg = 0, mayRaiseFPException = 0
 981
 982 //===----------------------------------------------------------------------===//
 983 // V_ICMPIntrinsic Pattern.
 984 //===----------------------------------------------------------------------===//
 985
 986 // We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()
 987 // complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.
 988 multiclass ICMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
 989   let WaveSizePredicate = isWave64 in
 990   def : GCNPat <
 991     (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
 992     (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))
 993   >;
 994
 995   let WaveSizePredicate = isWave32 in
 996   def : GCNPat <
 997     (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
 998     (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32))
 999   >;
1000 }
1001
1002 defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>;
1003 defm : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>;
1004 defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
1005 defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
1006 defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
1007 defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
1008 defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
1009 defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
1010 defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
1011 defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
1012
1013 defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>;
1014 defm : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>;
1015 defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
1016 defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
1017 defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
1018 defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
1019 defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
1020 defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
1021 defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
1022 defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
1023
1024 let OtherPredicates = [HasTrue16BitInsts] in {
1025 defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_t16_e64, i16>;
1026 defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_t16_e64, i16>;
1027 defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_t16_e64, i16>;
1028 defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_t16_e64, i16>;
1029 defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_t16_e64, i16>;
1030 defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_t16_e64, i16>;
1031 defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_t16_e64, i16>;
1032 defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_t16_e64, i16>;
1033 defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_t16_e64, i16>;
1034 defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_t16_e64, i16>;
1035 } // End OtherPredicates = [HasTrue16BitInsts]
1036
1037 let OtherPredicates = [NotHasTrue16BitInsts] in {
1038 defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>;
1039 defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>;
1040 defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>;
1041 defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_e64, i16>;
1042 defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_e64, i16>;
1043 defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_e64, i16>;
1044 defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_e64, i16>;
1045 defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>;
1046 defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>;
1047 defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;
1048 } // End OtherPredicates = [NotHasTrue16BitInsts]
1049
1050 multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
1051   let WaveSizePredicate = isWave64 in
1052   def : GCNPat <
1053     (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
1054                  (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
1055     (i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
1056                            DSTCLAMP.NONE), SReg_64))
1057   >;
1058
1059   let WaveSizePredicate = isWave32 in
1060   def : GCNPat <
1061     (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
1062                  (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
1063     (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
1064                            DSTCLAMP.NONE), SReg_32))
1065   >;
1066 }
1067
1068 defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
1069 defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
1070 defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
1071 defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
1072 defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
1073 defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
1074
1075 defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
1076 defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
1077 defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
1078 defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
1079 defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
1080 defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
1081
1082 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
1083 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
1084 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
1085 defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
1086 defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
1087 defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
1088
1089 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
1090 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
1091 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
1092 defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
1093 defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
1094 defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
1095
1096 let OtherPredicates = [HasTrue16BitInsts] in {
1097 defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_t16_e64, f16>;
1098 defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_t16_e64, f16>;
1099 defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_t16_e64, f16>;
1100 defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_t16_e64, f16>;
1101 defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_t16_e64, f16>;
1102 defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_t16_e64, f16>;
1103
1104 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_t16_e64, f16>;
1105 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_t16_e64, f16>;
1106 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_t16_e64, f16>;
1107 defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_t16_e64, f16>;
1108 defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_t16_e64, f16>;
1109 defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_t16_e64, f16>;
1110 } // End OtherPredicates = [HasTrue16BitInsts]
1111
1112 let OtherPredicates = [NotHasTrue16BitInsts] in {
1113 defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>;
1114 defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>;
1115 defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>;
1116 defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>;
1117 defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>;
1118 defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>;
1119
1120 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>;
1121 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>;
1122 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>;
1123 defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>;
1124 defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>;
1125 defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>;
1126 } // End OtherPredicates = [NotHasTrue16BitInsts]
1127
1128 //===----------------------------------------------------------------------===//
1129 // DPP Encodings
1130 //===----------------------------------------------------------------------===//
1131
1132 // VOPC32
1133
1134 class VOPC_DPPe_Common<bits<8> op> : Enc64 {
1135   bits<8> src1;
1136   let Inst{16-9} = src1;
1137   let Inst{24-17} = op;
1138   let Inst{31-25} = 0x3e;
1139 }
1140
1141 class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
1142     : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>,
1143       VOPC_DPPe_Common<op> {
1144   bits<2> src0_modifiers;
1145   bits<8> src0;
1146   bits<2> src1_modifiers;
1147   bits<9> dpp_ctrl;
1148   bits<1> bound_ctrl;
1149   bits<4> bank_mask;
1150   bits<4> row_mask;
1151   bit fi;
1152
1153   let Inst{8-0} = 0xfa;
1154
1155   let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
1156   let Inst{48-40} = dpp_ctrl;
1157   let Inst{50} = fi;
1158   let Inst{51} = bound_ctrl;
1159   let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
1160   let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
1161   let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
1162   let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
1163   let Inst{59-56} = bank_mask;
1164   let Inst{63-60} = row_mask;
1165
1166   let AsmMatchConverter = "cvtDPP";
1167   let VOPC = 1;
1168 }
1169
1170 class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
1171     : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>,
1172       VOPC_DPPe_Common<op> {
1173   bits<8> src0;
1174   bits<24> dpp8;
1175   bits<9> fi;
1176
1177   let Inst{8-0} = fi;
1178
1179   let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
1180   let Inst{63-40} = dpp8{23-0};
1181
1182   let AsmMatchConverter = "cvtDPP8";
1183   let VOPC = 1;
1184 }
1185
1186 class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
1187     : VOPC_DPP_Base<op, opName, ps.Pfl> {
1188   let AssemblerPredicate = HasDPP16;
1189   let SubtargetPredicate = HasDPP16;
1190   let hasSideEffects = ps.hasSideEffects;
1191   let Defs = ps.Defs;
1192   let SchedRW = ps.SchedRW;
1193   let Uses = ps.Uses;
1194   let OtherPredicates = ps.OtherPredicates;
1195   let Constraints = ps.Constraints;
1196 }
1197
1198 class VOPC_DPP16_SIMC<bits<8> op, VOP_DPP_Pseudo ps, int subtarget,
1199                       string opName = ps.OpName>
1200     : VOPC_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>;
1201
1202 class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName>
1203     : VOPC_DPP8_Base<op, opName, ps.Pfl> {
1204   // Note ps is the non-dpp pseudo
1205   let hasSideEffects = ps.hasSideEffects;
1206   let Defs = ps.Defs;
1207   let SchedRW = ps.SchedRW;
1208   let Uses = ps.Uses;
1209   let OtherPredicates = ps.OtherPredicates;
1210   let Constraints = "";
1211 }
1212
1213 // VOPC64
1214
1215 class VOPC64_DPP_Base<bits<10> op, string OpName, VOPProfile P>
1216     : VOP3_DPP_Base<OpName, P, 1>, VOP3_DPPe_Common<op, P> {
1217   Instruction Opcode = !cast<Instruction>(NAME);
1218
1219   bits<8> src0;
1220   bits<9> dpp_ctrl;
1221   bits<1> bound_ctrl;
1222   bits<4> bank_mask;
1223   bits<4> row_mask;
1224   bit     fi;
1225
1226   let Inst{40-32} = 0xfa;
1227   let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1228   let Inst{80-72} = dpp_ctrl;
1229   let Inst{82}    = fi;
1230   let Inst{83}    = bound_ctrl;
1231   // Inst{87-84} ignored by hw
1232   let Inst{91-88} = bank_mask;
1233   let Inst{95-92} = row_mask;
1234 }
1235
1236 class VOPC64_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
1237     : VOPC64_DPP_Base<op, opName, ps.Pfl> {
1238   let AssemblerPredicate = HasDPP16;
1239   let SubtargetPredicate = HasDPP16;
1240   let hasSideEffects = ps.hasSideEffects;
1241   let Defs = ps.Defs;
1242   let SchedRW = ps.SchedRW;
1243   let Uses = ps.Uses;
1244   let OtherPredicates = ps.OtherPredicates;
1245   let Constraints = ps.Constraints;
1246 }
1247
1248 class VOPC64_DPP16_Dst<bits<10> op, VOP_DPP_Pseudo ps,
1249                        string opName = ps.OpName>
1250     : VOPC64_DPP16<op, ps, opName> {
1251   bits<8> sdst;
1252   let Inst{7-0} = sdst;
1253 }
1254
1255 class VOPC64_DPP16_NoDst<bits<10> op, VOP_DPP_Pseudo ps,
1256                          string opName = ps.OpName>
1257     : VOPC64_DPP16<op, ps, opName> {
1258   let Inst{7-0} = ? ;
1259 }
1260
1261 class VOPC64_DPP8_Base<bits<10> op, string OpName, VOPProfile P>
1262     : VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P> {
1263   Instruction Opcode = !cast<Instruction>(NAME);
1264
1265   bits<8> src0;
1266   bits<24> dpp8;
1267   bits<9> fi;
1268
1269   let Inst{40-32} = fi;
1270   let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1271   let Inst{95-72} = dpp8{23-0};
1272 }
1273
1274 class VOPC64_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1275     : VOPC64_DPP8_Base<op, opName, ps.Pfl> {
1276   // Note ps is the non-dpp pseudo
1277   let hasSideEffects = ps.hasSideEffects;
1278   let Defs = ps.Defs;
1279   let SchedRW = ps.SchedRW;
1280   let Uses = ps.Uses;
1281   let OtherPredicates = ps.OtherPredicates;
1282 }
1283
1284 class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1285     : VOPC64_DPP8<op, ps, opName> {
1286   bits<8> sdst;
1287   let Inst{7-0} = sdst;
1288   let Constraints = "";
1289 }
1290
1291 class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1292     : VOPC64_DPP8<op, ps, opName> {
1293   let Inst{7-0} = ? ;
1294   let Constraints = "";
1295 }
1296
1297 //===----------------------------------------------------------------------===//
1298 // Target-specific instruction encodings.
1299 //===----------------------------------------------------------------------===//
1300
1301 //===----------------------------------------------------------------------===//
1302 // GFX11.
1303 //===----------------------------------------------------------------------===//
1304
1305 let AssemblerPredicate = isGFX11Only in {
1306   multiclass VOPC_Real_gfx11<bits<9> op> {
1307     defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32");
1308     defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64");
1309     let DecoderNamespace = "GFX11" in {
1310       def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1311                        VOPCe<op{7-0}>;
1312       def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1313                        VOP3a_gfx11<{0, op}, ps64.Pfl> {
1314         // Encoding used for VOPC instructions encoded as VOP3 differs from
1315         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1316         bits<8> sdst;
1317         let Inst{7-0} = sdst;
1318       }
1319     } // End DecoderNamespace = "GFX11"
1320
1321     defm : VOPCInstAliases<NAME, "gfx11">;
1322
1323     foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1324       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp");
1325       defvar AsmDPP = ps32.Pfl.AsmDPP16;
1326       let DecoderNamespace = "DPPGFX11" in {
1327         def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1328                                              SIEncodingFamily.GFX11>;
1329         def _e32_dpp_w32_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
1330           let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
1331           let isAsmParserOnly = 1;
1332           let WaveSizePredicate = isWave32;
1333         }
1334         def _e32_dpp_w64_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
1335           let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
1336           let isAsmParserOnly = 1;
1337           let WaveSizePredicate = isWave64;
1338         }
1339       }
1340       defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
1341       let DecoderNamespace = "DPP8GFX11" in {
1342         def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32>;
1343         def _e32_dpp8_w32_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
1344           let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
1345           let isAsmParserOnly = 1;
1346           let WaveSizePredicate = isWave32;
1347         }
1348         def _e32_dpp8_w64_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
1349           let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
1350           let isAsmParserOnly = 1;
1351           let WaveSizePredicate = isWave64;
1352         }
1353       }
1354     }
1355     foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1356       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp");
1357       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1358       let DecoderNamespace = "DPPGFX11" in {
1359         def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP>,
1360                              SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
1361         def _e64_dpp_w32_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
1362           let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
1363           let isAsmParserOnly = 1;
1364           let WaveSizePredicate = isWave32;
1365         }
1366         def _e64_dpp_w64_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
1367           let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
1368           let isAsmParserOnly = 1;
1369           let WaveSizePredicate = isWave64;
1370         }
1371       }
1372       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1373       let DecoderNamespace = "DPP8GFX11" in {
1374         def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64>;
1375         def _e64_dpp8_w32_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
1376           let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
1377           let isAsmParserOnly = 1;
1378           let WaveSizePredicate = isWave32;
1379         }
1380         def _e64_dpp8_w64_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
1381           let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
1382           let isAsmParserOnly = 1;
1383           let WaveSizePredicate = isWave64;
1384         }
1385       }
1386     }
1387
1388   }
1389
1390   multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName,
1391         string asm_name, string pseudo_mnemonic = ""> {
1392     defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32");
1393     defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64");
1394     let DecoderNamespace = "GFX11" in {
1395       def _e32_gfx11 :
1396         // 32 and 64 bit forms of the instruction have _e32 and _e64
1397         // respectively appended to their assembly mnemonic.
1398         // _e64 is printed as part of the VOPDstS64orS32 operand, whereas
1399         // the destination-less 32bit forms add it to the asmString here.
1400         VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">,
1401         VOPCe<op{7-0}>,
1402         MnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic,
1403                           pseudo_mnemonic),
1404                       asm_name, ps32.AsmVariantName>,
1405         Requires<[isGFX11Plus]>;
1406       def _e64_gfx11 :
1407             VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
1408             VOP3a_gfx11<{0, op}, ps64.Pfl>,
1409             MnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic,
1410                               pseudo_mnemonic),
1411                           asm_name, ps64.AsmVariantName>,
1412             Requires<[isGFX11Plus]> {
1413         // Encoding used for VOPC instructions encoded as VOP3 differs from
1414         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1415         bits<8> sdst;
1416         let Inst{7-0} = sdst;
1417       }
1418     } // End DecoderNamespace = "GFX11"
1419
1420     defm : VOPCInstAliases<OpName, "gfx11", NAME, asm_name>;
1421
1422     foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1423       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp");
1424       defvar AsmDPP = ps32.Pfl.AsmDPP16;
1425       let DecoderNamespace = "DPPGFX11" in {
1426         def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1427                                              SIEncodingFamily.GFX11, asm_name>;
1428         def _e32_dpp_w32_gfx11
1429             : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
1430           let AsmString = asm_name # " vcc_lo, " # AsmDPP;
1431           let isAsmParserOnly = 1;
1432           let WaveSizePredicate = isWave32;
1433         }
1434         def _e32_dpp_w64_gfx11
1435             : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
1436           let AsmString = asm_name # " vcc, " # AsmDPP;
1437           let isAsmParserOnly = 1;
1438           let WaveSizePredicate = isWave64;
1439         }
1440       }
1441       defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
1442       let DecoderNamespace = "DPP8GFX11" in {
1443         def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
1444         def _e32_dpp8_w32_gfx11
1445             : VOPC_DPP8<op{7-0}, ps32, asm_name> {
1446           let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
1447           let isAsmParserOnly = 1;
1448           let WaveSizePredicate = isWave32;
1449         }
1450         def _e32_dpp8_w64_gfx11
1451             : VOPC_DPP8<op{7-0}, ps32, asm_name> {
1452           let AsmString = asm_name # " vcc, " # AsmDPP8;
1453           let isAsmParserOnly = 1;
1454           let WaveSizePredicate = isWave64;
1455         }
1456       }
1457     }
1458
1459     foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1460       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp");
1461       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1462       let DecoderNamespace = "DPPGFX11" in {
1463         def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>,
1464                              SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
1465         def _e64_dpp_w32_gfx11
1466             : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
1467           let AsmString = asm_name # " vcc_lo, " # AsmDPP;
1468           let isAsmParserOnly = 1;
1469           let WaveSizePredicate = isWave32;
1470         }
1471         def _e64_dpp_w64_gfx11
1472             : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
1473           let AsmString = asm_name # " vcc, " # AsmDPP;
1474           let isAsmParserOnly = 1;
1475           let WaveSizePredicate = isWave64;
1476         }
1477       }
1478       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1479       let DecoderNamespace = "DPP8GFX11" in {
1480         def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>;
1481         def _e64_dpp8_w32_gfx11
1482             : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
1483           let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
1484           let isAsmParserOnly = 1;
1485           let WaveSizePredicate = isWave32;
1486         }
1487         def _e64_dpp8_w64_gfx11
1488             : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
1489           let AsmString = asm_name # " vcc, " # AsmDPP8;
1490           let isAsmParserOnly = 1;
1491           let WaveSizePredicate = isWave64;
1492         }
1493       }
1494     }
1495   }
1496
1497   multiclass VOPC_Real_t16_gfx11<bits<9> op, string asm_name,
1498         string OpName = NAME> : VOPC_Real_with_name_gfx11<op, OpName, asm_name>;
1499
1500   multiclass VOPCX_Real_gfx11<bits<9> op> {
1501     defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32");
1502     defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64");
1503     let DecoderNamespace = "GFX11" in {
1504       def _e32_gfx11 :
1505         VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1506         VOPCe<op{7-0}> {
1507           let AsmString = !subst("_nosdst", "", ps32.PseudoInstr)
1508                           # " " # ps32.AsmOperands;
1509         }
1510       def _e64_gfx11 :
1511         VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1512         VOP3a_gfx11<{0, op}, ps64.Pfl> {
1513           let Inst{7-0} = ?; // sdst
1514           let AsmString = !subst("_nosdst", "", ps64.Mnemonic)
1515                           # "{_e64} " # ps64.AsmOperands;
1516         }
1517     } // End DecoderNamespace = "GFX11"
1518
1519     defm : VOPCXInstAliases<NAME, "gfx11">;
1520
1521     foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1522       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp");
1523       defvar AsmDPP = ps32.Pfl.AsmDPP16;
1524       let DecoderNamespace = "DPPGFX11" in {
1525         def _e32_dpp_gfx11
1526             : VOPC_DPP16_SIMC<op{7-0}, psDPP, SIEncodingFamily.GFX11> {
1527           let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP;
1528         }
1529       }
1530       defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
1531       let DecoderNamespace = "DPP8GFX11" in {
1532         def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
1533           let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8;
1534         }
1535       }
1536     }
1537
1538     foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1539       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp");
1540       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1541       let DecoderNamespace = "DPPGFX11" in {
1542         def _e64_dpp_gfx11
1543             : VOPC64_DPP16_NoDst<{0, op}, psDPP>,
1544               SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
1545           let AsmString = !subst("_nosdst", "", psDPP.OpName)
1546                           # "{_e64_dpp} " # AsmDPP;
1547         }
1548       }
1549       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1550       let DecoderNamespace = "DPP8GFX11" in {
1551         def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64> {
1552           let AsmString = !subst("_nosdst", "", ps64.OpName)
1553                           # "{_e64_dpp} " # AsmDPP8;
1554         }
1555       }
1556     }
1557   }
1558
1559   multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName,
1560         string asm_name, string pseudo_mnemonic = ""> {
1561     defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32");
1562     defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64");
1563     let DecoderNamespace = "GFX11" in {
1564       def _e32_gfx11
1565           : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
1566             MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic),
1567                               pseudo_mnemonic),
1568                           asm_name, ps32.AsmVariantName>,
1569             Requires<[isGFX11Plus]>,
1570             VOPCe<op{7-0}> {
1571         let AsmString = asm_name # "{_e32} " # ps32.AsmOperands;
1572       }
1573       def _e64_gfx11
1574           : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
1575             MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic),
1576                               pseudo_mnemonic),
1577                           asm_name, ps64.AsmVariantName>,
1578             Requires<[isGFX11Plus]>,
1579             VOP3a_gfx11<{0, op}, ps64.Pfl> {
1580         let Inst{7-0} = ? ; // sdst
1581         let AsmString = asm_name # "{_e64} " # ps64.AsmOperands;
1582       }
1583     } // End DecoderNamespace = "GFX11"
1584
1585     defm : VOPCXInstAliases<OpName, "gfx11", NAME, asm_name>;
1586
1587     foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1588       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp");
1589       let DecoderNamespace = "DPPGFX11" in {
1590         def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1591                                              SIEncodingFamily.GFX11, asm_name>;
1592       }
1593       let DecoderNamespace = "DPP8GFX11" in {
1594         def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
1595       }
1596     }
1597     foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1598       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp");
1599       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1600       let DecoderNamespace = "DPPGFX11" in {
1601         def _e64_dpp_gfx11
1602             : VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>,
1603               SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
1604           let AsmString = asm_name # "{_e64_dpp} " # AsmDPP;
1605         }
1606       }
1607       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1608       let DecoderNamespace = "DPP8GFX11" in {
1609         def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> {
1610           let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8;
1611         }
1612       }
1613     }
1614   }
1615
1616   multiclass VOPCX_Real_t16_gfx11<bits<9> op, string asm_name,
1617         string OpName = NAME> : VOPCX_Real_with_name_gfx11<op, OpName, asm_name>;
1618
1619
1620 } // End AssemblerPredicate = isGFX11Only
1621
1622 defm V_CMP_F_F16_t16      : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">;
1623 defm V_CMP_LT_F16_t16     : VOPC_Real_t16_gfx11<0x001, "v_cmp_lt_f16">;
1624 defm V_CMP_EQ_F16_t16     : VOPC_Real_t16_gfx11<0x002, "v_cmp_eq_f16">;
1625 defm V_CMP_LE_F16_t16     : VOPC_Real_t16_gfx11<0x003, "v_cmp_le_f16">;
1626 defm V_CMP_GT_F16_t16     : VOPC_Real_t16_gfx11<0x004, "v_cmp_gt_f16">;
1627 defm V_CMP_LG_F16_t16     : VOPC_Real_t16_gfx11<0x005, "v_cmp_lg_f16">;
1628 defm V_CMP_GE_F16_t16     : VOPC_Real_t16_gfx11<0x006, "v_cmp_ge_f16">;
1629 defm V_CMP_O_F16_t16      : VOPC_Real_t16_gfx11<0x007, "v_cmp_o_f16">;
1630 defm V_CMP_U_F16_t16      : VOPC_Real_t16_gfx11<0x008, "v_cmp_u_f16">;
1631 defm V_CMP_NGE_F16_t16    : VOPC_Real_t16_gfx11<0x009, "v_cmp_nge_f16">;
1632 defm V_CMP_NLG_F16_t16    : VOPC_Real_t16_gfx11<0x00a, "v_cmp_nlg_f16">;
1633 defm V_CMP_NGT_F16_t16    : VOPC_Real_t16_gfx11<0x00b, "v_cmp_ngt_f16">;
1634 defm V_CMP_NLE_F16_t16    : VOPC_Real_t16_gfx11<0x00c, "v_cmp_nle_f16">;
1635 defm V_CMP_NEQ_F16_t16    : VOPC_Real_t16_gfx11<0x00d, "v_cmp_neq_f16">;
1636 defm V_CMP_NLT_F16_t16    : VOPC_Real_t16_gfx11<0x00e, "v_cmp_nlt_f16">;
1637 defm V_CMP_T_F16_t16      : VOPC_Real_with_name_gfx11<0x00f, "V_CMP_TRU_F16_t16", "v_cmp_t_f16", "v_cmp_tru_f16">;
1638 defm V_CMP_F_F32      : VOPC_Real_gfx11<0x010>;
1639 defm V_CMP_LT_F32     : VOPC_Real_gfx11<0x011>;
1640 defm V_CMP_EQ_F32     : VOPC_Real_gfx11<0x012>;
1641 defm V_CMP_LE_F32     : VOPC_Real_gfx11<0x013>;
1642 defm V_CMP_GT_F32     : VOPC_Real_gfx11<0x014>;
1643 defm V_CMP_LG_F32     : VOPC_Real_gfx11<0x015>;
1644 defm V_CMP_GE_F32     : VOPC_Real_gfx11<0x016>;
1645 defm V_CMP_O_F32      : VOPC_Real_gfx11<0x017>;
1646 defm V_CMP_U_F32      : VOPC_Real_gfx11<0x018>;
1647 defm V_CMP_NGE_F32    : VOPC_Real_gfx11<0x019>;
1648 defm V_CMP_NLG_F32    : VOPC_Real_gfx11<0x01a>;
1649 defm V_CMP_NGT_F32    : VOPC_Real_gfx11<0x01b>;
1650 defm V_CMP_NLE_F32    : VOPC_Real_gfx11<0x01c>;
1651 defm V_CMP_NEQ_F32    : VOPC_Real_gfx11<0x01d>;
1652 defm V_CMP_NLT_F32    : VOPC_Real_gfx11<0x01e>;
1653 defm V_CMP_T_F32      : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">;
1654 defm V_CMP_T_F64      : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">;
1655 defm V_CMP_LT_I16_t16     : VOPC_Real_t16_gfx11<0x031, "v_cmp_lt_i16">;
1656 defm V_CMP_EQ_I16_t16     : VOPC_Real_t16_gfx11<0x032, "v_cmp_eq_i16">;
1657 defm V_CMP_LE_I16_t16     : VOPC_Real_t16_gfx11<0x033, "v_cmp_le_i16">;
1658 defm V_CMP_GT_I16_t16     : VOPC_Real_t16_gfx11<0x034, "v_cmp_gt_i16">;
1659 defm V_CMP_NE_I16_t16     : VOPC_Real_t16_gfx11<0x035, "v_cmp_ne_i16">;
1660 defm V_CMP_GE_I16_t16     : VOPC_Real_t16_gfx11<0x036, "v_cmp_ge_i16">;
1661 defm V_CMP_LT_U16_t16     : VOPC_Real_t16_gfx11<0x039, "v_cmp_lt_u16">;
1662 defm V_CMP_EQ_U16_t16     : VOPC_Real_t16_gfx11<0x03a, "v_cmp_eq_u16">;
1663 defm V_CMP_LE_U16_t16     : VOPC_Real_t16_gfx11<0x03b, "v_cmp_le_u16">;
1664 defm V_CMP_GT_U16_t16     : VOPC_Real_t16_gfx11<0x03c, "v_cmp_gt_u16">;
1665 defm V_CMP_NE_U16_t16     : VOPC_Real_t16_gfx11<0x03d, "v_cmp_ne_u16">;
1666 defm V_CMP_GE_U16_t16     : VOPC_Real_t16_gfx11<0x03e, "v_cmp_ge_u16">;
1667 defm V_CMP_F_I32      : VOPC_Real_gfx11<0x040>;
1668 defm V_CMP_LT_I32     : VOPC_Real_gfx11<0x041>;
1669 defm V_CMP_EQ_I32     : VOPC_Real_gfx11<0x042>;
1670 defm V_CMP_LE_I32     : VOPC_Real_gfx11<0x043>;
1671 defm V_CMP_GT_I32     : VOPC_Real_gfx11<0x044>;
1672 defm V_CMP_NE_I32     : VOPC_Real_gfx11<0x045>;
1673 defm V_CMP_GE_I32     : VOPC_Real_gfx11<0x046>;
1674 defm V_CMP_T_I32      : VOPC_Real_gfx11<0x047>;
1675 defm V_CMP_F_U32      : VOPC_Real_gfx11<0x048>;
1676 defm V_CMP_LT_U32     : VOPC_Real_gfx11<0x049>;
1677 defm V_CMP_EQ_U32     : VOPC_Real_gfx11<0x04a>;
1678 defm V_CMP_LE_U32     : VOPC_Real_gfx11<0x04b>;
1679 defm V_CMP_GT_U32     : VOPC_Real_gfx11<0x04c>;
1680 defm V_CMP_NE_U32     : VOPC_Real_gfx11<0x04d>;
1681 defm V_CMP_GE_U32     : VOPC_Real_gfx11<0x04e>;
1682 defm V_CMP_T_U32      : VOPC_Real_gfx11<0x04f>;
1683
1684 defm V_CMP_F_I64      : VOPC_Real_gfx11<0x050>;
1685 defm V_CMP_LT_I64     : VOPC_Real_gfx11<0x051>;
1686 defm V_CMP_EQ_I64     : VOPC_Real_gfx11<0x052>;
1687 defm V_CMP_LE_I64     : VOPC_Real_gfx11<0x053>;
1688 defm V_CMP_GT_I64     : VOPC_Real_gfx11<0x054>;
1689 defm V_CMP_NE_I64     : VOPC_Real_gfx11<0x055>;
1690 defm V_CMP_GE_I64     : VOPC_Real_gfx11<0x056>;
1691 defm V_CMP_T_I64      : VOPC_Real_gfx11<0x057>;
1692 defm V_CMP_F_U64      : VOPC_Real_gfx11<0x058>;
1693 defm V_CMP_LT_U64     : VOPC_Real_gfx11<0x059>;
1694 defm V_CMP_EQ_U64     : VOPC_Real_gfx11<0x05a>;
1695 defm V_CMP_LE_U64     : VOPC_Real_gfx11<0x05b>;
1696 defm V_CMP_GT_U64     : VOPC_Real_gfx11<0x05c>;
1697 defm V_CMP_NE_U64     : VOPC_Real_gfx11<0x05d>;
1698 defm V_CMP_GE_U64     : VOPC_Real_gfx11<0x05e>;
1699 defm V_CMP_T_U64      : VOPC_Real_gfx11<0x05f>;
1700
1701 defm V_CMP_CLASS_F16_t16  : VOPC_Real_t16_gfx11<0x07d, "v_cmp_class_f16">;
1702 defm V_CMP_CLASS_F32  : VOPC_Real_gfx11<0x07e>;
1703 defm V_CMP_CLASS_F64  : VOPC_Real_gfx11<0x07f>;
1704
1705 defm V_CMPX_F_F16_t16     : VOPCX_Real_t16_gfx11<0x080, "v_cmpx_f_f16">;
1706 defm V_CMPX_LT_F16_t16    : VOPCX_Real_t16_gfx11<0x081, "v_cmpx_lt_f16">;
1707 defm V_CMPX_EQ_F16_t16    : VOPCX_Real_t16_gfx11<0x082, "v_cmpx_eq_f16">;
1708 defm V_CMPX_LE_F16_t16    : VOPCX_Real_t16_gfx11<0x083, "v_cmpx_le_f16">;
1709 defm V_CMPX_GT_F16_t16    : VOPCX_Real_t16_gfx11<0x084, "v_cmpx_gt_f16">;
1710 defm V_CMPX_LG_F16_t16    : VOPCX_Real_t16_gfx11<0x085, "v_cmpx_lg_f16">;
1711 defm V_CMPX_GE_F16_t16    : VOPCX_Real_t16_gfx11<0x086, "v_cmpx_ge_f16">;
1712 defm V_CMPX_O_F16_t16     : VOPCX_Real_t16_gfx11<0x087, "v_cmpx_o_f16">;
1713 defm V_CMPX_U_F16_t16     : VOPCX_Real_t16_gfx11<0x088, "v_cmpx_u_f16">;
1714 defm V_CMPX_NGE_F16_t16   : VOPCX_Real_t16_gfx11<0x089, "v_cmpx_nge_f16">;
1715 defm V_CMPX_NLG_F16_t16   : VOPCX_Real_t16_gfx11<0x08a, "v_cmpx_nlg_f16">;
1716 defm V_CMPX_NGT_F16_t16   : VOPCX_Real_t16_gfx11<0x08b, "v_cmpx_ngt_f16">;
1717 defm V_CMPX_NLE_F16_t16   : VOPCX_Real_t16_gfx11<0x08c, "v_cmpx_nle_f16">;
1718 defm V_CMPX_NEQ_F16_t16   : VOPCX_Real_t16_gfx11<0x08d, "v_cmpx_neq_f16">;
1719 defm V_CMPX_NLT_F16_t16   : VOPCX_Real_t16_gfx11<0x08e, "v_cmpx_nlt_f16">;
1720 defm V_CMPX_T_F16_t16     : VOPCX_Real_with_name_gfx11<0x08f, "V_CMPX_TRU_F16_t16", "v_cmpx_t_f16", "v_cmpx_tru_f16">;
1721 defm V_CMPX_F_F32     : VOPCX_Real_gfx11<0x090>;
1722 defm V_CMPX_LT_F32    : VOPCX_Real_gfx11<0x091>;
1723 defm V_CMPX_EQ_F32    : VOPCX_Real_gfx11<0x092>;
1724 defm V_CMPX_LE_F32    : VOPCX_Real_gfx11<0x093>;
1725 defm V_CMPX_GT_F32    : VOPCX_Real_gfx11<0x094>;
1726 defm V_CMPX_LG_F32    : VOPCX_Real_gfx11<0x095>;
1727 defm V_CMPX_GE_F32    : VOPCX_Real_gfx11<0x096>;
1728 defm V_CMPX_O_F32     : VOPCX_Real_gfx11<0x097>;
1729 defm V_CMPX_U_F32     : VOPCX_Real_gfx11<0x098>;
1730 defm V_CMPX_NGE_F32   : VOPCX_Real_gfx11<0x099>;
1731 defm V_CMPX_NLG_F32   : VOPCX_Real_gfx11<0x09a>;
1732 defm V_CMPX_NGT_F32   : VOPCX_Real_gfx11<0x09b>;
1733 defm V_CMPX_NLE_F32   : VOPCX_Real_gfx11<0x09c>;
1734 defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx11<0x09d>;
1735 defm V_CMPX_NLT_F32   : VOPCX_Real_gfx11<0x09e>;
1736 defm V_CMPX_T_F32     : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">;
1737
1738 defm V_CMPX_F_F64     : VOPCX_Real_gfx11<0x0a0>;
1739 defm V_CMPX_LT_F64    : VOPCX_Real_gfx11<0x0a1>;
1740 defm V_CMPX_EQ_F64    : VOPCX_Real_gfx11<0x0a2>;
1741 defm V_CMPX_LE_F64    : VOPCX_Real_gfx11<0x0a3>;
1742 defm V_CMPX_GT_F64    : VOPCX_Real_gfx11<0x0a4>;
1743 defm V_CMPX_LG_F64    : VOPCX_Real_gfx11<0x0a5>;
1744 defm V_CMPX_GE_F64    : VOPCX_Real_gfx11<0x0a6>;
1745 defm V_CMPX_O_F64     : VOPCX_Real_gfx11<0x0a7>;
1746 defm V_CMPX_U_F64     : VOPCX_Real_gfx11<0x0a8>;
1747 defm V_CMPX_NGE_F64   : VOPCX_Real_gfx11<0x0a9>;
1748 defm V_CMPX_NLG_F64   : VOPCX_Real_gfx11<0x0aa>;
1749 defm V_CMPX_NGT_F64   : VOPCX_Real_gfx11<0x0ab>;
1750 defm V_CMPX_NLE_F64   : VOPCX_Real_gfx11<0x0ac>;
1751 defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx11<0x0ad>;
1752 defm V_CMPX_NLT_F64   : VOPCX_Real_gfx11<0x0ae>;
1753 defm V_CMPX_T_F64     : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">;
1754
1755 defm V_CMPX_LT_I16_t16    : VOPCX_Real_t16_gfx11<0x0b1, "v_cmpx_lt_i16">;
1756 defm V_CMPX_EQ_I16_t16    : VOPCX_Real_t16_gfx11<0x0b2, "v_cmpx_eq_i16">;
1757 defm V_CMPX_LE_I16_t16    : VOPCX_Real_t16_gfx11<0x0b3, "v_cmpx_le_i16">;
1758 defm V_CMPX_GT_I16_t16    : VOPCX_Real_t16_gfx11<0x0b4, "v_cmpx_gt_i16">;
1759 defm V_CMPX_NE_I16_t16    : VOPCX_Real_t16_gfx11<0x0b5, "v_cmpx_ne_i16">;
1760 defm V_CMPX_GE_I16_t16    : VOPCX_Real_t16_gfx11<0x0b6, "v_cmpx_ge_i16">;
1761 defm V_CMPX_LT_U16_t16    : VOPCX_Real_t16_gfx11<0x0b9, "v_cmpx_lt_u16">;
1762 defm V_CMPX_EQ_U16_t16    : VOPCX_Real_t16_gfx11<0x0ba, "v_cmpx_eq_u16">;
1763 defm V_CMPX_LE_U16_t16    : VOPCX_Real_t16_gfx11<0x0bb, "v_cmpx_le_u16">;
1764 defm V_CMPX_GT_U16_t16    : VOPCX_Real_t16_gfx11<0x0bc, "v_cmpx_gt_u16">;
1765 defm V_CMPX_NE_U16_t16    : VOPCX_Real_t16_gfx11<0x0bd, "v_cmpx_ne_u16">;
1766 defm V_CMPX_GE_U16_t16    : VOPCX_Real_t16_gfx11<0x0be, "v_cmpx_ge_u16">;
1767 defm V_CMPX_F_I32     : VOPCX_Real_gfx11<0x0c0>;
1768 defm V_CMPX_LT_I32    : VOPCX_Real_gfx11<0x0c1>;
1769 defm V_CMPX_EQ_I32    : VOPCX_Real_gfx11<0x0c2>;
1770 defm V_CMPX_LE_I32    : VOPCX_Real_gfx11<0x0c3>;
1771 defm V_CMPX_GT_I32    : VOPCX_Real_gfx11<0x0c4>;
1772 defm V_CMPX_NE_I32    : VOPCX_Real_gfx11<0x0c5>;
1773 defm V_CMPX_GE_I32    : VOPCX_Real_gfx11<0x0c6>;
1774 defm V_CMPX_T_I32     : VOPCX_Real_gfx11<0x0c7>;
1775 defm V_CMPX_F_U32     : VOPCX_Real_gfx11<0x0c8>;
1776 defm V_CMPX_LT_U32    : VOPCX_Real_gfx11<0x0c9>;
1777 defm V_CMPX_EQ_U32    : VOPCX_Real_gfx11<0x0ca>;
1778 defm V_CMPX_LE_U32    : VOPCX_Real_gfx11<0x0cb>;
1779 defm V_CMPX_GT_U32    : VOPCX_Real_gfx11<0x0cc>;
1780 defm V_CMPX_NE_U32    : VOPCX_Real_gfx11<0x0cd>;
1781 defm V_CMPX_GE_U32    : VOPCX_Real_gfx11<0x0ce>;
1782 defm V_CMPX_T_U32     : VOPCX_Real_gfx11<0x0cf>;
1783
1784 defm V_CMPX_F_I64     : VOPCX_Real_gfx11<0x0d0>;
1785 defm V_CMPX_LT_I64    : VOPCX_Real_gfx11<0x0d1>;
1786 defm V_CMPX_EQ_I64    : VOPCX_Real_gfx11<0x0d2>;
1787 defm V_CMPX_LE_I64    : VOPCX_Real_gfx11<0x0d3>;
1788 defm V_CMPX_GT_I64    : VOPCX_Real_gfx11<0x0d4>;
1789 defm V_CMPX_NE_I64    : VOPCX_Real_gfx11<0x0d5>;
1790 defm V_CMPX_GE_I64    : VOPCX_Real_gfx11<0x0d6>;
1791 defm V_CMPX_T_I64     : VOPCX_Real_gfx11<0x0d7>;
1792 defm V_CMPX_F_U64     : VOPCX_Real_gfx11<0x0d8>;
1793 defm V_CMPX_LT_U64    : VOPCX_Real_gfx11<0x0d9>;
1794 defm V_CMPX_EQ_U64    : VOPCX_Real_gfx11<0x0da>;
1795 defm V_CMPX_LE_U64    : VOPCX_Real_gfx11<0x0db>;
1796 defm V_CMPX_GT_U64    : VOPCX_Real_gfx11<0x0dc>;
1797 defm V_CMPX_NE_U64    : VOPCX_Real_gfx11<0x0dd>;
1798 defm V_CMPX_GE_U64    : VOPCX_Real_gfx11<0x0de>;
1799 defm V_CMPX_T_U64     : VOPCX_Real_gfx11<0x0df>;
1800 defm V_CMPX_CLASS_F16_t16 : VOPCX_Real_t16_gfx11<0x0fd, "v_cmpx_class_f16">;
1801 defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11<0x0fe>;
1802 defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11<0x0ff>;
1803
1804 //===----------------------------------------------------------------------===//
1805 // GFX10.
1806 //===----------------------------------------------------------------------===//
1807
1808 let AssemblerPredicate = isGFX10Only in {
1809   multiclass VOPC_Real_gfx10<bits<9> op> {
1810     let DecoderNamespace = "GFX10" in {
1811       def _e32_gfx10 :
1812         VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
1813         VOPCe<op{7-0}>;
1814       def _e64_gfx10 :
1815         VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1816         VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1817         // Encoding used for VOPC instructions encoded as VOP3 differs from
1818         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1819         bits<8> sdst;
1820         let Inst{7-0} = sdst;
1821       }
1822     } // End DecoderNamespace = "GFX10"
1823
1824     foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1825     def _sdwa_gfx10 :
1826       VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
1827       VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1828
1829     defm : VOPCInstAliases<NAME, "gfx10">;
1830   }
1831
1832   multiclass VOPCX_Real_gfx10<bits<9> op> {
1833     let DecoderNamespace = "GFX10" in {
1834       def _e32_gfx10 :
1835         VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>,
1836         VOPCe<op{7-0}> {
1837           let AsmString = !subst("_nosdst", "", !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").PseudoInstr)
1838                           # " " # !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").AsmOperands;
1839         }
1840
1841       def _e64_gfx10 :
1842         VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>,
1843         VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Pfl> {
1844           let Inst{7-0} = ?; // sdst
1845           let AsmString = !subst("_nosdst", "", !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Mnemonic)
1846                           # "{_e64} " # !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").AsmOperands;
1847         }
1848     } // End DecoderNamespace = "GFX10"
1849
1850     foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32").Pfl.HasExtSDWA9>.ret in
1851     def _sdwa_gfx10 :
1852       VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa")>,
1853       VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> {
1854         let AsmString = !subst("_nosdst", "", !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Mnemonic)
1855                         # "{_sdwa} " # !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").AsmOperands9;
1856       }
1857
1858     defm : VOPCXInstAliases<NAME, "gfx10">;
1859   }
1860 } // End AssemblerPredicate = isGFX10Only
1861
1862 defm V_CMP_LT_I16     : VOPC_Real_gfx10<0x089>;
1863 defm V_CMP_EQ_I16     : VOPC_Real_gfx10<0x08a>;
1864 defm V_CMP_LE_I16     : VOPC_Real_gfx10<0x08b>;
1865 defm V_CMP_GT_I16     : VOPC_Real_gfx10<0x08c>;
1866 defm V_CMP_NE_I16     : VOPC_Real_gfx10<0x08d>;
1867 defm V_CMP_GE_I16     : VOPC_Real_gfx10<0x08e>;
1868 defm V_CMP_CLASS_F16  : VOPC_Real_gfx10<0x08f>;
1869 defm V_CMPX_LT_I16    : VOPCX_Real_gfx10<0x099>;
1870 defm V_CMPX_EQ_I16    : VOPCX_Real_gfx10<0x09a>;
1871 defm V_CMPX_LE_I16    : VOPCX_Real_gfx10<0x09b>;
1872 defm V_CMPX_GT_I16    : VOPCX_Real_gfx10<0x09c>;
1873 defm V_CMPX_NE_I16    : VOPCX_Real_gfx10<0x09d>;
1874 defm V_CMPX_GE_I16    : VOPCX_Real_gfx10<0x09e>;
1875 defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx10<0x09f>;
1876 defm V_CMP_LT_U16     : VOPC_Real_gfx10<0x0a9>;
1877 defm V_CMP_EQ_U16     : VOPC_Real_gfx10<0x0aa>;
1878 defm V_CMP_LE_U16     : VOPC_Real_gfx10<0x0ab>;
1879 defm V_CMP_GT_U16     : VOPC_Real_gfx10<0x0ac>;
1880 defm V_CMP_NE_U16     : VOPC_Real_gfx10<0x0ad>;
1881 defm V_CMP_GE_U16     : VOPC_Real_gfx10<0x0ae>;
1882 defm V_CMPX_LT_U16    : VOPCX_Real_gfx10<0x0b9>;
1883 defm V_CMPX_EQ_U16    : VOPCX_Real_gfx10<0x0ba>;
1884 defm V_CMPX_LE_U16    : VOPCX_Real_gfx10<0x0bb>;
1885 defm V_CMPX_GT_U16    : VOPCX_Real_gfx10<0x0bc>;
1886 defm V_CMPX_NE_U16    : VOPCX_Real_gfx10<0x0bd>;
1887 defm V_CMPX_GE_U16    : VOPCX_Real_gfx10<0x0be>;
1888 defm V_CMP_F_F16      : VOPC_Real_gfx10<0x0c8>;
1889 defm V_CMP_LT_F16     : VOPC_Real_gfx10<0x0c9>;
1890 defm V_CMP_EQ_F16     : VOPC_Real_gfx10<0x0ca>;
1891 defm V_CMP_LE_F16     : VOPC_Real_gfx10<0x0cb>;
1892 defm V_CMP_GT_F16     : VOPC_Real_gfx10<0x0cc>;
1893 defm V_CMP_LG_F16     : VOPC_Real_gfx10<0x0cd>;
1894 defm V_CMP_GE_F16     : VOPC_Real_gfx10<0x0ce>;
1895 defm V_CMP_O_F16      : VOPC_Real_gfx10<0x0cf>;
1896 defm V_CMPX_F_F16     : VOPCX_Real_gfx10<0x0d8>;
1897 defm V_CMPX_LT_F16    : VOPCX_Real_gfx10<0x0d9>;
1898 defm V_CMPX_EQ_F16    : VOPCX_Real_gfx10<0x0da>;
1899 defm V_CMPX_LE_F16    : VOPCX_Real_gfx10<0x0db>;
1900 defm V_CMPX_GT_F16    : VOPCX_Real_gfx10<0x0dc>;
1901 defm V_CMPX_LG_F16    : VOPCX_Real_gfx10<0x0dd>;
1902 defm V_CMPX_GE_F16    : VOPCX_Real_gfx10<0x0de>;
1903 defm V_CMPX_O_F16     : VOPCX_Real_gfx10<0x0df>;
1904 defm V_CMP_U_F16      : VOPC_Real_gfx10<0x0e8>;
1905 defm V_CMP_NGE_F16    : VOPC_Real_gfx10<0x0e9>;
1906 defm V_CMP_NLG_F16    : VOPC_Real_gfx10<0x0ea>;
1907 defm V_CMP_NGT_F16    : VOPC_Real_gfx10<0x0eb>;
1908 defm V_CMP_NLE_F16    : VOPC_Real_gfx10<0x0ec>;
1909 defm V_CMP_NEQ_F16    : VOPC_Real_gfx10<0x0ed>;
1910 defm V_CMP_NLT_F16    : VOPC_Real_gfx10<0x0ee>;
1911 defm V_CMP_TRU_F16    : VOPC_Real_gfx10<0x0ef>;
1912 defm V_CMPX_U_F16     : VOPCX_Real_gfx10<0x0f8>;
1913 defm V_CMPX_NGE_F16   : VOPCX_Real_gfx10<0x0f9>;
1914 defm V_CMPX_NLG_F16   : VOPCX_Real_gfx10<0x0fa>;
1915 defm V_CMPX_NGT_F16   : VOPCX_Real_gfx10<0x0fb>;
1916 defm V_CMPX_NLE_F16   : VOPCX_Real_gfx10<0x0fc>;
1917 defm V_CMPX_NEQ_F16   : VOPCX_Real_gfx10<0x0fd>;
1918 defm V_CMPX_NLT_F16   : VOPCX_Real_gfx10<0x0fe>;
1919 defm V_CMPX_TRU_F16   : VOPCX_Real_gfx10<0x0ff>;
1920
1921 //===----------------------------------------------------------------------===//
1922 // GFX6, GFX7, GFX10.
1923 //===----------------------------------------------------------------------===//
1924
1925 let AssemblerPredicate = isGFX6GFX7 in {
1926   multiclass VOPC_Real_gfx6_gfx7<bits<9> op> {
1927     let DecoderNamespace = "GFX6GFX7" in {
1928       def _e32_gfx6_gfx7 :
1929         VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
1930         VOPCe<op{7-0}>;
1931       def _e64_gfx6_gfx7 :
1932         VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1933         VOP3a_gfx6_gfx7<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1934         // Encoding used for VOPC instructions encoded as VOP3 differs from
1935         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1936         bits<8> sdst;
1937         let Inst{7-0} = sdst;
1938       }
1939     } // End DecoderNamespace = "GFX6GFX7"
1940
1941     defm : VOPCInstAliases<NAME, "gfx6_gfx7">;
1942   }
1943 } // End AssemblerPredicate = isGFX6GFX7
1944
1945 multiclass VOPC_Real_gfx6_gfx7_gfx10<bits<9> op> :
1946   VOPC_Real_gfx6_gfx7<op>, VOPC_Real_gfx10<op>;
1947
1948 multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> :
1949   VOPC_Real_gfx6_gfx7<op>;
1950
1951 multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> :
1952   VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>;
1953
1954 multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
1955   VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_gfx11<op>;
1956
1957 multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
1958   VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real_gfx11<op>;
1959
1960 defm V_CMP_F_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x000>;
1961 defm V_CMP_LT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x001>;
1962 defm V_CMP_EQ_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x002>;
1963 defm V_CMP_LE_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x003>;
1964 defm V_CMP_GT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x004>;
1965 defm V_CMP_LG_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x005>;
1966 defm V_CMP_GE_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x006>;
1967 defm V_CMP_O_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x007>;
1968 defm V_CMP_U_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x008>;
1969 defm V_CMP_NGE_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x009>;
1970 defm V_CMP_NLG_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00a>;
1971 defm V_CMP_NGT_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00b>;
1972 defm V_CMP_NLE_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00c>;
1973 defm V_CMP_NEQ_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00d>;
1974 defm V_CMP_NLT_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00e>;
1975 defm V_CMP_TRU_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00f>;
1976 defm V_CMPX_F_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x010>;
1977 defm V_CMPX_LT_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x011>;
1978 defm V_CMPX_EQ_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x012>;
1979 defm V_CMPX_LE_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x013>;
1980 defm V_CMPX_GT_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x014>;
1981 defm V_CMPX_LG_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x015>;
1982 defm V_CMPX_GE_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x016>;
1983 defm V_CMPX_O_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x017>;
1984 defm V_CMPX_U_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x018>;
1985 defm V_CMPX_NGE_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x019>;
1986 defm V_CMPX_NLG_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01a>;
1987 defm V_CMPX_NGT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01b>;
1988 defm V_CMPX_NLE_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>;
1989 defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>;
1990 defm V_CMPX_NLT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>;
1991 defm V_CMPX_TRU_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>;
1992 defm V_CMP_F_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>;
1993 defm V_CMP_LT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x021>;
1994 defm V_CMP_EQ_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x022>;
1995 defm V_CMP_LE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x023>;
1996 defm V_CMP_GT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x024>;
1997 defm V_CMP_LG_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x025>;
1998 defm V_CMP_GE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x026>;
1999 defm V_CMP_O_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x027>;
2000 defm V_CMP_U_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x028>;
2001 defm V_CMP_NGE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x029>;
2002 defm V_CMP_NLG_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02a>;
2003 defm V_CMP_NGT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02b>;
2004 defm V_CMP_NLE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02c>;
2005 defm V_CMP_NEQ_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02d>;
2006 defm V_CMP_NLT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02e>;
2007 defm V_CMP_TRU_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02f>;
2008 defm V_CMPX_F_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x030>;
2009 defm V_CMPX_LT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x031>;
2010 defm V_CMPX_EQ_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x032>;
2011 defm V_CMPX_LE_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x033>;
2012 defm V_CMPX_GT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x034>;
2013 defm V_CMPX_LG_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x035>;
2014 defm V_CMPX_GE_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x036>;
2015 defm V_CMPX_O_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x037>;
2016 defm V_CMPX_U_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x038>;
2017 defm V_CMPX_NGE_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x039>;
2018 defm V_CMPX_NLG_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03a>;
2019 defm V_CMPX_NGT_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03b>;
2020 defm V_CMPX_NLE_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03c>;
2021 defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03d>;
2022 defm V_CMPX_NLT_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03e>;
2023 defm V_CMPX_TRU_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03f>;
2024 defm V_CMPS_F_F32     : VOPC_Real_gfx6_gfx7<0x040>;
2025 defm V_CMPS_LT_F32    : VOPC_Real_gfx6_gfx7<0x041>;
2026 defm V_CMPS_EQ_F32    : VOPC_Real_gfx6_gfx7<0x042>;
2027 defm V_CMPS_LE_F32    : VOPC_Real_gfx6_gfx7<0x043>;
2028 defm V_CMPS_GT_F32    : VOPC_Real_gfx6_gfx7<0x044>;
2029 defm V_CMPS_LG_F32    : VOPC_Real_gfx6_gfx7<0x045>;
2030 defm V_CMPS_GE_F32    : VOPC_Real_gfx6_gfx7<0x046>;
2031 defm V_CMPS_O_F32     : VOPC_Real_gfx6_gfx7<0x047>;
2032 defm V_CMPS_U_F32     : VOPC_Real_gfx6_gfx7<0x048>;
2033 defm V_CMPS_NGE_F32   : VOPC_Real_gfx6_gfx7<0x049>;
2034 defm V_CMPS_NLG_F32   : VOPC_Real_gfx6_gfx7<0x04a>;
2035 defm V_CMPS_NGT_F32   : VOPC_Real_gfx6_gfx7<0x04b>;
2036 defm V_CMPS_NLE_F32   : VOPC_Real_gfx6_gfx7<0x04c>;
2037 defm V_CMPS_NEQ_F32   : VOPC_Real_gfx6_gfx7<0x04d>;
2038 defm V_CMPS_NLT_F32   : VOPC_Real_gfx6_gfx7<0x04e>;
2039 defm V_CMPS_TRU_F32   : VOPC_Real_gfx6_gfx7<0x04f>;
2040 defm V_CMPSX_F_F32    : VOPCX_Real_gfx6_gfx7<0x050>;
2041 defm V_CMPSX_LT_F32   : VOPCX_Real_gfx6_gfx7<0x051>;
2042 defm V_CMPSX_EQ_F32   : VOPCX_Real_gfx6_gfx7<0x052>;
2043 defm V_CMPSX_LE_F32   : VOPCX_Real_gfx6_gfx7<0x053>;
2044 defm V_CMPSX_GT_F32   : VOPCX_Real_gfx6_gfx7<0x054>;
2045 defm V_CMPSX_LG_F32   : VOPCX_Real_gfx6_gfx7<0x055>;
2046 defm V_CMPSX_GE_F32   : VOPCX_Real_gfx6_gfx7<0x056>;
2047 defm V_CMPSX_O_F32    : VOPCX_Real_gfx6_gfx7<0x057>;
2048 defm V_CMPSX_U_F32    : VOPCX_Real_gfx6_gfx7<0x058>;
2049 defm V_CMPSX_NGE_F32  : VOPCX_Real_gfx6_gfx7<0x059>;
2050 defm V_CMPSX_NLG_F32  : VOPCX_Real_gfx6_gfx7<0x05a>;
2051 defm V_CMPSX_NGT_F32  : VOPCX_Real_gfx6_gfx7<0x05b>;
2052 defm V_CMPSX_NLE_F32  : VOPCX_Real_gfx6_gfx7<0x05c>;
2053 defm V_CMPSX_NEQ_F32  : VOPCX_Real_gfx6_gfx7<0x05d>;
2054 defm V_CMPSX_NLT_F32  : VOPCX_Real_gfx6_gfx7<0x05e>;
2055 defm V_CMPSX_TRU_F32  : VOPCX_Real_gfx6_gfx7<0x05f>;
2056 defm V_CMPS_F_F64     : VOPC_Real_gfx6_gfx7<0x060>;
2057 defm V_CMPS_LT_F64    : VOPC_Real_gfx6_gfx7<0x061>;
2058 defm V_CMPS_EQ_F64    : VOPC_Real_gfx6_gfx7<0x062>;
2059 defm V_CMPS_LE_F64    : VOPC_Real_gfx6_gfx7<0x063>;
2060 defm V_CMPS_GT_F64    : VOPC_Real_gfx6_gfx7<0x064>;
2061 defm V_CMPS_LG_F64    : VOPC_Real_gfx6_gfx7<0x065>;
2062 defm V_CMPS_GE_F64    : VOPC_Real_gfx6_gfx7<0x066>;
2063 defm V_CMPS_O_F64     : VOPC_Real_gfx6_gfx7<0x067>;
2064 defm V_CMPS_U_F64     : VOPC_Real_gfx6_gfx7<0x068>;
2065 defm V_CMPS_NGE_F64   : VOPC_Real_gfx6_gfx7<0x069>;
2066 defm V_CMPS_NLG_F64   : VOPC_Real_gfx6_gfx7<0x06a>;
2067 defm V_CMPS_NGT_F64   : VOPC_Real_gfx6_gfx7<0x06b>;
2068 defm V_CMPS_NLE_F64   : VOPC_Real_gfx6_gfx7<0x06c>;
2069 defm V_CMPS_NEQ_F64   : VOPC_Real_gfx6_gfx7<0x06d>;
2070 defm V_CMPS_NLT_F64   : VOPC_Real_gfx6_gfx7<0x06e>;
2071 defm V_CMPS_TRU_F64   : VOPC_Real_gfx6_gfx7<0x06f>;
2072 defm V_CMPSX_F_F64    : VOPCX_Real_gfx6_gfx7<0x070>;
2073 defm V_CMPSX_LT_F64   : VOPCX_Real_gfx6_gfx7<0x071>;
2074 defm V_CMPSX_EQ_F64   : VOPCX_Real_gfx6_gfx7<0x072>;
2075 defm V_CMPSX_LE_F64   : VOPCX_Real_gfx6_gfx7<0x073>;
2076 defm V_CMPSX_GT_F64   : VOPCX_Real_gfx6_gfx7<0x074>;
2077 defm V_CMPSX_LG_F64   : VOPCX_Real_gfx6_gfx7<0x075>;
2078 defm V_CMPSX_GE_F64   : VOPCX_Real_gfx6_gfx7<0x076>;
2079 defm V_CMPSX_O_F64    : VOPCX_Real_gfx6_gfx7<0x077>;
2080 defm V_CMPSX_U_F64    : VOPCX_Real_gfx6_gfx7<0x078>;
2081 defm V_CMPSX_NGE_F64  : VOPCX_Real_gfx6_gfx7<0x079>;
2082 defm V_CMPSX_NLG_F64  : VOPCX_Real_gfx6_gfx7<0x07a>;
2083 defm V_CMPSX_NGT_F64  : VOPCX_Real_gfx6_gfx7<0x07b>;
2084 defm V_CMPSX_NLE_F64  : VOPCX_Real_gfx6_gfx7<0x07c>;
2085 defm V_CMPSX_NEQ_F64  : VOPCX_Real_gfx6_gfx7<0x07d>;
2086 defm V_CMPSX_NLT_F64  : VOPCX_Real_gfx6_gfx7<0x07e>;
2087 defm V_CMPSX_TRU_F64  : VOPCX_Real_gfx6_gfx7<0x07f>;
2088 defm V_CMP_F_I32      : VOPC_Real_gfx6_gfx7_gfx10<0x080>;
2089 defm V_CMP_LT_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x081>;
2090 defm V_CMP_EQ_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x082>;
2091 defm V_CMP_LE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x083>;
2092 defm V_CMP_GT_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x084>;
2093 defm V_CMP_NE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x085>;
2094 defm V_CMP_GE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x086>;
2095 defm V_CMP_T_I32      : VOPC_Real_gfx6_gfx7_gfx10<0x087>;
2096 defm V_CMP_CLASS_F32  : VOPC_Real_gfx6_gfx7_gfx10<0x088>;
2097 defm V_CMPX_F_I32     : VOPCX_Real_gfx6_gfx7_gfx10<0x090>;
2098 defm V_CMPX_LT_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x091>;
2099 defm V_CMPX_EQ_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x092>;
2100 defm V_CMPX_LE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x093>;
2101 defm V_CMPX_GT_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x094>;
2102 defm V_CMPX_NE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x095>;
2103 defm V_CMPX_GE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x096>;
2104 defm V_CMPX_T_I32     : VOPCX_Real_gfx6_gfx7_gfx10<0x097>;
2105 defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x098>;
2106 defm V_CMP_F_I64      : VOPC_Real_gfx6_gfx7_gfx10<0x0a0>;
2107 defm V_CMP_LT_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a1>;
2108 defm V_CMP_EQ_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a2>;
2109 defm V_CMP_LE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a3>;
2110 defm V_CMP_GT_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a4>;
2111 defm V_CMP_NE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a5>;
2112 defm V_CMP_GE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a6>;
2113 defm V_CMP_T_I64      : VOPC_Real_gfx6_gfx7_gfx10<0x0a7>;
2114 defm V_CMP_CLASS_F64  : VOPC_Real_gfx6_gfx7_gfx10<0x0a8>;
2115 defm V_CMPX_F_I64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0b0>;
2116 defm V_CMPX_LT_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b1>;
2117 defm V_CMPX_EQ_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b2>;
2118 defm V_CMPX_LE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b3>;
2119 defm V_CMPX_GT_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b4>;
2120 defm V_CMPX_NE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b5>;
2121 defm V_CMPX_GE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b6>;
2122 defm V_CMPX_T_I64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0b7>;
2123 defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b8>;
2124 defm V_CMP_F_U32      : VOPC_Real_gfx6_gfx7_gfx10<0x0c0>;
2125 defm V_CMP_LT_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c1>;
2126 defm V_CMP_EQ_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c2>;
2127 defm V_CMP_LE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c3>;
2128 defm V_CMP_GT_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c4>;
2129 defm V_CMP_NE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c5>;
2130 defm V_CMP_GE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c6>;
2131 defm V_CMP_T_U32      : VOPC_Real_gfx6_gfx7_gfx10<0x0c7>;
2132 defm V_CMPX_F_U32     : VOPCX_Real_gfx6_gfx7_gfx10<0x0d0>;
2133 defm V_CMPX_LT_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d1>;
2134 defm V_CMPX_EQ_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d2>;
2135 defm V_CMPX_LE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d3>;
2136 defm V_CMPX_GT_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d4>;
2137 defm V_CMPX_NE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d5>;
2138 defm V_CMPX_GE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d6>;
2139 defm V_CMPX_T_U32     : VOPCX_Real_gfx6_gfx7_gfx10<0x0d7>;
2140 defm V_CMP_F_U64      : VOPC_Real_gfx6_gfx7_gfx10<0x0e0>;
2141 defm V_CMP_LT_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e1>;
2142 defm V_CMP_EQ_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e2>;
2143 defm V_CMP_LE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e3>;
2144 defm V_CMP_GT_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e4>;
2145 defm V_CMP_NE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e5>;
2146 defm V_CMP_GE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e6>;
2147 defm V_CMP_T_U64      : VOPC_Real_gfx6_gfx7_gfx10<0x0e7>;
2148 defm V_CMPX_F_U64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0f0>;
2149 defm V_CMPX_LT_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f1>;
2150 defm V_CMPX_EQ_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f2>;
2151 defm V_CMPX_LE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f3>;
2152 defm V_CMPX_GT_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f4>;
2153 defm V_CMPX_NE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f5>;
2154 defm V_CMPX_GE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f6>;
2155 defm V_CMPX_T_U64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>;
2156
2157 //===----------------------------------------------------------------------===//
2158 // GFX8, GFX9 (VI).
2159 //===----------------------------------------------------------------------===//
2160
2161 multiclass VOPC_Real_vi <bits<10> op> {
2162   let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
2163     def _e32_vi :
2164       VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
2165       VOPCe<op{7-0}>;
2166
2167     def _e64_vi :
2168       VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
2169       VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
2170       // Encoding used for VOPC instructions encoded as VOP3
2171       // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
2172       bits<8> sdst;
2173       let Inst{7-0} = sdst;
2174     }
2175   }
2176
2177   foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
2178   def _sdwa_vi :
2179     VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
2180     VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2181
2182   foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
2183   def _sdwa_gfx9 :
2184     VOP_SDWA9_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
2185     VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2186
2187   let AssemblerPredicate = isGFX8GFX9 in {
2188     defm : VOPCInstAliases<NAME, "vi">;
2189   }
2190 }
2191
2192 defm V_CMP_CLASS_F32  : VOPC_Real_vi <0x10>;
2193 defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>;
2194 defm V_CMP_CLASS_F64  : VOPC_Real_vi <0x12>;
2195 defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>;
2196 defm V_CMP_CLASS_F16  : VOPC_Real_vi <0x14>;
2197 defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>;
2198
2199 defm V_CMP_F_F16      : VOPC_Real_vi <0x20>;
2200 defm V_CMP_LT_F16     : VOPC_Real_vi <0x21>;
2201 defm V_CMP_EQ_F16     : VOPC_Real_vi <0x22>;
2202 defm V_CMP_LE_F16     : VOPC_Real_vi <0x23>;
2203 defm V_CMP_GT_F16     : VOPC_Real_vi <0x24>;
2204 defm V_CMP_LG_F16     : VOPC_Real_vi <0x25>;
2205 defm V_CMP_GE_F16     : VOPC_Real_vi <0x26>;
2206 defm V_CMP_O_F16      : VOPC_Real_vi <0x27>;
2207 defm V_CMP_U_F16      : VOPC_Real_vi <0x28>;
2208 defm V_CMP_NGE_F16    : VOPC_Real_vi <0x29>;
2209 defm V_CMP_NLG_F16    : VOPC_Real_vi <0x2a>;
2210 defm V_CMP_NGT_F16    : VOPC_Real_vi <0x2b>;
2211 defm V_CMP_NLE_F16    : VOPC_Real_vi <0x2c>;
2212 defm V_CMP_NEQ_F16    : VOPC_Real_vi <0x2d>;
2213 defm V_CMP_NLT_F16    : VOPC_Real_vi <0x2e>;
2214 defm V_CMP_TRU_F16    : VOPC_Real_vi <0x2f>;
2215
2216 defm V_CMPX_F_F16     : VOPC_Real_vi <0x30>;
2217 defm V_CMPX_LT_F16    : VOPC_Real_vi <0x31>;
2218 defm V_CMPX_EQ_F16    : VOPC_Real_vi <0x32>;
2219 defm V_CMPX_LE_F16    : VOPC_Real_vi <0x33>;
2220 defm V_CMPX_GT_F16    : VOPC_Real_vi <0x34>;
2221 defm V_CMPX_LG_F16    : VOPC_Real_vi <0x35>;
2222 defm V_CMPX_GE_F16    : VOPC_Real_vi <0x36>;
2223 defm V_CMPX_O_F16     : VOPC_Real_vi <0x37>;
2224 defm V_CMPX_U_F16     : VOPC_Real_vi <0x38>;
2225 defm V_CMPX_NGE_F16   : VOPC_Real_vi <0x39>;
2226 defm V_CMPX_NLG_F16   : VOPC_Real_vi <0x3a>;
2227 defm V_CMPX_NGT_F16   : VOPC_Real_vi <0x3b>;
2228 defm V_CMPX_NLE_F16   : VOPC_Real_vi <0x3c>;
2229 defm V_CMPX_NEQ_F16   : VOPC_Real_vi <0x3d>;
2230 defm V_CMPX_NLT_F16   : VOPC_Real_vi <0x3e>;
2231 defm V_CMPX_TRU_F16   : VOPC_Real_vi <0x3f>;
2232
2233 defm V_CMP_F_F32      : VOPC_Real_vi <0x40>;
2234 defm V_CMP_LT_F32     : VOPC_Real_vi <0x41>;
2235 defm V_CMP_EQ_F32     : VOPC_Real_vi <0x42>;
2236 defm V_CMP_LE_F32     : VOPC_Real_vi <0x43>;
2237 defm V_CMP_GT_F32     : VOPC_Real_vi <0x44>;
2238 defm V_CMP_LG_F32     : VOPC_Real_vi <0x45>;
2239 defm V_CMP_GE_F32     : VOPC_Real_vi <0x46>;
2240 defm V_CMP_O_F32      : VOPC_Real_vi <0x47>;
2241 defm V_CMP_U_F32      : VOPC_Real_vi <0x48>;
2242 defm V_CMP_NGE_F32    : VOPC_Real_vi <0x49>;
2243 defm V_CMP_NLG_F32    : VOPC_Real_vi <0x4a>;
2244 defm V_CMP_NGT_F32    : VOPC_Real_vi <0x4b>;
2245 defm V_CMP_NLE_F32    : VOPC_Real_vi <0x4c>;
2246 defm V_CMP_NEQ_F32    : VOPC_Real_vi <0x4d>;
2247 defm V_CMP_NLT_F32    : VOPC_Real_vi <0x4e>;
2248 defm V_CMP_TRU_F32    : VOPC_Real_vi <0x4f>;
2249
2250 defm V_CMPX_F_F32     : VOPC_Real_vi <0x50>;
2251 defm V_CMPX_LT_F32    : VOPC_Real_vi <0x51>;
2252 defm V_CMPX_EQ_F32    : VOPC_Real_vi <0x52>;
2253 defm V_CMPX_LE_F32    : VOPC_Real_vi <0x53>;
2254 defm V_CMPX_GT_F32    : VOPC_Real_vi <0x54>;
2255 defm V_CMPX_LG_F32    : VOPC_Real_vi <0x55>;
2256 defm V_CMPX_GE_F32    : VOPC_Real_vi <0x56>;
2257 defm V_CMPX_O_F32     : VOPC_Real_vi <0x57>;
2258 defm V_CMPX_U_F32     : VOPC_Real_vi <0x58>;
2259 defm V_CMPX_NGE_F32   : VOPC_Real_vi <0x59>;
2260 defm V_CMPX_NLG_F32   : VOPC_Real_vi <0x5a>;
2261 defm V_CMPX_NGT_F32   : VOPC_Real_vi <0x5b>;
2262 defm V_CMPX_NLE_F32   : VOPC_Real_vi <0x5c>;
2263 defm V_CMPX_NEQ_F32   : VOPC_Real_vi <0x5d>;
2264 defm V_CMPX_NLT_F32   : VOPC_Real_vi <0x5e>;
2265 defm V_CMPX_TRU_F32   : VOPC_Real_vi <0x5f>;
2266
2267 defm V_CMP_F_F64      : VOPC_Real_vi <0x60>;
2268 defm V_CMP_LT_F64     : VOPC_Real_vi <0x61>;
2269 defm V_CMP_EQ_F64     : VOPC_Real_vi <0x62>;
2270 defm V_CMP_LE_F64     : VOPC_Real_vi <0x63>;
2271 defm V_CMP_GT_F64     : VOPC_Real_vi <0x64>;
2272 defm V_CMP_LG_F64     : VOPC_Real_vi <0x65>;
2273 defm V_CMP_GE_F64     : VOPC_Real_vi <0x66>;
2274 defm V_CMP_O_F64      : VOPC_Real_vi <0x67>;
2275 defm V_CMP_U_F64      : VOPC_Real_vi <0x68>;
2276 defm V_CMP_NGE_F64    : VOPC_Real_vi <0x69>;
2277 defm V_CMP_NLG_F64    : VOPC_Real_vi <0x6a>;
2278 defm V_CMP_NGT_F64    : VOPC_Real_vi <0x6b>;
2279 defm V_CMP_NLE_F64    : VOPC_Real_vi <0x6c>;
2280 defm V_CMP_NEQ_F64    : VOPC_Real_vi <0x6d>;
2281 defm V_CMP_NLT_F64    : VOPC_Real_vi <0x6e>;
2282 defm V_CMP_TRU_F64    : VOPC_Real_vi <0x6f>;
2283
2284 defm V_CMPX_F_F64     : VOPC_Real_vi <0x70>;
2285 defm V_CMPX_LT_F64    : VOPC_Real_vi <0x71>;
2286 defm V_CMPX_EQ_F64    : VOPC_Real_vi <0x72>;
2287 defm V_CMPX_LE_F64    : VOPC_Real_vi <0x73>;
2288 defm V_CMPX_GT_F64    : VOPC_Real_vi <0x74>;
2289 defm V_CMPX_LG_F64    : VOPC_Real_vi <0x75>;
2290 defm V_CMPX_GE_F64    : VOPC_Real_vi <0x76>;
2291 defm V_CMPX_O_F64     : VOPC_Real_vi <0x77>;
2292 defm V_CMPX_U_F64     : VOPC_Real_vi <0x78>;
2293 defm V_CMPX_NGE_F64   : VOPC_Real_vi <0x79>;
2294 defm V_CMPX_NLG_F64   : VOPC_Real_vi <0x7a>;
2295 defm V_CMPX_NGT_F64   : VOPC_Real_vi <0x7b>;
2296 defm V_CMPX_NLE_F64   : VOPC_Real_vi <0x7c>;
2297 defm V_CMPX_NEQ_F64   : VOPC_Real_vi <0x7d>;
2298 defm V_CMPX_NLT_F64   : VOPC_Real_vi <0x7e>;
2299 defm V_CMPX_TRU_F64   : VOPC_Real_vi <0x7f>;
2300
2301 defm V_CMP_F_I16      : VOPC_Real_vi <0xa0>;
2302 defm V_CMP_LT_I16     : VOPC_Real_vi <0xa1>;
2303 defm V_CMP_EQ_I16     : VOPC_Real_vi <0xa2>;
2304 defm V_CMP_LE_I16     : VOPC_Real_vi <0xa3>;
2305 defm V_CMP_GT_I16     : VOPC_Real_vi <0xa4>;
2306 defm V_CMP_NE_I16     : VOPC_Real_vi <0xa5>;
2307 defm V_CMP_GE_I16     : VOPC_Real_vi <0xa6>;
2308 defm V_CMP_T_I16      : VOPC_Real_vi <0xa7>;
2309
2310 defm V_CMP_F_U16      : VOPC_Real_vi <0xa8>;
2311 defm V_CMP_LT_U16     : VOPC_Real_vi <0xa9>;
2312 defm V_CMP_EQ_U16     : VOPC_Real_vi <0xaa>;
2313 defm V_CMP_LE_U16     : VOPC_Real_vi <0xab>;
2314 defm V_CMP_GT_U16     : VOPC_Real_vi <0xac>;
2315 defm V_CMP_NE_U16     : VOPC_Real_vi <0xad>;
2316 defm V_CMP_GE_U16     : VOPC_Real_vi <0xae>;
2317 defm V_CMP_T_U16      : VOPC_Real_vi <0xaf>;
2318
2319 defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>;
2320 defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>;
2321 defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>;
2322 defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>;
2323 defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>;
2324 defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>;
2325 defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>;
2326 defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>;
2327
2328 defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>;
2329 defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>;
2330 defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>;
2331 defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>;
2332 defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>;
2333 defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>;
2334 defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>;
2335 defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>;
2336
2337 defm V_CMP_F_I32      : VOPC_Real_vi <0xc0>;
2338 defm V_CMP_LT_I32     : VOPC_Real_vi <0xc1>;
2339 defm V_CMP_EQ_I32     : VOPC_Real_vi <0xc2>;
2340 defm V_CMP_LE_I32     : VOPC_Real_vi <0xc3>;
2341 defm V_CMP_GT_I32     : VOPC_Real_vi <0xc4>;
2342 defm V_CMP_NE_I32     : VOPC_Real_vi <0xc5>;
2343 defm V_CMP_GE_I32     : VOPC_Real_vi <0xc6>;
2344 defm V_CMP_T_I32      : VOPC_Real_vi <0xc7>;
2345
2346 defm V_CMPX_F_I32     : VOPC_Real_vi <0xd0>;
2347 defm V_CMPX_LT_I32    : VOPC_Real_vi <0xd1>;
2348 defm V_CMPX_EQ_I32    : VOPC_Real_vi <0xd2>;
2349 defm V_CMPX_LE_I32    : VOPC_Real_vi <0xd3>;
2350 defm V_CMPX_GT_I32    : VOPC_Real_vi <0xd4>;
2351 defm V_CMPX_NE_I32    : VOPC_Real_vi <0xd5>;
2352 defm V_CMPX_GE_I32    : VOPC_Real_vi <0xd6>;
2353 defm V_CMPX_T_I32     : VOPC_Real_vi <0xd7>;
2354
2355 defm V_CMP_F_I64      : VOPC_Real_vi <0xe0>;
2356 defm V_CMP_LT_I64     : VOPC_Real_vi <0xe1>;
2357 defm V_CMP_EQ_I64     : VOPC_Real_vi <0xe2>;
2358 defm V_CMP_LE_I64     : VOPC_Real_vi <0xe3>;
2359 defm V_CMP_GT_I64     : VOPC_Real_vi <0xe4>;
2360 defm V_CMP_NE_I64     : VOPC_Real_vi <0xe5>;
2361 defm V_CMP_GE_I64     : VOPC_Real_vi <0xe6>;
2362 defm V_CMP_T_I64      : VOPC_Real_vi <0xe7>;
2363
2364 defm V_CMPX_F_I64     : VOPC_Real_vi <0xf0>;
2365 defm V_CMPX_LT_I64    : VOPC_Real_vi <0xf1>;
2366 defm V_CMPX_EQ_I64    : VOPC_Real_vi <0xf2>;
2367 defm V_CMPX_LE_I64    : VOPC_Real_vi <0xf3>;
2368 defm V_CMPX_GT_I64    : VOPC_Real_vi <0xf4>;
2369 defm V_CMPX_NE_I64    : VOPC_Real_vi <0xf5>;
2370 defm V_CMPX_GE_I64    : VOPC_Real_vi <0xf6>;
2371 defm V_CMPX_T_I64     : VOPC_Real_vi <0xf7>;
2372
2373 defm V_CMP_F_U32      : VOPC_Real_vi <0xc8>;
2374 defm V_CMP_LT_U32     : VOPC_Real_vi <0xc9>;
2375 defm V_CMP_EQ_U32     : VOPC_Real_vi <0xca>;
2376 defm V_CMP_LE_U32     : VOPC_Real_vi <0xcb>;
2377 defm V_CMP_GT_U32     : VOPC_Real_vi <0xcc>;
2378 defm V_CMP_NE_U32     : VOPC_Real_vi <0xcd>;
2379 defm V_CMP_GE_U32     : VOPC_Real_vi <0xce>;
2380 defm V_CMP_T_U32      : VOPC_Real_vi <0xcf>;
2381
2382 defm V_CMPX_F_U32     : VOPC_Real_vi <0xd8>;
2383 defm V_CMPX_LT_U32    : VOPC_Real_vi <0xd9>;
2384 defm V_CMPX_EQ_U32    : VOPC_Real_vi <0xda>;
2385 defm V_CMPX_LE_U32    : VOPC_Real_vi <0xdb>;
2386 defm V_CMPX_GT_U32    : VOPC_Real_vi <0xdc>;
2387 defm V_CMPX_NE_U32    : VOPC_Real_vi <0xdd>;
2388 defm V_CMPX_GE_U32    : VOPC_Real_vi <0xde>;
2389 defm V_CMPX_T_U32     : VOPC_Real_vi <0xdf>;
2390
2391 defm V_CMP_F_U64      : VOPC_Real_vi <0xe8>;
2392 defm V_CMP_LT_U64     : VOPC_Real_vi <0xe9>;
2393 defm V_CMP_EQ_U64     : VOPC_Real_vi <0xea>;
2394 defm V_CMP_LE_U64     : VOPC_Real_vi <0xeb>;
2395 defm V_CMP_GT_U64     : VOPC_Real_vi <0xec>;
2396 defm V_CMP_NE_U64     : VOPC_Real_vi <0xed>;
2397 defm V_CMP_GE_U64     : VOPC_Real_vi <0xee>;
2398 defm V_CMP_T_U64      : VOPC_Real_vi <0xef>;
2399
2400 defm V_CMPX_F_U64     : VOPC_Real_vi <0xf8>;
2401 defm V_CMPX_LT_U64    : VOPC_Real_vi <0xf9>;
2402 defm V_CMPX_EQ_U64    : VOPC_Real_vi <0xfa>;
2403 defm V_CMPX_LE_U64    : VOPC_Real_vi <0xfb>;
2404 defm V_CMPX_GT_U64    : VOPC_Real_vi <0xfc>;
2405 defm V_CMPX_NE_U64    : VOPC_Real_vi <0xfd>;
2406 defm V_CMPX_GE_U64    : VOPC_Real_vi <0xfe>;
2407 defm V_CMPX_T_U64     : VOPC_Real_vi <0xff>;