1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // The Cortex-A15 processor employs a tracking scheme in its register renaming
10 // in order to process each instruction's micro-ops speculatively and
11 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
12 // instructions to read and write 32-bit S-registers. Each S-register
13 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
15 // There are several instruction patterns which can be used to provide this
16 // capability which can provide higher performance than other, potentially more
17 // direct patterns, specifically around when one micro-op reads a D-register
18 // operand that has recently been written as one or more S-register results.
20 // This file defines a pre-regalloc pass which looks for SPR producers which
21 // are going to be used by a DPR (or QPR) consumers and creates the more
22 // optimized access pattern.
24 //===----------------------------------------------------------------------===//
27 #include "ARMBaseInstrInfo.h"
28 #include "ARMBaseRegisterInfo.h"
29 #include "ARMSubtarget.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/raw_ostream.h"
45 #define DEBUG_TYPE "a15-sd-optimizer"
48 struct A15SDOptimizer : public MachineFunctionPass {
50 A15SDOptimizer() : MachineFunctionPass(ID) {}
52 bool runOnMachineFunction(MachineFunction &Fn) override;
54 StringRef getPassName() const override { return "ARM A15 S->D optimizer"; }
57 const ARMBaseInstrInfo *TII;
58 const TargetRegisterInfo *TRI;
59 MachineRegisterInfo *MRI;
61 bool runOnInstruction(MachineInstr *MI);
64 // Instruction builder helpers
66 unsigned createDupLane(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator InsertBefore,
68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
71 unsigned createExtractSubreg(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator InsertBefore,
73 const DebugLoc &DL, unsigned DReg,
74 unsigned Lane, const TargetRegisterClass *TRC);
76 unsigned createVExt(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator InsertBefore,
78 const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
80 unsigned createRegSequence(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator InsertBefore,
82 const DebugLoc &DL, unsigned Reg1,
85 unsigned createInsertSubreg(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator InsertBefore,
87 const DebugLoc &DL, unsigned DReg,
88 unsigned Lane, unsigned ToInsert);
90 unsigned createImplicitDef(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator InsertBefore,
95 // Various property checkers
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
98 bool hasPartialWrite(MachineInstr *MI);
99 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
100 unsigned getDPRLaneFromSPR(unsigned SReg);
103 // Methods used for getting the definitions of partial registers
106 MachineInstr *elideCopies(MachineInstr *MI);
107 void elideCopiesAndPHIs(MachineInstr *MI,
108 SmallVectorImpl<MachineInstr*> &Outs);
111 // Pattern optimization methods
113 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
114 unsigned optimizeSDPattern(MachineInstr *MI);
115 unsigned getPrefSPRLane(unsigned SReg);
118 // Sanitizing method - used to make sure if don't leave dead code around.
120 void eraseInstrWithNoUses(MachineInstr *MI);
123 // A map used to track the changes done by this pass.
125 std::map<MachineInstr*, unsigned> Replacements;
126 std::set<MachineInstr *> DeadInstr;
128 char A15SDOptimizer::ID = 0;
129 } // end anonymous namespace
131 // Returns true if this is a use of a SPR register.
132 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
133 const TargetRegisterClass *TRC) {
136 Register Reg = MO.getReg();
138 if (Register::isVirtualRegister(Reg))
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
141 return TRC->contains(Reg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
147 if (DReg != ARM::NoRegister) return ARM::ssub_1;
151 // Get the subreg type that is most likely to be coalesced
152 // for an SPR register that will be used in VDUP32d pseudo.
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
154 if (!Register::isVirtualRegister(SReg))
155 return getDPRLaneFromSPR(SReg);
157 MachineInstr *MI = MRI->getVRegDef(SReg);
158 if (!MI) return ARM::ssub_0;
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
160 if (!MO) return ARM::ssub_0;
161 assert(MO->isReg() && "Non-register operand found!");
163 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
164 &ARM::SPRRegClass)) {
165 SReg = MI->getOperand(1).getReg();
168 if (Register::isVirtualRegister(SReg)) {
169 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
172 return getDPRLaneFromSPR(SReg);
175 // MI is known to be dead. Figure out what instructions
176 // are also made dead by this and mark them for removal.
177 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
178 SmallVector<MachineInstr *, 8> Front;
179 DeadInstr.insert(MI);
181 LLVM_DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
184 while (Front.size() != 0) {
188 // MI is already known to be dead. We need to see
189 // if other instructions can also be removed.
190 for (MachineOperand &MO : MI->operands()) {
191 if ((!MO.isReg()) || (!MO.isUse()))
193 Register Reg = MO.getReg();
194 if (!Register::isVirtualRegister(Reg))
196 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
201 MachineInstr *Def = Op->getParent();
203 // We don't need to do anything if we have already marked
204 // this instruction as being dead.
205 if (DeadInstr.find(Def) != DeadInstr.end())
208 // Check if all the uses of this instruction are marked as
209 // dead. If so, we can also mark this instruction as being
212 for (MachineOperand &MODef : Def->operands()) {
213 if ((!MODef.isReg()) || (!MODef.isDef()))
215 Register DefReg = MODef.getReg();
216 if (!Register::isVirtualRegister(DefReg)) {
220 for (MachineInstr &Use : MRI->use_instructions(Reg)) {
221 // We don't care about self references.
224 if (DeadInstr.find(&Use) == DeadInstr.end()) {
231 if (!IsDead) continue;
233 LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
234 DeadInstr.insert(Def);
239 // Creates the more optimized patterns and generally does all the code
240 // transformations in this pass.
241 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
243 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
246 if (MI->isInsertSubreg()) {
247 Register DPRReg = MI->getOperand(1).getReg();
248 Register SPRReg = MI->getOperand(2).getReg();
250 if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
251 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
252 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
254 if (DPRMI && SPRMI) {
255 // See if the first operand of this insert_subreg is IMPLICIT_DEF
256 MachineInstr *ECDef = elideCopies(DPRMI);
257 if (ECDef && ECDef->isImplicitDef()) {
258 // Another corner case - if we're inserting something that is purely
259 // a subreg copy of a DPR, just use that DPR.
261 MachineInstr *EC = elideCopies(SPRMI);
262 // Is it a subreg copy of ssub_0?
263 if (EC && EC->isCopy() &&
264 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
265 LLVM_DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
267 // Find the thing we're subreg copying out of - is it of the same
268 // regclass as DPRMI? (i.e. a DPR or QPR).
269 Register FullReg = SPRMI->getOperand(1).getReg();
270 const TargetRegisterClass *TRC =
271 MRI->getRegClass(MI->getOperand(1).getReg());
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
273 LLVM_DEBUG(dbgs() << "Subreg copy is compatible - returning ");
274 LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n");
275 eraseInstrWithNoUses(MI);
280 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
284 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
287 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
288 &ARM::SPRRegClass)) {
289 // See if all bar one of the operands are IMPLICIT_DEF and insert the
290 // optimizer pattern accordingly.
291 unsigned NumImplicit = 0, NumTotal = 0;
292 unsigned NonImplicitReg = ~0U;
294 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
295 if (!MI->getOperand(I).isReg())
298 Register OpReg = MI->getOperand(I).getReg();
300 if (!Register::isVirtualRegister(OpReg))
303 MachineInstr *Def = MRI->getVRegDef(OpReg);
306 if (Def->isImplicitDef())
309 NonImplicitReg = MI->getOperand(I).getReg();
312 if (NumImplicit == NumTotal - 1)
313 return optimizeAllLanesPattern(MI, NonImplicitReg);
315 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
318 llvm_unreachable("Unhandled update pattern!");
321 // Return true if this MachineInstr inserts a scalar (SPR) value into
322 // a D or Q register.
323 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
324 // The only way we can do a partial register update is through a COPY,
325 // INSERT_SUBREG or REG_SEQUENCE.
326 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
329 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
333 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
339 // Looks through full copies to get the instruction that defines the input
341 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
342 if (!MI->isFullCopy())
344 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
346 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
349 return elideCopies(Def);
352 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
353 // that can produce MI.
354 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
355 SmallVectorImpl<MachineInstr*> &Outs) {
356 // Looking through PHIs may create loops so we need to track what
357 // instructions we have visited before.
358 std::set<MachineInstr *> Reached;
359 SmallVector<MachineInstr *, 8> Front;
361 while (Front.size() != 0) {
365 // If we have already explored this MachineInstr, ignore it.
366 if (Reached.find(MI) != Reached.end())
370 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
371 Register Reg = MI->getOperand(I).getReg();
372 if (!Register::isVirtualRegister(Reg)) {
375 MachineInstr *NewMI = MRI->getVRegDef(Reg);
378 Front.push_back(NewMI);
380 } else if (MI->isFullCopy()) {
381 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
383 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
386 Front.push_back(NewMI);
388 LLVM_DEBUG(dbgs() << "Found partial copy" << *MI << "\n");
394 // Return the DPR virtual registers that are read by this machine instruction
396 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
397 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
399 return SmallVector<unsigned, 8>();
401 SmallVector<unsigned, 8> Defs;
402 for (MachineOperand &MO : MI->operands()) {
403 if (!MO.isReg() || !MO.isUse())
405 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
406 !usesRegClass(MO, &ARM::QPRRegClass) &&
407 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
410 Defs.push_back(MO.getReg());
415 // Creates a DPR register from an SPR one by using a VDUP.
416 unsigned A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
417 MachineBasicBlock::iterator InsertBefore,
418 const DebugLoc &DL, unsigned Reg,
419 unsigned Lane, bool QPR) {
421 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass);
422 BuildMI(MBB, InsertBefore, DL,
423 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
426 .add(predOps(ARMCC::AL));
431 // Creates a SPR register from a DPR by copying the value in lane 0.
432 unsigned A15SDOptimizer::createExtractSubreg(
433 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
434 const DebugLoc &DL, unsigned DReg, unsigned Lane,
435 const TargetRegisterClass *TRC) {
436 Register Out = MRI->createVirtualRegister(TRC);
440 TII->get(TargetOpcode::COPY), Out)
441 .addReg(DReg, 0, Lane);
446 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
447 unsigned A15SDOptimizer::createRegSequence(
448 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
449 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
450 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
454 TII->get(TargetOpcode::REG_SEQUENCE), Out)
458 .addImm(ARM::dsub_1);
462 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
463 // and merges them into one DPR register.
464 unsigned A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
465 MachineBasicBlock::iterator InsertBefore,
466 const DebugLoc &DL, unsigned Ssub0,
468 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
469 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
473 .add(predOps(ARMCC::AL));
477 unsigned A15SDOptimizer::createInsertSubreg(
478 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
479 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
480 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
484 TII->get(TargetOpcode::INSERT_SUBREG), Out)
493 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
494 MachineBasicBlock::iterator InsertBefore,
495 const DebugLoc &DL) {
496 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
500 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
504 // This function inserts instructions in order to optimize interactions between
505 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
506 // lanes, and the using VEXT instructions to recompose the result.
508 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
509 MachineBasicBlock::iterator InsertPt(MI);
510 DebugLoc DL = MI->getDebugLoc();
511 MachineBasicBlock &MBB = *MI->getParent();
515 // DPair has the same length as QPR and also has two DPRs as subreg.
516 // Treat DPair as QPR.
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
519 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
520 ARM::dsub_0, &ARM::DPRRegClass);
521 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
522 ARM::dsub_1, &ARM::DPRRegClass);
524 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
525 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
526 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
528 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
529 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
530 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
532 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
535 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
536 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
537 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
541 "Found unexpected regclass!");
543 unsigned PrefLane = getPrefSPRLane(Reg);
546 case ARM::ssub_0: Lane = 0; break;
547 case ARM::ssub_1: Lane = 1; break;
548 default: llvm_unreachable("Unknown preferred lane!");
551 // Treat DPair as QPR
552 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
553 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
555 Out = createImplicitDef(MBB, InsertPt, DL);
556 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
557 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
558 eraseInstrWithNoUses(MI);
563 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
564 // We look for instructions that write S registers that are then read as
565 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
566 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
567 // merge two SPR values to form a DPR register. In order avoid false
568 // positives we make sure that there is an SPR producer so we look past
569 // COPY and PHI nodes to find it.
571 // The best code pattern for when an SPR producer is going to be used by a
572 // DPR or QPR consumer depends on whether the other lanes of the
573 // corresponding DPR/QPR are currently defined.
575 // We can handle these efficiently, depending on the type of
576 // pseudo-instruction that is producing the pattern
578 // * COPY: * VDUP all lanes and merge the results together
581 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
582 // lane, and the other lane(s) of the DPR/QPR register
583 // that we are inserting in are undefined, use the
584 // original DPR/QPR value.
585 // * Otherwise, fall back on the same stategy as COPY.
587 // * REG_SEQUENCE: * If all except one of the input operands are
588 // IMPLICIT_DEFs, insert the VDUP pattern for just the
589 // defined input operand
590 // * Otherwise, fall back on the same stategy as COPY.
593 // First, get all the reads of D-registers done by this instruction.
594 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
595 bool Modified = false;
597 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
599 // Follow the def-use chain for this DPR through COPYs, and also through
600 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
601 // we can end up with multiple defs of this DPR.
603 SmallVector<MachineInstr *, 8> DefSrcs;
604 if (!Register::isVirtualRegister(*I))
606 MachineInstr *Def = MRI->getVRegDef(*I);
610 elideCopiesAndPHIs(Def, DefSrcs);
612 for (MachineInstr *MI : DefSrcs) {
613 // If we've already analyzed and replaced this operand, don't do
615 if (Replacements.find(MI) != Replacements.end())
618 // Now, work out if the instruction causes a SPR->DPR dependency.
619 if (!hasPartialWrite(MI))
622 // Collect all the uses of this MI's DPR def for updating later.
623 SmallVector<MachineOperand*, 8> Uses;
624 Register DPRDefReg = MI->getOperand(0).getReg();
625 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
626 E = MRI->use_end(); I != E; ++I)
629 // We can optimize this.
630 unsigned NewReg = optimizeSDPattern(MI);
634 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
635 E = Uses.end(); I != E; ++I) {
636 // Make sure to constrain the register class of the new register to
637 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
638 // reference into a plain DPR, and that will end poorly. NewReg is
639 // always virtual here, so there will always be a matching subclass
641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
643 LLVM_DEBUG(dbgs() << "Replacing operand " << **I << " with "
644 << printReg(NewReg) << "\n");
645 (*I)->substVirtReg(NewReg, 0, *TRI);
648 Replacements[MI] = NewReg;
654 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
655 if (skipFunction(Fn.getFunction()))
658 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
659 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
660 // enabled when NEON is available.
661 if (!(STI.useSplatVFPToNeon() && STI.hasNEON()))
664 TII = STI.getInstrInfo();
665 TRI = STI.getRegisterInfo();
666 MRI = &Fn.getRegInfo();
667 bool Modified = false;
669 LLVM_DEBUG(dbgs() << "Running on function " << Fn.getName() << "\n");
672 Replacements.clear();
674 for (MachineBasicBlock &MBB : Fn) {
675 for (MachineInstr &MI : MBB) {
676 Modified |= runOnInstruction(&MI);
680 for (MachineInstr *MI : DeadInstr) {
681 MI->eraseFromParent();
687 FunctionPass *llvm::createA15SDOptimizerPass() {
688 return new A15SDOptimizer();