contrib/llvm-project/llvm/lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // ARM Subtarget state.
  20 //
  21
  22 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  23                                              "true", "Thumb mode">;
  24
  25 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  26                                              "true", "Use software floating "
  27                                              "point features.">;
  28
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget features.
  32 //
  33
  34 // Floating Point, HW Division and Neon Support
  35
  36 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
  37 // version).
  38 def FeatureFPRegs         : SubtargetFeature<"fpregs", "HasFPRegs", "true",
  39                                              "Enable FP registers">;
  40
  41 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
  42 // extension) and MVE (even in the integer-only version).
  43 def FeatureFPRegs16       : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",
  44                                              "Enable 16-bit FP registers",
  45                                              [FeatureFPRegs]>;
  46
  47 def FeatureFPRegs64       : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",
  48                                              "Enable 64-bit FP registers",
  49                                              [FeatureFPRegs]>;
  50
  51 def FeatureFP64           : SubtargetFeature<"fp64", "HasFP64", "true",
  52                                              "Floating point unit supports "
  53                                              "double precision",
  54                                              [FeatureFPRegs64]>;
  55
  56 def FeatureD32            : SubtargetFeature<"d32", "HasD32", "true",
  57                                              "Extend FP to 32 double registers">;
  58
  59 multiclass VFPver<string name, string query, string description,
  60                   list<SubtargetFeature> prev,
  61                   list<SubtargetFeature> otherimplies,
  62                   list<SubtargetFeature> vfp2prev = []> {
  63   def _D16_SP: SubtargetFeature<
  64     name#"d16sp", query#"D16SP", "true",
  65     description#" with only 16 d-registers and no double precision",
  66     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
  67       !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
  68       otherimplies>;
  69   def _SP: SubtargetFeature<
  70     name#"sp", query#"SP", "true",
  71     description#" with no double precision",
  72     !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #
  73       otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  74   def _D16: SubtargetFeature<
  75     name#"d16", query#"D16", "true",
  76     description#" with only 16 d-registers",
  77     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
  78       vfp2prev #
  79       otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  80   def "": SubtargetFeature<
  81     name, query, "true", description,
  82     prev # otherimplies # [
  83         !cast<SubtargetFeature>(NAME # "_D16"),
  84         !cast<SubtargetFeature>(NAME # "_SP")]>;
  85 }
  86
  87 def FeatureVFP2_SP        : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
  88                                              "Enable VFP2 instructions with "
  89                                              "no double precision",
  90                                              [FeatureFPRegs]>;
  91
  92 def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  93                                              "Enable VFP2 instructions",
  94                                              [FeatureFP64, FeatureVFP2_SP]>;
  95
  96 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
  97                          [], [], [FeatureVFP2]>;
  98
  99 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
 100                                              "Enable NEON instructions",
 101                                              [FeatureVFP3]>;
 102
 103 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
 104                                              "Enable half-precision "
 105                                              "floating point">;
 106
 107 defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
 108                          [FeatureVFP3], [FeatureFP16]>;
 109
 110 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
 111                          [FeatureVFP4], []>;
 112
 113 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
 114                                              "Enable full half-precision "
 115                                              "floating point",
 116                                              [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>;
 117
 118 def FeatureFP16FML        : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
 119                                              "Enable full half-precision "
 120                                              "floating point fml instructions",
 121                                              [FeatureFullFP16]>;
 122
 123 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
 124                                              "HasHardwareDivideInThumb", "true",
 125                                              "Enable divide instructions in Thumb">;
 126
 127 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
 128                                              "HasHardwareDivideInARM", "true",
 129                                              "Enable divide instructions in ARM mode">;
 130
 131 // Atomic Support
 132 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
 133                                              "Has data barrier (dmb/dsb) instructions">;
 134
 135 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
 136                                              "Has v7 clrex instruction">;
 137
 138 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
 139                                    "Has full data barrier (dfb) instruction">;
 140
 141 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
 142                                              "HasAcquireRelease", "true",
 143                                              "Has v8 acquire/release (lda/ldaex "
 144                                              " etc) instructions">;
 145
 146
 147 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
 148                                              "FP compare + branch is slow">;
 149
 150 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
 151                                              "Enable support for Performance "
 152                                              "Monitor extensions">;
 153
 154
 155 // TrustZone Security Extensions
 156 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 157                                              "Enable support for TrustZone "
 158                                              "security extensions">;
 159
 160 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 161                                              "Enable support for ARMv8-M "
 162                                              "Security Extensions">;
 163
 164 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 165                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 166
 167 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 168                                              "Enable AES support", [FeatureNEON]>;
 169
 170 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 171                                              "Enable support for "
 172                                              "Cryptography extensions",
 173                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 174
 175 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 176                                              "Enable support for CRC instructions">;
 177
 178 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 179                                              "Enable support for dot product instructions",
 180                                              [FeatureNEON]>;
 181
 182 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 183 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 184                                              "Enable Reliability, Availability "
 185                                              "and Serviceability extensions">;
 186
 187 // Fast computation of non-negative address offsets
 188 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 189                                              "Enable fast computation of "
 190                                              "positive address offsets">;
 191
 192 // Fast execution of AES crypto operations
 193 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 194                                              "CPU fuses AES crypto operations">;
 195
 196 // Fast execution of bottom and top halves of literal generation
 197 def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
 198                                              "CPU fuses literal generation operations">;
 199
 200 // The way of reading thread pointer
 201 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 202                                       "Reading thread pointer from register">;
 203
 204 // Cyclone can zero VFP registers in 0 cycles.
 205 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 206                                              "Has zero-cycle zeroing instructions">;
 207
 208 // Whether it is profitable to unpredicate certain instructions during if-conversion
 209 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 210                                               "IsProfitableToUnpredicate", "true",
 211                                               "Is profitable to unpredicate">;
 212
 213 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 214 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 215                                              "HasSlowVGETLNi32", "true",
 216                                              "Has slow VGETLNi32 - prefer VMOV">;
 217
 218 // Some targets (e.g. Swift) have microcoded VDUP32.
 219 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 220                                              "true",
 221                                              "Has slow VDUP32 - prefer VMOV">;
 222
 223 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 224 // for scalar FP, as this allows more effective execution domain optimization.
 225 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 226                                              "true", "Prefer VMOVSR">;
 227
 228 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 229 // than ISH
 230 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 231                                                "true", "Prefer ISHST barriers">;
 232
 233 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 234 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 235                                              "true",
 236                                              "Has muxed AGU and NEON/FPU">;
 237
 238 // Whether VLDM/VSTM starting with odd register number need more microops
 239 // than single VLDRS
 240 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 241                                               "true", "VLDM/VSTM starting "
 242                                               "with an odd register is slow">;
 243
 244 // Some targets have a renaming dependency when loading into D subregisters.
 245 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 246                                               "SlowLoadDSubregister", "true",
 247                                               "Loading into D subregs is slow">;
 248
 249 def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
 250                                                "UseWideStrideVFP", "true",
 251                                                "Use a wide stride when allocating VFP registers">;
 252
 253 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 254 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 255                                              "DontWidenVMOVS", "true",
 256                                              "Don't widen VMOVS to VMOVD">;
 257
 258 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
 259 // VFP register widths.
 260 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
 261                                              "SplatVFPToNeon", "true",
 262                                              "Splat register from VFP to NEON",
 263                                              [FeatureDontWidenVMOVS]>;
 264
 265 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 266 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 267                                              "ExpandMLx", "true",
 268                                              "Expand VFP/NEON MLA/MLS instructions">;
 269
 270 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 271 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 272                                              "true", "Has VMLx hazards">;
 273
 274 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 275 // VFP to NEON, as an execution domain optimization.
 276 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 277                                              "UseNEONForFPMovs", "true",
 278                                              "Convert VMOVSR, VMOVRS, "
 279                                              "VMOVS to NEON">;
 280
 281 // Some processors benefit from using NEON instructions for scalar
 282 // single-precision FP operations. This affects instruction selection and should
 283 // only be enabled if the handling of denormals is not important.
 284 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 285                                              "UseNEONForSinglePrecisionFP",
 286                                              "true",
 287                                              "Use NEON for single precision FP">;
 288
 289 // On some processors, VLDn instructions that access unaligned data take one
 290 // extra cycle. Take that into account when computing operand latencies.
 291 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 292                                              "true",
 293                                              "Check for VLDn unaligned access">;
 294
 295 // Some processors have a nonpipelined VFP coprocessor.
 296 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 297                                               "NonpipelinedVFP", "true",
 298                                               "VFP instructions are not pipelined">;
 299
 300 // Some processors have FP multiply-accumulate instructions that don't
 301 // play nicely with other VFP / NEON instructions, and it's generally better
 302 // to just not use them.
 303 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 304                                              "Disable VFP / NEON MAC instructions">;
 305
 306 // VFPv4 added VFMA instructions that can similar be fast or slow.
 307 def FeatureHasSlowFPVFMx  : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true",
 308                                              "Disable VFP / NEON FMA instructions">;
 309
 310 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 311 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 312                                              "HasVMLxForwarding", "true",
 313                                              "Has multiplier accumulator forwarding">;
 314
 315 // Disable 32-bit to 16-bit narrowing for experimentation.
 316 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 317                                              "Prefer 32-bit Thumb instrs">;
 318
 319 def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
 320                                               "Prefer 32-bit alignment for loops">;
 321
 322 def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1",
 323                         "Model MVE instructions as a 1 beat per tick architecture">;
 324
 325 def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2",
 326                         "Model MVE instructions as a 2 beats per tick architecture">;
 327
 328 def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4",
 329                         "Model MVE instructions as a 4 beats per tick architecture">;
 330
 331 /// Some instructions update CPSR partially, which can add false dependency for
 332 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 333 /// mapped to a separate physical register. Avoid partial CPSR update for these
 334 /// processors.
 335 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 336                                                "AvoidCPSRPartialUpdate", "true",
 337                                  "Avoid CPSR partial update for OOO execution">;
 338
 339 /// Disable +1 predication cost for instructions updating CPSR.
 340 /// Enabled for Cortex-A57.
 341 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 342                                                   "CheapPredicableCPSRDef",
 343                                                   "true",
 344                   "Disable +1 predication cost for instructions updating CPSR">;
 345
 346 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 347                                              "AvoidMOVsShifterOperand", "true",
 348                                              "Avoid movs instructions with "
 349                                              "shifter operand">;
 350
 351 // Some processors perform return stack prediction. CodeGen should avoid issue
 352 // "normal" call instructions to callees which do not return.
 353 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 354                                               "HasRetAddrStack", "true",
 355                                               "Has return address stack">;
 356
 357 // Some processors have no branch predictor, which changes the expected cost of
 358 // taking a branch which affects the choice of whether to use predicated
 359 // instructions.
 360 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 361                                                    "HasBranchPredictor", "false",
 362                                                    "Has no branch predictor">;
 363
 364 /// DSP extension.
 365 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 366                                              "Supports DSP instructions in "
 367                                              "ARM and/or Thumb2">;
 368
 369 // Multiprocessing extension.
 370 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 371                                         "Supports Multiprocessing extension">;
 372
 373 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 374 def FeatureVirtualization : SubtargetFeature<"virtualization",
 375                                              "HasVirtualization", "true",
 376                                              "Supports Virtualization extension",
 377                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 378
 379 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 380 // See ARMInstrInfo.td for details.
 381 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 382                                              "NaCl trap">;
 383
 384 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 385                                              "StrictAlign", "true",
 386                                              "Disallow all unaligned memory "
 387                                              "access">;
 388
 389 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 390                                              "Generate calls via indirect call "
 391                                              "instructions">;
 392
 393 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 394                                              "GenExecuteOnly", "true",
 395                                              "Enable the generation of "
 396                                              "execute only code.">;
 397
 398 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 399                                              "Reserve R9, making it unavailable"
 400                                              " as GPR">;
 401
 402 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 403                                              "Don't use movt/movw pairs for "
 404                                              "32-bit imms">;
 405
 406 def FeatureNoNegativeImmediates
 407                           : SubtargetFeature<"no-neg-immediates",
 408                                              "NegativeImmediates", "false",
 409                                              "Convert immediates and instructions "
 410                                              "to their negated or complemented "
 411                                              "equivalent when the immediate does "
 412                                              "not fit in the encoding.">;
 413
 414 // Use the MachineScheduler for instruction scheduling for the subtarget.
 415 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 416                                         "Use the MachineScheduler">;
 417
 418 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 419     "DisablePostRAScheduler", "true",
 420     "Don't schedule again after register allocation">;
 421
 422 // Armv8.5-A extensions
 423
 424 def FeatureSB       : SubtargetFeature<"sb", "HasSB", "true",
 425   "Enable v8.5a Speculation Barrier" >;
 426
 427 // Armv8.1-M extensions
 428
 429 def FeatureLOB            : SubtargetFeature<"lob", "HasLOB", "true",
 430                                              "Enable Low Overhead Branch "
 431                                              "extensions">;
 432
 433 //===----------------------------------------------------------------------===//
 434 // ARM architecture class
 435 //
 436
 437 // A-series ISA
 438 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 439                                      "Is application profile ('A' series)">;
 440
 441 // R-series ISA
 442 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 443                                      "Is realtime profile ('R' series)">;
 444
 445 // M-series ISA
 446 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 447                                      "Is microcontroller profile ('M' series)">;
 448
 449
 450 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 451                                      "Enable Thumb2 instructions">;
 452
 453 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 454                                      "Does not support ARM mode execution">;
 455
 456 //===----------------------------------------------------------------------===//
 457 // ARM ISAa.
 458 //
 459
 460 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 461                                    "Support ARM v4T instructions">;
 462
 463 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 464                                    "Support ARM v5T instructions",
 465                                    [HasV4TOps]>;
 466
 467 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 468                                    "Support ARM v5TE, v5TEj, and "
 469                                    "v5TExp instructions",
 470                                    [HasV5TOps]>;
 471
 472 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 473                                    "Support ARM v6 instructions",
 474                                    [HasV5TEOps]>;
 475
 476 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 477                                    "Support ARM v6M instructions",
 478                                    [HasV6Ops]>;
 479
 480 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 481                                          "Support ARM v8M Baseline instructions",
 482                                          [HasV6MOps]>;
 483
 484 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 485                                    "Support ARM v6k instructions",
 486                                    [HasV6Ops]>;
 487
 488 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 489                                    "Support ARM v6t2 instructions",
 490                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 491
 492 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 493                                    "Support ARM v7 instructions",
 494                                    [HasV6T2Ops, FeaturePerfMon,
 495                                     FeatureV7Clrex]>;
 496
 497 def HasV8MMainlineOps :
 498                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 499                                    "Support ARM v8M Mainline instructions",
 500                                    [HasV7Ops]>;
 501
 502 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 503                                    "Support ARM v8 instructions",
 504                                    [HasV7Ops, FeatureAcquireRelease]>;
 505
 506 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 507                                    "Support ARM v8.1a instructions",
 508                                    [HasV8Ops]>;
 509
 510 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 511                                    "Support ARM v8.2a instructions",
 512                                    [HasV8_1aOps]>;
 513
 514 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 515                                    "Support ARM v8.3a instructions",
 516                                    [HasV8_2aOps]>;
 517
 518 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 519                                    "Support ARM v8.4a instructions",
 520                                    [HasV8_3aOps, FeatureDotProd]>;
 521
 522 def HasV8_5aOps   : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
 523                                    "Support ARM v8.5a instructions",
 524                                    [HasV8_4aOps, FeatureSB]>;
 525
 526 def HasV8_1MMainlineOps : SubtargetFeature<
 527                "v8.1m.main", "HasV8_1MMainlineOps", "true",
 528                "Support ARM v8-1M Mainline instructions",
 529                [HasV8MMainlineOps]>;
 530 def HasMVEIntegerOps : SubtargetFeature<
 531                "mve", "HasMVEIntegerOps", "true",
 532                "Support M-Class Vector Extension with integer ops",
 533                [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;
 534 def HasMVEFloatOps : SubtargetFeature<
 535                "mve.fp", "HasMVEFloatOps", "true",
 536                "Support M-Class Vector Extension with integer and floating ops",
 537                [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;
 538
 539 //===----------------------------------------------------------------------===//
 540 // ARM Processor subtarget features.
 541 //
 542
 543 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 544                                    "Cortex-A5 ARM processors", []>;
 545 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 546                                    "Cortex-A7 ARM processors", []>;
 547 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 548                                    "Cortex-A8 ARM processors", []>;
 549 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 550                                    "Cortex-A9 ARM processors", []>;
 551 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 552                                    "Cortex-A12 ARM processors", []>;
 553 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 554                                    "Cortex-A15 ARM processors", []>;
 555 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 556                                    "Cortex-A17 ARM processors", []>;
 557 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 558                                    "Cortex-A32 ARM processors", []>;
 559 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 560                                    "Cortex-A35 ARM processors", []>;
 561 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 562                                    "Cortex-A53 ARM processors", []>;
 563 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 564                                    "Cortex-A55 ARM processors", []>;
 565 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 566                                    "Cortex-A57 ARM processors", []>;
 567 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 568                                    "Cortex-A72 ARM processors", []>;
 569 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 570                                    "Cortex-A73 ARM processors", []>;
 571 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 572                                    "Cortex-A75 ARM processors", []>;
 573 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 574                                    "Cortex-A76 ARM processors", []>;
 575
 576 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 577                                    "Qualcomm Krait processors", []>;
 578 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 579                                    "Qualcomm Kryo processors", []>;
 580 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 581                                    "Swift ARM processors", []>;
 582
 583 def ProcExynos  : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
 584                                    "Samsung Exynos processors",
 585                                    [FeatureZCZeroing,
 586                                     FeatureUseWideStrideVFP,
 587                                     FeatureSplatVFPToNeon,
 588                                     FeatureSlowVGETLNi32,
 589                                     FeatureSlowVDUP32,
 590                                     FeatureSlowFPBrcc,
 591                                     FeatureProfUnpredicate,
 592                                     FeatureHWDivThumb,
 593                                     FeatureHWDivARM,
 594                                     FeatureHasSlowFPVMLx,
 595                                     FeatureHasSlowFPVFMx,
 596                                     FeatureHasRetAddrStack,
 597                                     FeatureFuseLiterals,
 598                                     FeatureFuseAES,
 599                                     FeatureExpandMLx,
 600                                     FeatureCrypto,
 601                                     FeatureCRC]>;
 602
 603 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 604                                    "Cortex-R4 ARM processors", []>;
 605 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 606                                    "Cortex-R5 ARM processors", []>;
 607 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 608                                    "Cortex-R7 ARM processors", []>;
 609 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 610                                    "Cortex-R52 ARM processors", []>;
 611
 612 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 613                                    "Cortex-M3 ARM processors", []>;
 614
 615
 616 //===----------------------------------------------------------------------===//
 617 // ARM Helper classes.
 618 //
 619
 620 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 621   : SubtargetFeature<fname, "ARMArch", aname,
 622                      !strconcat(aname, " architecture"), features>;
 623
 624 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 625   : Processor<Name, NoItineraries, Features>;
 626
 627
 628 //===----------------------------------------------------------------------===//
 629 // ARM architectures
 630 //
 631
 632 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 633
 634 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 635
 636 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 637
 638 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 639
 640 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 641
 642 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 643
 644 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 645
 646 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 647
 648 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 649
 650 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 651                                                        FeatureDSP]>;
 652
 653 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 654                                                        FeatureDSP]>;
 655
 656 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 657
 658 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 659                                                        FeatureTrustZone]>;
 660
 661 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 662                                                        FeatureNoARM,
 663                                                        ModeThumb,
 664                                                        FeatureDB,
 665                                                        FeatureMClass,
 666                                                        FeatureStrictAlign]>;
 667
 668 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 669                                                        FeatureNoARM,
 670                                                        ModeThumb,
 671                                                        FeatureDB,
 672                                                        FeatureMClass,
 673                                                        FeatureStrictAlign]>;
 674
 675 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 676                                                        FeatureNEON,
 677                                                        FeatureDB,
 678                                                        FeatureDSP,
 679                                                        FeatureAClass]>;
 680
 681 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 682                                                        FeatureNEON,
 683                                                        FeatureDB,
 684                                                        FeatureDSP,
 685                                                        FeatureTrustZone,
 686                                                        FeatureMP,
 687                                                        FeatureVirtualization,
 688                                                        FeatureAClass]>;
 689
 690 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 691                                                        FeatureDB,
 692                                                        FeatureDSP,
 693                                                        FeatureHWDivThumb,
 694                                                        FeatureRClass]>;
 695
 696 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 697                                                        FeatureThumb2,
 698                                                        FeatureNoARM,
 699                                                        ModeThumb,
 700                                                        FeatureDB,
 701                                                        FeatureHWDivThumb,
 702                                                        FeatureMClass]>;
 703
 704 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 705                                                        FeatureThumb2,
 706                                                        FeatureNoARM,
 707                                                        ModeThumb,
 708                                                        FeatureDB,
 709                                                        FeatureHWDivThumb,
 710                                                        FeatureMClass,
 711                                                        FeatureDSP]>;
 712
 713 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 714                                                        FeatureAClass,
 715                                                        FeatureDB,
 716                                                        FeatureFPARMv8,
 717                                                        FeatureNEON,
 718                                                        FeatureDSP,
 719                                                        FeatureTrustZone,
 720                                                        FeatureMP,
 721                                                        FeatureVirtualization,
 722                                                        FeatureCrypto,
 723                                                        FeatureCRC]>;
 724
 725 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 726                                                        FeatureAClass,
 727                                                        FeatureDB,
 728                                                        FeatureFPARMv8,
 729                                                        FeatureNEON,
 730                                                        FeatureDSP,
 731                                                        FeatureTrustZone,
 732                                                        FeatureMP,
 733                                                        FeatureVirtualization,
 734                                                        FeatureCrypto,
 735                                                        FeatureCRC]>;
 736
 737 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 738                                                        FeatureAClass,
 739                                                        FeatureDB,
 740                                                        FeatureFPARMv8,
 741                                                        FeatureNEON,
 742                                                        FeatureDSP,
 743                                                        FeatureTrustZone,
 744                                                        FeatureMP,
 745                                                        FeatureVirtualization,
 746                                                        FeatureCrypto,
 747                                                        FeatureCRC,
 748                                                        FeatureRAS]>;
 749
 750 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 751                                                        FeatureAClass,
 752                                                        FeatureDB,
 753                                                        FeatureFPARMv8,
 754                                                        FeatureNEON,
 755                                                        FeatureDSP,
 756                                                        FeatureTrustZone,
 757                                                        FeatureMP,
 758                                                        FeatureVirtualization,
 759                                                        FeatureCrypto,
 760                                                        FeatureCRC,
 761                                                        FeatureRAS]>;
 762
 763 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 764                                                        FeatureAClass,
 765                                                        FeatureDB,
 766                                                        FeatureFPARMv8,
 767                                                        FeatureNEON,
 768                                                        FeatureDSP,
 769                                                        FeatureTrustZone,
 770                                                        FeatureMP,
 771                                                        FeatureVirtualization,
 772                                                        FeatureCrypto,
 773                                                        FeatureCRC,
 774                                                        FeatureRAS,
 775                                                        FeatureDotProd]>;
 776
 777 def ARMv85a   : Architecture<"armv8.5-a", "ARMv85a",  [HasV8_5aOps,
 778                                                        FeatureAClass,
 779                                                        FeatureDB,
 780                                                        FeatureFPARMv8,
 781                                                        FeatureNEON,
 782                                                        FeatureDSP,
 783                                                        FeatureTrustZone,
 784                                                        FeatureMP,
 785                                                        FeatureVirtualization,
 786                                                        FeatureCrypto,
 787                                                        FeatureCRC,
 788                                                        FeatureRAS,
 789                                                        FeatureDotProd]>;
 790
 791 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 792                                                        FeatureRClass,
 793                                                        FeatureDB,
 794                                                        FeatureDFB,
 795                                                        FeatureDSP,
 796                                                        FeatureCRC,
 797                                                        FeatureMP,
 798                                                        FeatureVirtualization,
 799                                                        FeatureFPARMv8,
 800                                                        FeatureNEON]>;
 801
 802 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 803                                                       [HasV8MBaselineOps,
 804                                                        FeatureNoARM,
 805                                                        ModeThumb,
 806                                                        FeatureDB,
 807                                                        FeatureHWDivThumb,
 808                                                        FeatureV7Clrex,
 809                                                        Feature8MSecExt,
 810                                                        FeatureAcquireRelease,
 811                                                        FeatureMClass,
 812                                                        FeatureStrictAlign]>;
 813
 814 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 815                                                       [HasV8MMainlineOps,
 816                                                        FeatureNoARM,
 817                                                        ModeThumb,
 818                                                        FeatureDB,
 819                                                        FeatureHWDivThumb,
 820                                                        Feature8MSecExt,
 821                                                        FeatureAcquireRelease,
 822                                                        FeatureMClass]>;
 823
 824 def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline",
 825                                                       [HasV8_1MMainlineOps,
 826                                                        FeatureNoARM,
 827                                                        ModeThumb,
 828                                                        FeatureDB,
 829                                                        FeatureHWDivThumb,
 830                                                        Feature8MSecExt,
 831                                                        FeatureAcquireRelease,
 832                                                        FeatureMClass,
 833                                                        FeatureRAS,
 834                                                        FeatureLOB]>;
 835
 836 // Aliases
 837 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 838 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 839 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 840 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 841 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 842 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 843
 844
 845 //===----------------------------------------------------------------------===//
 846 // ARM schedules.
 847 //===----------------------------------------------------------------------===//
 848 //
 849 include "ARMPredicates.td"
 850 include "ARMSchedule.td"
 851
 852 //===----------------------------------------------------------------------===//
 853 // ARM processors
 854 //
 855
 856 // Dummy CPU, used to target architectures
 857 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 858
 859 // FIXME: Several processors below are not using their own scheduler
 860 // model, but one of similar/previous processor. These should be fixed.
 861
 862 def : ProcNoItin<"arm8",                                [ARMv4]>;
 863 def : ProcNoItin<"arm810",                              [ARMv4]>;
 864 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 865 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 866 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 867 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 868
 869 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 870 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 871 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 872 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 873 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 874 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 875 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 876 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 877 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 878 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 879 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 880
 881 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 882 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 883
 884 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 885 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 886 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 887 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 888 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 889 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 890 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 891 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 892 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 893 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 894
 895 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 896 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 897                                                          FeatureVFP2,
 898                                                          FeatureHasSlowFPVMLx]>;
 899
 900 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 901 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 902 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 903 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 904
 905 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 906 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 907 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 908                                                          FeatureVFP2,
 909                                                          FeatureHasSlowFPVMLx]>;
 910
 911 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 912 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 913                                                          FeatureVFP2,
 914                                                          FeatureHasSlowFPVMLx]>;
 915
 916 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 917 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 918                                                          FeatureVFP2,
 919                                                          FeatureHasSlowFPVMLx]>;
 920
 921 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 922                                                          FeatureHasRetAddrStack,
 923                                                          FeatureTrustZone,
 924                                                          FeatureSlowFPBrcc,
 925                                                          FeatureHasSlowFPVMLx,
 926                                                          FeatureHasSlowFPVFMx,
 927                                                          FeatureVMLxForwarding,
 928                                                          FeatureMP,
 929                                                          FeatureVFP4]>;
 930
 931 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 932                                                          FeatureHasRetAddrStack,
 933                                                          FeatureTrustZone,
 934                                                          FeatureSlowFPBrcc,
 935                                                          FeatureHasVMLxHazards,
 936                                                          FeatureHasSlowFPVMLx,
 937                                                          FeatureHasSlowFPVFMx,
 938                                                          FeatureVMLxForwarding,
 939                                                          FeatureMP,
 940                                                          FeatureVFP4,
 941                                                          FeatureVirtualization]>;
 942
 943 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 944                                                          FeatureHasRetAddrStack,
 945                                                          FeatureNonpipelinedVFP,
 946                                                          FeatureTrustZone,
 947                                                          FeatureSlowFPBrcc,
 948                                                          FeatureHasVMLxHazards,
 949                                                          FeatureHasSlowFPVMLx,
 950                                                          FeatureHasSlowFPVFMx,
 951                                                          FeatureVMLxForwarding]>;
 952
 953 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 954                                                          FeatureHasRetAddrStack,
 955                                                          FeatureTrustZone,
 956                                                          FeatureHasVMLxHazards,
 957                                                          FeatureVMLxForwarding,
 958                                                          FeatureFP16,
 959                                                          FeatureAvoidPartialCPSR,
 960                                                          FeatureExpandMLx,
 961                                                          FeaturePreferVMOVSR,
 962                                                          FeatureMuxedUnits,
 963                                                          FeatureNEONForFPMovs,
 964                                                          FeatureCheckVLDnAlign,
 965                                                          FeatureMP]>;
 966
 967 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 968                                                          FeatureHasRetAddrStack,
 969                                                          FeatureTrustZone,
 970                                                          FeatureVMLxForwarding,
 971                                                          FeatureVFP4,
 972                                                          FeatureAvoidPartialCPSR,
 973                                                          FeatureVirtualization,
 974                                                          FeatureMP]>;
 975
 976 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 977                                                          FeatureDontWidenVMOVS,
 978                                                          FeatureSplatVFPToNeon,
 979                                                          FeatureHasRetAddrStack,
 980                                                          FeatureMuxedUnits,
 981                                                          FeatureTrustZone,
 982                                                          FeatureVFP4,
 983                                                          FeatureMP,
 984                                                          FeatureCheckVLDnAlign,
 985                                                          FeatureAvoidPartialCPSR,
 986                                                          FeatureVirtualization]>;
 987
 988 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 989                                                          FeatureHasRetAddrStack,
 990                                                          FeatureTrustZone,
 991                                                          FeatureMP,
 992                                                          FeatureVMLxForwarding,
 993                                                          FeatureVFP4,
 994                                                          FeatureAvoidPartialCPSR,
 995                                                          FeatureVirtualization]>;
 996
 997 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 998 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 999                                                          FeatureHasRetAddrStack,
1000                                                          FeatureMuxedUnits,
1001                                                          FeatureCheckVLDnAlign,
1002                                                          FeatureVMLxForwarding,
1003                                                          FeatureFP16,
1004                                                          FeatureAvoidPartialCPSR,
1005                                                          FeatureVFP4,
1006                                                          FeatureHWDivThumb,
1007                                                          FeatureHWDivARM]>;
1008
1009 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
1010                                                          FeatureHasRetAddrStack,
1011                                                          FeatureNEONForFP,
1012                                                          FeatureVFP4,
1013                                                          FeatureUseWideStrideVFP,
1014                                                          FeatureMP,
1015                                                          FeatureHWDivThumb,
1016                                                          FeatureHWDivARM,
1017                                                          FeatureAvoidPartialCPSR,
1018                                                          FeatureAvoidMOVsShOp,
1019                                                          FeatureHasSlowFPVMLx,
1020                                                          FeatureHasSlowFPVFMx,
1021                                                          FeatureHasVMLxHazards,
1022                                                          FeatureProfUnpredicate,
1023                                                          FeaturePrefISHSTBarrier,
1024                                                          FeatureSlowOddRegister,
1025                                                          FeatureSlowLoadDSubreg,
1026                                                          FeatureSlowVGETLNi32,
1027                                                          FeatureSlowVDUP32,
1028                                                          FeatureUseMISched,
1029                                                          FeatureNoPostRASched]>;
1030
1031 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
1032                                                          FeatureHasRetAddrStack,
1033                                                          FeatureAvoidPartialCPSR]>;
1034
1035 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
1036                                                          FeatureHasRetAddrStack,
1037                                                          FeatureSlowFPBrcc,
1038                                                          FeatureHasSlowFPVMLx,
1039                                                          FeatureHasSlowFPVFMx,
1040                                                          FeatureVFP3_D16,
1041                                                          FeatureAvoidPartialCPSR]>;
1042
1043 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
1044                                                          FeatureHasRetAddrStack,
1045                                                          FeatureVFP3_D16,
1046                                                          FeatureSlowFPBrcc,
1047                                                          FeatureHWDivARM,
1048                                                          FeatureHasSlowFPVMLx,
1049                                                          FeatureHasSlowFPVFMx,
1050                                                          FeatureAvoidPartialCPSR]>;
1051
1052 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
1053                                                          FeatureHasRetAddrStack,
1054                                                          FeatureVFP3_D16,
1055                                                          FeatureFP16,
1056                                                          FeatureMP,
1057                                                          FeatureSlowFPBrcc,
1058                                                          FeatureHWDivARM,
1059                                                          FeatureHasSlowFPVMLx,
1060                                                          FeatureHasSlowFPVFMx,
1061                                                          FeatureAvoidPartialCPSR]>;
1062
1063 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
1064                                                          FeatureHasRetAddrStack,
1065                                                          FeatureVFP3_D16,
1066                                                          FeatureFP16,
1067                                                          FeatureMP,
1068                                                          FeatureSlowFPBrcc,
1069                                                          FeatureHWDivARM,
1070                                                          FeatureHasSlowFPVMLx,
1071                                                          FeatureHasSlowFPVFMx,
1072                                                          FeatureAvoidPartialCPSR]>;
1073
1074 def : ProcessorModel<"cortex-m3",   CortexM4Model,      [ARMv7m,
1075                                                          ProcM3,
1076                                                          FeaturePrefLoopAlign32,
1077                                                          FeatureUseMISched,
1078                                                          FeatureHasNoBranchPredictor]>;
1079
1080 def : ProcessorModel<"sc300",       CortexM4Model,      [ARMv7m,
1081                                                          ProcM3,
1082                                                          FeatureUseMISched,
1083                                                          FeatureHasNoBranchPredictor]>;
1084
1085 def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
1086                                                          FeatureVFP4_D16_SP,
1087                                                          FeaturePrefLoopAlign32,
1088                                                          FeatureHasSlowFPVMLx,
1089                                                          FeatureHasSlowFPVFMx,
1090                                                          FeatureUseMISched,
1091                                                          FeatureHasNoBranchPredictor]>;
1092
1093 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
1094                                                          FeatureFPARMv8_D16]>;
1095
1096 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
1097                                                          FeatureNoMovt]>;
1098
1099 def : ProcessorModel<"cortex-m33", CortexM4Model,       [ARMv8mMainline,
1100                                                          FeatureDSP,
1101                                                          FeatureFPARMv8_D16_SP,
1102                                                          FeaturePrefLoopAlign32,
1103                                                          FeatureHasSlowFPVMLx,
1104                                                          FeatureHasSlowFPVFMx,
1105                                                          FeatureUseMISched,
1106                                                          FeatureHasNoBranchPredictor]>;
1107
1108 def : ProcessorModel<"cortex-m35p", CortexM4Model,      [ARMv8mMainline,
1109                                                          FeatureDSP,
1110                                                          FeatureFPARMv8_D16_SP,
1111                                                          FeaturePrefLoopAlign32,
1112                                                          FeatureHasSlowFPVMLx,
1113                                                          FeatureHasSlowFPVFMx,
1114                                                          FeatureUseMISched,
1115                                                          FeatureHasNoBranchPredictor]>;
1116
1117
1118 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
1119                                                          FeatureHWDivThumb,
1120                                                          FeatureHWDivARM,
1121                                                          FeatureCrypto,
1122                                                          FeatureCRC]>;
1123
1124 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
1125                                                          FeatureHWDivThumb,
1126                                                          FeatureHWDivARM,
1127                                                          FeatureCrypto,
1128                                                          FeatureCRC]>;
1129
1130 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
1131                                                          FeatureHWDivThumb,
1132                                                          FeatureHWDivARM,
1133                                                          FeatureCrypto,
1134                                                          FeatureCRC,
1135                                                          FeatureFPAO]>;
1136
1137 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
1138                                                          FeatureHWDivThumb,
1139                                                          FeatureHWDivARM,
1140                                                          FeatureDotProd]>;
1141
1142 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
1143                                                          FeatureHWDivThumb,
1144                                                          FeatureHWDivARM,
1145                                                          FeatureCrypto,
1146                                                          FeatureCRC,
1147                                                          FeatureFPAO,
1148                                                          FeatureAvoidPartialCPSR,
1149                                                          FeatureCheapPredicableCPSR]>;
1150
1151 def : ProcessorModel<"cortex-a72",  CortexA57Model,     [ARMv8a, ProcA72,
1152                                                          FeatureHWDivThumb,
1153                                                          FeatureHWDivARM,
1154                                                          FeatureCrypto,
1155                                                          FeatureCRC]>;
1156
1157 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
1158                                                          FeatureHWDivThumb,
1159                                                          FeatureHWDivARM,
1160                                                          FeatureCrypto,
1161                                                          FeatureCRC]>;
1162
1163 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1164                                                          FeatureHWDivThumb,
1165                                                          FeatureHWDivARM,
1166                                                          FeatureDotProd]>;
1167
1168 def : ProcNoItin<"cortex-a76",                          [ARMv82a, ProcA76,
1169                                                          FeatureHWDivThumb,
1170                                                          FeatureHWDivARM,
1171                                                          FeatureCrypto,
1172                                                          FeatureCRC,
1173                                                          FeatureFullFP16,
1174                                                          FeatureDotProd]>;
1175
1176 def : ProcNoItin<"cortex-a76ae",                        [ARMv82a, ProcA76,
1177                                                          FeatureHWDivThumb,
1178                                                          FeatureHWDivARM,
1179                                                          FeatureCrypto,
1180                                                          FeatureCRC,
1181                                                          FeatureFullFP16,
1182                                                          FeatureDotProd]>;
1183
1184 def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
1185                                                          FeatureHWDivThumb,
1186                                                          FeatureHWDivARM,
1187                                                          FeatureCrypto,
1188                                                          FeatureCRC,
1189                                                          FeatureDotProd]>;
1190
1191 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1192                                                          FeatureHasRetAddrStack,
1193                                                          FeatureNEONForFP,
1194                                                          FeatureVFP4,
1195                                                          FeatureMP,
1196                                                          FeatureHWDivThumb,
1197                                                          FeatureHWDivARM,
1198                                                          FeatureAvoidPartialCPSR,
1199                                                          FeatureAvoidMOVsShOp,
1200                                                          FeatureHasSlowFPVMLx,
1201                                                          FeatureHasSlowFPVFMx,
1202                                                          FeatureCrypto,
1203                                                          FeatureUseMISched,
1204                                                          FeatureZCZeroing,
1205                                                          FeatureNoPostRASched]>;
1206
1207 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynos]>;
1208 def : ProcNoItin<"exynos-m4",                           [ARMv82a, ProcExynos,
1209                                                          FeatureFullFP16,
1210                                                          FeatureDotProd]>;
1211 def : ProcNoItin<"exynos-m5",                           [ARMv82a, ProcExynos,
1212                                                          FeatureFullFP16,
1213                                                          FeatureDotProd]>;
1214
1215 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1216                                                          FeatureHWDivThumb,
1217                                                          FeatureHWDivARM,
1218                                                          FeatureCrypto,
1219                                                          FeatureCRC]>;
1220
1221 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1222                                                          FeatureUseMISched,
1223                                                          FeatureFPAO]>;
1224
1225 //===----------------------------------------------------------------------===//
1226 // Register File Description
1227 //===----------------------------------------------------------------------===//
1228
1229 include "ARMRegisterInfo.td"
1230 include "ARMRegisterBanks.td"
1231 include "ARMCallingConv.td"
1232
1233 //===----------------------------------------------------------------------===//
1234 // Instruction Descriptions
1235 //===----------------------------------------------------------------------===//
1236
1237 include "ARMInstrInfo.td"
1238 def ARMInstrInfo : InstrInfo;
1239
1240 //===----------------------------------------------------------------------===//
1241 // Declare the target which we are implementing
1242 //===----------------------------------------------------------------------===//
1243
1244 def ARMAsmWriter : AsmWriter {
1245   string AsmWriterClassName  = "InstPrinter";
1246   int PassSubtarget = 1;
1247   int Variant = 0;
1248   bit isMCAsmWriter = 1;
1249 }
1250
1251 def ARMAsmParser : AsmParser {
1252   bit ReportMultipleNearMisses = 1;
1253 }
1254
1255 def ARMAsmParserVariant : AsmParserVariant {
1256   int Variant = 0;
1257   string Name = "ARM";
1258   string BreakCharacters = ".";
1259 }
1260
1261 def ARM : Target {
1262   // Pull in Instruction Info.
1263   let InstructionSet = ARMInstrInfo;
1264   let AssemblyWriters = [ARMAsmWriter];
1265   let AssemblyParsers = [ARMAsmParser];
1266   let AssemblyParserVariants = [ARMAsmParserVariant];
1267   let AllowRegisterRenaming = 1;
1268 }