1 //===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the ARM-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // ARMGenFastISel.inc, which is #included here.
13 //===----------------------------------------------------------------------===//
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMBaseInfo.h"
25 #include "Utils/ARMBaseInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineConstantPool.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineMemOperand.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/RuntimeLibcalls.h"
44 #include "llvm/CodeGen/TargetInstrInfo.h"
45 #include "llvm/CodeGen/TargetLowering.h"
46 #include "llvm/CodeGen/TargetOpcodes.h"
47 #include "llvm/CodeGen/TargetRegisterInfo.h"
48 #include "llvm/CodeGen/ValueTypes.h"
49 #include "llvm/IR/Argument.h"
50 #include "llvm/IR/Attributes.h"
51 #include "llvm/IR/CallSite.h"
52 #include "llvm/IR/CallingConv.h"
53 #include "llvm/IR/Constant.h"
54 #include "llvm/IR/Constants.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DerivedTypes.h"
57 #include "llvm/IR/Function.h"
58 #include "llvm/IR/GetElementPtrTypeIterator.h"
59 #include "llvm/IR/GlobalValue.h"
60 #include "llvm/IR/GlobalVariable.h"
61 #include "llvm/IR/InstrTypes.h"
62 #include "llvm/IR/Instruction.h"
63 #include "llvm/IR/Instructions.h"
64 #include "llvm/IR/IntrinsicInst.h"
65 #include "llvm/IR/Intrinsics.h"
66 #include "llvm/IR/Module.h"
67 #include "llvm/IR/Operator.h"
68 #include "llvm/IR/Type.h"
69 #include "llvm/IR/User.h"
70 #include "llvm/IR/Value.h"
71 #include "llvm/MC/MCInstrDesc.h"
72 #include "llvm/MC/MCRegisterInfo.h"
73 #include "llvm/Support/Casting.h"
74 #include "llvm/Support/Compiler.h"
75 #include "llvm/Support/ErrorHandling.h"
76 #include "llvm/Support/MachineValueType.h"
77 #include "llvm/Support/MathExtras.h"
78 #include "llvm/Target/TargetMachine.h"
79 #include "llvm/Target/TargetOptions.h"
88 // All possible address modes, plus some.
102 // Innocuous defaults for our address.
108 class ARMFastISel final : public FastISel {
109 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
110 /// make the right decision when generating code for different targets.
111 const ARMSubtarget *Subtarget;
113 const TargetMachine &TM;
114 const TargetInstrInfo &TII;
115 const TargetLowering &TLI;
116 ARMFunctionInfo *AFI;
118 // Convenience variables to avoid some queries.
120 LLVMContext *Context;
123 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
124 const TargetLibraryInfo *libInfo)
125 : FastISel(funcInfo, libInfo),
127 &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
128 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
129 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
130 TLI(*Subtarget->getTargetLowering()) {
131 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
132 isThumb2 = AFI->isThumbFunction();
133 Context = &funcInfo.Fn->getContext();
137 // Code from FastISel.cpp.
139 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
140 const TargetRegisterClass *RC,
141 unsigned Op0, bool Op0IsKill);
142 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
143 const TargetRegisterClass *RC,
144 unsigned Op0, bool Op0IsKill,
145 unsigned Op1, bool Op1IsKill);
146 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
147 const TargetRegisterClass *RC,
148 unsigned Op0, bool Op0IsKill,
150 unsigned fastEmitInst_i(unsigned MachineInstOpcode,
151 const TargetRegisterClass *RC,
154 // Backend specific FastISel code.
156 bool fastSelectInstruction(const Instruction *I) override;
157 unsigned fastMaterializeConstant(const Constant *C) override;
158 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
159 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
160 const LoadInst *LI) override;
161 bool fastLowerArguments() override;
163 #include "ARMGenFastISel.inc"
165 // Instruction selection routines.
167 bool SelectLoad(const Instruction *I);
168 bool SelectStore(const Instruction *I);
169 bool SelectBranch(const Instruction *I);
170 bool SelectIndirectBr(const Instruction *I);
171 bool SelectCmp(const Instruction *I);
172 bool SelectFPExt(const Instruction *I);
173 bool SelectFPTrunc(const Instruction *I);
174 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
175 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
176 bool SelectIToFP(const Instruction *I, bool isSigned);
177 bool SelectFPToI(const Instruction *I, bool isSigned);
178 bool SelectDiv(const Instruction *I, bool isSigned);
179 bool SelectRem(const Instruction *I, bool isSigned);
180 bool SelectCall(const Instruction *I, const char *IntrMemName);
181 bool SelectIntrinsicCall(const IntrinsicInst &I);
182 bool SelectSelect(const Instruction *I);
183 bool SelectRet(const Instruction *I);
184 bool SelectTrunc(const Instruction *I);
185 bool SelectIntExt(const Instruction *I);
186 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
190 bool isPositionIndependent() const;
191 bool isTypeLegal(Type *Ty, MVT &VT);
192 bool isLoadTypeLegal(Type *Ty, MVT &VT);
193 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
195 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
196 unsigned Alignment = 0, bool isZExt = true,
197 bool allocReg = true);
198 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
199 unsigned Alignment = 0);
200 bool ARMComputeAddress(const Value *Obj, Address &Addr);
201 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
202 bool ARMIsMemCpySmall(uint64_t Len);
203 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
205 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
206 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
207 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
208 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
209 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
210 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
211 unsigned ARMSelectCallOp(bool UseReg);
212 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
214 const TargetLowering *getTargetLowering() { return &TLI; }
216 // Call handling routines.
218 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
221 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
222 SmallVectorImpl<Register> &ArgRegs,
223 SmallVectorImpl<MVT> &ArgVTs,
224 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
225 SmallVectorImpl<Register> &RegArgs,
229 unsigned getLibcallReg(const Twine &Name);
230 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
231 const Instruction *I, CallingConv::ID CC,
232 unsigned &NumBytes, bool isVarArg);
233 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
235 // OptionalDef handling routines.
237 bool isARMNEONPred(const MachineInstr *MI);
238 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
239 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
240 void AddLoadStoreOperands(MVT VT, Address &Addr,
241 const MachineInstrBuilder &MIB,
242 MachineMemOperand::Flags Flags, bool useAM3);
245 } // end anonymous namespace
247 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
248 // we don't care about implicit defs here, just places we'll need to add a
249 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
250 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
251 if (!MI->hasOptionalDef())
254 // Look to see if our OptionalDef is defining CPSR or CCR.
255 for (const MachineOperand &MO : MI->operands()) {
256 if (!MO.isReg() || !MO.isDef()) continue;
257 if (MO.getReg() == ARM::CPSR)
263 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
264 const MCInstrDesc &MCID = MI->getDesc();
266 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
267 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
268 AFI->isThumb2Function())
269 return MI->isPredicable();
271 for (const MCOperandInfo &opInfo : MCID.operands())
272 if (opInfo.isPredicate())
278 // If the machine is predicable go ahead and add the predicate operands, if
279 // it needs default CC operands add those.
280 // TODO: If we want to support thumb1 then we'll need to deal with optional
281 // CPSR defs that need to be added before the remaining operands. See s_cc_out
282 // for descriptions why.
283 const MachineInstrBuilder &
284 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
285 MachineInstr *MI = &*MIB;
287 // Do we use a predicate? or...
288 // Are we NEON in ARM mode and have a predicate operand? If so, I know
289 // we're not predicable but add it anyways.
290 if (isARMNEONPred(MI))
291 MIB.add(predOps(ARMCC::AL));
293 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
294 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
296 if (DefinesOptionalPredicate(MI, &CPSR))
297 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp());
301 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
302 const TargetRegisterClass *RC,
303 unsigned Op0, bool Op0IsKill) {
304 Register ResultReg = createResultReg(RC);
305 const MCInstrDesc &II = TII.get(MachineInstOpcode);
307 // Make sure the input operand is sufficiently constrained to be legal
308 // for this instruction.
309 Op0 = constrainOperandRegClass(II, Op0, 1);
310 if (II.getNumDefs() >= 1) {
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
312 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
315 .addReg(Op0, Op0IsKill * RegState::Kill));
316 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
317 TII.get(TargetOpcode::COPY), ResultReg)
318 .addReg(II.ImplicitDefs[0]));
323 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
324 const TargetRegisterClass *RC,
325 unsigned Op0, bool Op0IsKill,
326 unsigned Op1, bool Op1IsKill) {
327 unsigned ResultReg = createResultReg(RC);
328 const MCInstrDesc &II = TII.get(MachineInstOpcode);
330 // Make sure the input operands are sufficiently constrained to be legal
331 // for this instruction.
332 Op0 = constrainOperandRegClass(II, Op0, 1);
333 Op1 = constrainOperandRegClass(II, Op1, 2);
335 if (II.getNumDefs() >= 1) {
337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
338 .addReg(Op0, Op0IsKill * RegState::Kill)
339 .addReg(Op1, Op1IsKill * RegState::Kill));
341 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
342 .addReg(Op0, Op0IsKill * RegState::Kill)
343 .addReg(Op1, Op1IsKill * RegState::Kill));
344 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
345 TII.get(TargetOpcode::COPY), ResultReg)
346 .addReg(II.ImplicitDefs[0]));
351 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
352 const TargetRegisterClass *RC,
353 unsigned Op0, bool Op0IsKill,
355 unsigned ResultReg = createResultReg(RC);
356 const MCInstrDesc &II = TII.get(MachineInstOpcode);
358 // Make sure the input operand is sufficiently constrained to be legal
359 // for this instruction.
360 Op0 = constrainOperandRegClass(II, Op0, 1);
361 if (II.getNumDefs() >= 1) {
363 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
364 .addReg(Op0, Op0IsKill * RegState::Kill)
367 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
368 .addReg(Op0, Op0IsKill * RegState::Kill)
370 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
371 TII.get(TargetOpcode::COPY), ResultReg)
372 .addReg(II.ImplicitDefs[0]));
377 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
378 const TargetRegisterClass *RC,
380 unsigned ResultReg = createResultReg(RC);
381 const MCInstrDesc &II = TII.get(MachineInstOpcode);
383 if (II.getNumDefs() >= 1) {
384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
385 ResultReg).addImm(Imm));
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
389 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
390 TII.get(TargetOpcode::COPY), ResultReg)
391 .addReg(II.ImplicitDefs[0]));
396 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
397 // checks from the various callers.
398 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
399 if (VT == MVT::f64) return 0;
401 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
402 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
403 TII.get(ARM::VMOVSR), MoveReg)
408 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
409 if (VT == MVT::i64) return 0;
411 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
412 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
413 TII.get(ARM::VMOVRS), MoveReg)
418 // For double width floating point we need to materialize two constants
419 // (the high and the low) into integer registers then use a move to get
420 // the combined constant into an FP reg.
421 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
422 const APFloat Val = CFP->getValueAPF();
423 bool is64bit = VT == MVT::f64;
425 // This checks to see if we can use VFP3 instructions to materialize
426 // a constant, otherwise we have to go through the constant pool.
427 if (TLI.isFPImmLegal(Val, VT)) {
431 Imm = ARM_AM::getFP64Imm(Val);
434 Imm = ARM_AM::getFP32Imm(Val);
437 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
438 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
439 TII.get(Opc), DestReg).addImm(Imm));
443 // Require VFP2 for loading fp constants.
444 if (!Subtarget->hasVFP2Base()) return false;
446 // MachineConstantPool wants an explicit alignment.
447 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
449 // TODO: Figure out if this is correct.
450 Align = DL.getTypeAllocSize(CFP->getType());
452 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
453 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
454 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
456 // The extra reg is for addrmode5.
458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
459 .addConstantPoolIndex(Idx)
464 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
465 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
468 // If we can do this in a single instruction without a constant pool entry
470 const ConstantInt *CI = cast<ConstantInt>(C);
471 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
472 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
473 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
475 unsigned ImmReg = createResultReg(RC);
476 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
477 TII.get(Opc), ImmReg)
478 .addImm(CI->getZExtValue()));
482 // Use MVN to emit negative constants.
483 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
484 unsigned Imm = (unsigned)~(CI->getSExtValue());
485 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
486 (ARM_AM::getSOImmVal(Imm) != -1);
488 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
489 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
491 unsigned ImmReg = createResultReg(RC);
492 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
493 TII.get(Opc), ImmReg)
499 unsigned ResultReg = 0;
500 if (Subtarget->useMovt())
501 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
506 // Load from constant pool. For now 32-bit only.
510 // MachineConstantPool wants an explicit alignment.
511 unsigned Align = DL.getPrefTypeAlignment(C->getType());
513 // TODO: Figure out if this is correct.
514 Align = DL.getTypeAllocSize(C->getType());
516 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
517 ResultReg = createResultReg(TLI.getRegClassFor(VT));
519 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
520 TII.get(ARM::t2LDRpci), ResultReg)
521 .addConstantPoolIndex(Idx));
523 // The extra immediate is for addrmode2.
524 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
525 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
526 TII.get(ARM::LDRcp), ResultReg)
527 .addConstantPoolIndex(Idx)
533 bool ARMFastISel::isPositionIndependent() const {
534 return TLI.isPositionIndependent();
537 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
538 // For now 32-bit only.
539 if (VT != MVT::i32 || GV->isThreadLocal()) return 0;
541 // ROPI/RWPI not currently supported.
542 if (Subtarget->isROPI() || Subtarget->isRWPI())
545 bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
546 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
548 unsigned DestReg = createResultReg(RC);
550 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
551 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
552 bool IsThreadLocal = GVar && GVar->isThreadLocal();
553 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
555 bool IsPositionIndependent = isPositionIndependent();
556 // Use movw+movt when possible, it avoids constant pool entries.
557 // Non-darwin targets only support static movt relocations in FastISel.
558 if (Subtarget->useMovt() &&
559 (Subtarget->isTargetMachO() || !IsPositionIndependent)) {
561 unsigned char TF = 0;
562 if (Subtarget->isTargetMachO())
563 TF = ARMII::MO_NONLAZY;
565 if (IsPositionIndependent)
566 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
568 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
570 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
572 // MachineConstantPool wants an explicit alignment.
573 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
575 // TODO: Figure out if this is correct.
576 Align = DL.getTypeAllocSize(GV->getType());
579 if (Subtarget->isTargetELF() && IsPositionIndependent)
580 return ARMLowerPICELF(GV, Align, VT);
583 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
584 unsigned Id = AFI->createPICLabelUId();
585 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
588 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
591 MachineInstrBuilder MIB;
593 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
594 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
595 DestReg).addConstantPoolIndex(Idx);
596 if (IsPositionIndependent)
598 AddOptionalDefs(MIB);
600 // The extra immediate is for addrmode2.
601 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
602 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
603 TII.get(ARM::LDRcp), DestReg)
604 .addConstantPoolIndex(Idx)
606 AddOptionalDefs(MIB);
608 if (IsPositionIndependent) {
609 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
610 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
612 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
613 DbgLoc, TII.get(Opc), NewDestReg)
616 AddOptionalDefs(MIB);
623 MachineInstrBuilder MIB;
624 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
626 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
627 TII.get(ARM::t2LDRi12), NewDestReg)
631 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
632 TII.get(ARM::LDRi12), NewDestReg)
635 DestReg = NewDestReg;
636 AddOptionalDefs(MIB);
642 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
643 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
645 // Only handle simple types.
646 if (!CEVT.isSimple()) return 0;
647 MVT VT = CEVT.getSimpleVT();
649 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
650 return ARMMaterializeFP(CFP, VT);
651 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
652 return ARMMaterializeGV(GV, VT);
653 else if (isa<ConstantInt>(C))
654 return ARMMaterializeInt(C, VT);
659 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
661 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
662 // Don't handle dynamic allocas.
663 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
666 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
668 DenseMap<const AllocaInst*, int>::iterator SI =
669 FuncInfo.StaticAllocaMap.find(AI);
671 // This will get lowered later into the correct offsets and registers
672 // via rewriteXFrameIndex.
673 if (SI != FuncInfo.StaticAllocaMap.end()) {
674 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
676 unsigned ResultReg = createResultReg(RC);
677 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
679 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
680 TII.get(Opc), ResultReg)
681 .addFrameIndex(SI->second)
689 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
690 EVT evt = TLI.getValueType(DL, Ty, true);
692 // Only handle simple types.
693 if (evt == MVT::Other || !evt.isSimple()) return false;
694 VT = evt.getSimpleVT();
696 // Handle all legal types, i.e. a register that will directly hold this
698 return TLI.isTypeLegal(VT);
701 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
702 if (isTypeLegal(Ty, VT)) return true;
704 // If this is a type than can be sign or zero-extended to a basic operation
705 // go ahead and accept it now.
706 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
712 // Computes the address to get to an object.
713 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
714 // Some boilerplate from the X86 FastISel.
715 const User *U = nullptr;
716 unsigned Opcode = Instruction::UserOp1;
717 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
718 // Don't walk into other basic blocks unless the object is an alloca from
719 // another block, otherwise it may not have a virtual register assigned.
720 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
721 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
722 Opcode = I->getOpcode();
725 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
726 Opcode = C->getOpcode();
730 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
731 if (Ty->getAddressSpace() > 255)
732 // Fast instruction selection doesn't support the special
739 case Instruction::BitCast:
740 // Look through bitcasts.
741 return ARMComputeAddress(U->getOperand(0), Addr);
742 case Instruction::IntToPtr:
743 // Look past no-op inttoptrs.
744 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
745 TLI.getPointerTy(DL))
746 return ARMComputeAddress(U->getOperand(0), Addr);
748 case Instruction::PtrToInt:
749 // Look past no-op ptrtoints.
750 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
751 return ARMComputeAddress(U->getOperand(0), Addr);
753 case Instruction::GetElementPtr: {
754 Address SavedAddr = Addr;
755 int TmpOffset = Addr.Offset;
757 // Iterate through the GEP folding the constants into offsets where
759 gep_type_iterator GTI = gep_type_begin(U);
760 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
761 i != e; ++i, ++GTI) {
762 const Value *Op = *i;
763 if (StructType *STy = GTI.getStructTypeOrNull()) {
764 const StructLayout *SL = DL.getStructLayout(STy);
765 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
766 TmpOffset += SL->getElementOffset(Idx);
768 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
770 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
771 // Constant-offset addressing.
772 TmpOffset += CI->getSExtValue() * S;
775 if (canFoldAddIntoGEP(U, Op)) {
776 // A compatible add with a constant operand. Fold the constant.
778 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
779 TmpOffset += CI->getSExtValue() * S;
780 // Iterate on the other operand.
781 Op = cast<AddOperator>(Op)->getOperand(0);
785 goto unsupported_gep;
790 // Try to grab the base operand now.
791 Addr.Offset = TmpOffset;
792 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
794 // We failed, restore everything and try the other options.
800 case Instruction::Alloca: {
801 const AllocaInst *AI = cast<AllocaInst>(Obj);
802 DenseMap<const AllocaInst*, int>::iterator SI =
803 FuncInfo.StaticAllocaMap.find(AI);
804 if (SI != FuncInfo.StaticAllocaMap.end()) {
805 Addr.BaseType = Address::FrameIndexBase;
806 Addr.Base.FI = SI->second;
813 // Try to get this in a register if nothing else has worked.
814 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
815 return Addr.Base.Reg != 0;
818 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
819 bool needsLowering = false;
820 switch (VT.SimpleTy) {
821 default: llvm_unreachable("Unhandled load/store type!");
827 // Integer loads/stores handle 12-bit offsets.
828 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
829 // Handle negative offsets.
830 if (needsLowering && isThumb2)
831 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
834 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
835 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
840 // Floating point operands handle 8-bit offsets.
841 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
845 // If this is a stack pointer and the offset needs to be simplified then
846 // put the alloca address into a register, set the base type back to
847 // register and continue. This should almost never happen.
848 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
849 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
851 unsigned ResultReg = createResultReg(RC);
852 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
853 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
854 TII.get(Opc), ResultReg)
855 .addFrameIndex(Addr.Base.FI)
857 Addr.Base.Reg = ResultReg;
858 Addr.BaseType = Address::RegBase;
861 // Since the offset is too large for the load/store instruction
862 // get the reg+offset into a register.
864 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
865 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
870 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
871 const MachineInstrBuilder &MIB,
872 MachineMemOperand::Flags Flags,
874 // addrmode5 output depends on the selection dag addressing dividing the
875 // offset by 4 that it then later multiplies. Do this here as well.
876 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
879 // Frame base works a bit differently. Handle it separately.
880 if (Addr.BaseType == Address::FrameIndexBase) {
881 int FI = Addr.Base.FI;
882 int Offset = Addr.Offset;
883 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
884 MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
885 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
886 // Now add the rest of the operands.
887 MIB.addFrameIndex(FI);
889 // ARM halfword load/stores and signed byte loads need an additional
892 int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
896 MIB.addImm(Addr.Offset);
898 MIB.addMemOperand(MMO);
900 // Now add the rest of the operands.
901 MIB.addReg(Addr.Base.Reg);
903 // ARM halfword load/stores and signed byte loads need an additional
906 int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
910 MIB.addImm(Addr.Offset);
913 AddOptionalDefs(MIB);
916 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
917 unsigned Alignment, bool isZExt, bool allocReg) {
920 bool needVMOV = false;
921 const TargetRegisterClass *RC;
922 switch (VT.SimpleTy) {
923 // This is mostly going to be Neon/vector support.
924 default: return false;
928 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
929 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
931 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
940 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
943 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
947 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
948 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
950 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
952 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
955 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
958 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
962 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
969 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
972 if (!Subtarget->hasVFP2Base()) return false;
973 // Unaligned loads need special handling. Floats require word-alignment.
974 if (Alignment && Alignment < 4) {
977 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
978 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
981 RC = TLI.getRegClassFor(VT);
985 // Can load and store double precision even without FeatureFP64
986 if (!Subtarget->hasVFP2Base()) return false;
987 // FIXME: Unaligned loads need special handling. Doublewords require
989 if (Alignment && Alignment < 4)
993 RC = TLI.getRegClassFor(VT);
996 // Simplify this down to something we can handle.
997 ARMSimplifyAddress(Addr, VT, useAM3);
999 // Create the base instruction, then add the operands.
1001 ResultReg = createResultReg(RC);
1002 assert(ResultReg > 255 && "Expected an allocated virtual register.");
1003 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1004 TII.get(Opc), ResultReg);
1005 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1007 // If we had an unaligned load of a float we've converted it to an regular
1008 // load. Now we must move from the GRP to the FP register.
1010 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1011 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1012 TII.get(ARM::VMOVSR), MoveReg)
1013 .addReg(ResultReg));
1014 ResultReg = MoveReg;
1019 bool ARMFastISel::SelectLoad(const Instruction *I) {
1020 // Atomic loads need special handling.
1021 if (cast<LoadInst>(I)->isAtomic())
1024 const Value *SV = I->getOperand(0);
1025 if (TLI.supportSwiftError()) {
1026 // Swifterror values can come from either a function parameter with
1027 // swifterror attribute or an alloca with swifterror attribute.
1028 if (const Argument *Arg = dyn_cast<Argument>(SV)) {
1029 if (Arg->hasSwiftErrorAttr())
1033 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
1034 if (Alloca->isSwiftError())
1039 // Verify we have a legal type before going any further.
1041 if (!isLoadTypeLegal(I->getType(), VT))
1044 // See if we can handle this address.
1046 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1049 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1051 updateValueMap(I, ResultReg);
1055 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1056 unsigned Alignment) {
1058 bool useAM3 = false;
1059 switch (VT.SimpleTy) {
1060 // This is mostly going to be Neon/vector support.
1061 default: return false;
1063 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1064 : &ARM::GPRRegClass);
1065 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1066 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1067 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1069 .addReg(SrcReg).addImm(1));
1075 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1076 StrOpc = ARM::t2STRBi8;
1078 StrOpc = ARM::t2STRBi12;
1080 StrOpc = ARM::STRBi12;
1084 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1088 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1089 StrOpc = ARM::t2STRHi8;
1091 StrOpc = ARM::t2STRHi12;
1098 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1102 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1103 StrOpc = ARM::t2STRi8;
1105 StrOpc = ARM::t2STRi12;
1107 StrOpc = ARM::STRi12;
1111 if (!Subtarget->hasVFP2Base()) return false;
1112 // Unaligned stores need special handling. Floats require word-alignment.
1113 if (Alignment && Alignment < 4) {
1114 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1115 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1116 TII.get(ARM::VMOVRS), MoveReg)
1120 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1122 StrOpc = ARM::VSTRS;
1126 // Can load and store double precision even without FeatureFP64
1127 if (!Subtarget->hasVFP2Base()) return false;
1128 // FIXME: Unaligned stores need special handling. Doublewords require
1130 if (Alignment && Alignment < 4)
1133 StrOpc = ARM::VSTRD;
1136 // Simplify this down to something we can handle.
1137 ARMSimplifyAddress(Addr, VT, useAM3);
1139 // Create the base instruction, then add the operands.
1140 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1141 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1144 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1148 bool ARMFastISel::SelectStore(const Instruction *I) {
1149 Value *Op0 = I->getOperand(0);
1150 unsigned SrcReg = 0;
1152 // Atomic stores need special handling.
1153 if (cast<StoreInst>(I)->isAtomic())
1156 const Value *PtrV = I->getOperand(1);
1157 if (TLI.supportSwiftError()) {
1158 // Swifterror values can come from either a function parameter with
1159 // swifterror attribute or an alloca with swifterror attribute.
1160 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
1161 if (Arg->hasSwiftErrorAttr())
1165 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
1166 if (Alloca->isSwiftError())
1171 // Verify we have a legal type before going any further.
1173 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1176 // Get the value to be stored into a register.
1177 SrcReg = getRegForValue(Op0);
1178 if (SrcReg == 0) return false;
1180 // See if we can handle this address.
1182 if (!ARMComputeAddress(I->getOperand(1), Addr))
1185 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1190 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1192 // Needs two compares...
1193 case CmpInst::FCMP_ONE:
1194 case CmpInst::FCMP_UEQ:
1196 // AL is our "false" for now. The other two need more compares.
1198 case CmpInst::ICMP_EQ:
1199 case CmpInst::FCMP_OEQ:
1201 case CmpInst::ICMP_SGT:
1202 case CmpInst::FCMP_OGT:
1204 case CmpInst::ICMP_SGE:
1205 case CmpInst::FCMP_OGE:
1207 case CmpInst::ICMP_UGT:
1208 case CmpInst::FCMP_UGT:
1210 case CmpInst::FCMP_OLT:
1212 case CmpInst::ICMP_ULE:
1213 case CmpInst::FCMP_OLE:
1215 case CmpInst::FCMP_ORD:
1217 case CmpInst::FCMP_UNO:
1219 case CmpInst::FCMP_UGE:
1221 case CmpInst::ICMP_SLT:
1222 case CmpInst::FCMP_ULT:
1224 case CmpInst::ICMP_SLE:
1225 case CmpInst::FCMP_ULE:
1227 case CmpInst::FCMP_UNE:
1228 case CmpInst::ICMP_NE:
1230 case CmpInst::ICMP_UGE:
1232 case CmpInst::ICMP_ULT:
1237 bool ARMFastISel::SelectBranch(const Instruction *I) {
1238 const BranchInst *BI = cast<BranchInst>(I);
1239 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1240 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1242 // Simple branch support.
1244 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1246 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1247 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1248 // Get the compare predicate.
1249 // Try to take advantage of fallthrough opportunities.
1250 CmpInst::Predicate Predicate = CI->getPredicate();
1251 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1252 std::swap(TBB, FBB);
1253 Predicate = CmpInst::getInversePredicate(Predicate);
1256 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1258 // We may not handle every CC for now.
1259 if (ARMPred == ARMCC::AL) return false;
1261 // Emit the compare.
1262 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1265 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1267 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1268 finishCondBranch(BI->getParent(), TBB, FBB);
1271 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1273 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1274 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1275 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1276 unsigned OpReg = getRegForValue(TI->getOperand(0));
1277 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1278 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1280 .addReg(OpReg).addImm(1));
1282 unsigned CCMode = ARMCC::NE;
1283 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1284 std::swap(TBB, FBB);
1288 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1290 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1292 finishCondBranch(BI->getParent(), TBB, FBB);
1295 } else if (const ConstantInt *CI =
1296 dyn_cast<ConstantInt>(BI->getCondition())) {
1297 uint64_t Imm = CI->getZExtValue();
1298 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1299 fastEmitBranch(Target, DbgLoc);
1303 unsigned CmpReg = getRegForValue(BI->getCondition());
1304 if (CmpReg == 0) return false;
1306 // We've been divorced from our compare! Our block was split, and
1307 // now our compare lives in a predecessor block. We musn't
1308 // re-compare here, as the children of the compare aren't guaranteed
1309 // live across the block boundary (we *could* check for this).
1310 // Regardless, the compare has been done in the predecessor block,
1311 // and it left a value for us in a virtual register. Ergo, we test
1312 // the one-bit value left in the virtual register.
1313 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1314 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1316 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1320 unsigned CCMode = ARMCC::NE;
1321 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1322 std::swap(TBB, FBB);
1326 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1327 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1328 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1329 finishCondBranch(BI->getParent(), TBB, FBB);
1333 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1334 unsigned AddrReg = getRegForValue(I->getOperand(0));
1335 if (AddrReg == 0) return false;
1337 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1338 assert(isThumb2 || Subtarget->hasV4TOps());
1340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1341 TII.get(Opc)).addReg(AddrReg));
1343 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1344 for (const BasicBlock *SuccBB : IB->successors())
1345 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1350 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1352 Type *Ty = Src1Value->getType();
1353 EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1354 if (!SrcEVT.isSimple()) return false;
1355 MVT SrcVT = SrcEVT.getSimpleVT();
1357 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1360 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1363 // Check to see if the 2nd operand is a constant that we can encode directly
1366 bool UseImm = false;
1367 bool isNegativeImm = false;
1368 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1369 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1370 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1371 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1373 const APInt &CIVal = ConstInt->getValue();
1374 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1375 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1376 // then a cmn, because there is no way to represent 2147483648 as a
1377 // signed 32-bit int.
1378 if (Imm < 0 && Imm != (int)0x80000000) {
1379 isNegativeImm = true;
1382 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1383 (ARM_AM::getSOImmVal(Imm) != -1);
1385 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1386 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1387 if (ConstFP->isZero() && !ConstFP->isNegative())
1393 bool needsExt = false;
1394 switch (SrcVT.SimpleTy) {
1395 default: return false;
1396 // TODO: Verify compares.
1399 CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS;
1403 CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD;
1413 CmpOpc = ARM::t2CMPrr;
1415 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1418 CmpOpc = ARM::CMPrr;
1420 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1425 unsigned SrcReg1 = getRegForValue(Src1Value);
1426 if (SrcReg1 == 0) return false;
1428 unsigned SrcReg2 = 0;
1430 SrcReg2 = getRegForValue(Src2Value);
1431 if (SrcReg2 == 0) return false;
1434 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1436 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1437 if (SrcReg1 == 0) return false;
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1440 if (SrcReg2 == 0) return false;
1444 const MCInstrDesc &II = TII.get(CmpOpc);
1445 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1449 .addReg(SrcReg1).addReg(SrcReg2));
1451 MachineInstrBuilder MIB;
1452 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1455 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1458 AddOptionalDefs(MIB);
1461 // For floating point we need to move the result to a comparison register
1462 // that we can then use for branches.
1463 if (Ty->isFloatTy() || Ty->isDoubleTy())
1464 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1465 TII.get(ARM::FMSTAT)));
1469 bool ARMFastISel::SelectCmp(const Instruction *I) {
1470 const CmpInst *CI = cast<CmpInst>(I);
1472 // Get the compare predicate.
1473 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1475 // We may not handle every CC for now.
1476 if (ARMPred == ARMCC::AL) return false;
1478 // Emit the compare.
1479 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1482 // Now set a register based on the comparison. Explicitly set the predicates
1484 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1485 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1486 : &ARM::GPRRegClass;
1487 unsigned DestReg = createResultReg(RC);
1488 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1489 unsigned ZeroReg = fastMaterializeConstant(Zero);
1490 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1492 .addReg(ZeroReg).addImm(1)
1493 .addImm(ARMPred).addReg(ARM::CPSR);
1495 updateValueMap(I, DestReg);
1499 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1500 // Make sure we have VFP and that we're extending float to double.
1501 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1503 Value *V = I->getOperand(0);
1504 if (!I->getType()->isDoubleTy() ||
1505 !V->getType()->isFloatTy()) return false;
1507 unsigned Op = getRegForValue(V);
1508 if (Op == 0) return false;
1510 unsigned Result = createResultReg(&ARM::DPRRegClass);
1511 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1512 TII.get(ARM::VCVTDS), Result)
1514 updateValueMap(I, Result);
1518 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1519 // Make sure we have VFP and that we're truncating double to float.
1520 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1522 Value *V = I->getOperand(0);
1523 if (!(I->getType()->isFloatTy() &&
1524 V->getType()->isDoubleTy())) return false;
1526 unsigned Op = getRegForValue(V);
1527 if (Op == 0) return false;
1529 unsigned Result = createResultReg(&ARM::SPRRegClass);
1530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1531 TII.get(ARM::VCVTSD), Result)
1533 updateValueMap(I, Result);
1537 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1538 // Make sure we have VFP.
1539 if (!Subtarget->hasVFP2Base()) return false;
1542 Type *Ty = I->getType();
1543 if (!isTypeLegal(Ty, DstVT))
1546 Value *Src = I->getOperand(0);
1547 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1548 if (!SrcEVT.isSimple())
1550 MVT SrcVT = SrcEVT.getSimpleVT();
1551 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1554 unsigned SrcReg = getRegForValue(Src);
1555 if (SrcReg == 0) return false;
1557 // Handle sign-extension.
1558 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1559 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1560 /*isZExt*/!isSigned);
1561 if (SrcReg == 0) return false;
1564 // The conversion routine works on fp-reg to fp-reg and the operand above
1565 // was an integer, move it to the fp registers if possible.
1566 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1567 if (FP == 0) return false;
1570 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1571 else if (Ty->isDoubleTy() && Subtarget->hasFP64())
1572 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1575 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1576 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1577 TII.get(Opc), ResultReg).addReg(FP));
1578 updateValueMap(I, ResultReg);
1582 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1583 // Make sure we have VFP.
1584 if (!Subtarget->hasVFP2Base()) return false;
1587 Type *RetTy = I->getType();
1588 if (!isTypeLegal(RetTy, DstVT))
1591 unsigned Op = getRegForValue(I->getOperand(0));
1592 if (Op == 0) return false;
1595 Type *OpTy = I->getOperand(0)->getType();
1596 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1597 else if (OpTy->isDoubleTy() && Subtarget->hasFP64())
1598 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1601 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1602 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1603 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1604 TII.get(Opc), ResultReg).addReg(Op));
1606 // This result needs to be in an integer register, but the conversion only
1607 // takes place in fp-regs.
1608 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1609 if (IntReg == 0) return false;
1611 updateValueMap(I, IntReg);
1615 bool ARMFastISel::SelectSelect(const Instruction *I) {
1617 if (!isTypeLegal(I->getType(), VT))
1620 // Things need to be register sized for register moves.
1621 if (VT != MVT::i32) return false;
1623 unsigned CondReg = getRegForValue(I->getOperand(0));
1624 if (CondReg == 0) return false;
1625 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1626 if (Op1Reg == 0) return false;
1628 // Check to see if we can use an immediate in the conditional move.
1630 bool UseImm = false;
1631 bool isNegativeImm = false;
1632 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1633 assert(VT == MVT::i32 && "Expecting an i32.");
1634 Imm = (int)ConstInt->getValue().getZExtValue();
1636 isNegativeImm = true;
1639 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1640 (ARM_AM::getSOImmVal(Imm) != -1);
1643 unsigned Op2Reg = 0;
1645 Op2Reg = getRegForValue(I->getOperand(2));
1646 if (Op2Reg == 0) return false;
1649 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1650 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1652 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1657 const TargetRegisterClass *RC;
1659 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1660 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1662 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1664 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1666 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1668 unsigned ResultReg = createResultReg(RC);
1670 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1671 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1672 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1679 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1687 updateValueMap(I, ResultReg);
1691 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1693 Type *Ty = I->getType();
1694 if (!isTypeLegal(Ty, VT))
1697 // If we have integer div support we should have selected this automagically.
1698 // In case we have a real miss go ahead and return false and we'll pick
1700 if (Subtarget->hasDivideInThumbMode())
1703 // Otherwise emit a libcall.
1704 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1706 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1707 else if (VT == MVT::i16)
1708 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1709 else if (VT == MVT::i32)
1710 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1711 else if (VT == MVT::i64)
1712 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1713 else if (VT == MVT::i128)
1714 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1715 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1717 return ARMEmitLibcall(I, LC);
1720 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1722 Type *Ty = I->getType();
1723 if (!isTypeLegal(Ty, VT))
1726 // Many ABIs do not provide a libcall for standalone remainder, so we need to
1727 // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
1728 // multi-reg returns, we'll have to bail out.
1729 if (!TLI.hasStandaloneRem(VT)) {
1733 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1735 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1736 else if (VT == MVT::i16)
1737 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1738 else if (VT == MVT::i32)
1739 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1740 else if (VT == MVT::i64)
1741 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1742 else if (VT == MVT::i128)
1743 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1744 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1746 return ARMEmitLibcall(I, LC);
1749 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1750 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1752 // We can get here in the case when we have a binary operation on a non-legal
1753 // type and the target independent selector doesn't know how to handle it.
1754 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1758 switch (ISDOpcode) {
1759 default: return false;
1761 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1764 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1767 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1771 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1772 if (SrcReg1 == 0) return false;
1774 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1775 // in the instruction, rather then materializing the value in a register.
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1777 if (SrcReg2 == 0) return false;
1779 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1780 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1782 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1783 TII.get(Opc), ResultReg)
1784 .addReg(SrcReg1).addReg(SrcReg2));
1785 updateValueMap(I, ResultReg);
1789 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1790 EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1791 if (!FPVT.isSimple()) return false;
1792 MVT VT = FPVT.getSimpleVT();
1794 // FIXME: Support vector types where possible.
1798 // We can get here in the case when we want to use NEON for our fp
1799 // operations, but can't figure out how to. Just use the vfp instructions
1801 // FIXME: It'd be nice to use NEON instructions.
1802 Type *Ty = I->getType();
1803 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1805 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1809 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1810 switch (ISDOpcode) {
1811 default: return false;
1813 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1816 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1819 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1822 unsigned Op1 = getRegForValue(I->getOperand(0));
1823 if (Op1 == 0) return false;
1825 unsigned Op2 = getRegForValue(I->getOperand(1));
1826 if (Op2 == 0) return false;
1828 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1829 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1830 TII.get(Opc), ResultReg)
1831 .addReg(Op1).addReg(Op2));
1832 updateValueMap(I, ResultReg);
1836 // Call Handling Code
1838 // This is largely taken directly from CCAssignFnForNode
1839 // TODO: We may not support all of this.
1840 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1845 report_fatal_error("Unsupported calling convention");
1846 case CallingConv::Fast:
1847 if (Subtarget->hasVFP2Base() && !isVarArg) {
1848 if (!Subtarget->isAAPCS_ABI())
1849 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1850 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1851 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1854 case CallingConv::C:
1855 case CallingConv::CXX_FAST_TLS:
1856 // Use target triple & subtarget features to do actual dispatch.
1857 if (Subtarget->isAAPCS_ABI()) {
1858 if (Subtarget->hasVFP2Base() &&
1859 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1860 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1862 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1864 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1866 case CallingConv::ARM_AAPCS_VFP:
1867 case CallingConv::Swift:
1869 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1870 // Fall through to soft float variant, variadic functions don't
1871 // use hard floating point ABI.
1873 case CallingConv::ARM_AAPCS:
1874 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1875 case CallingConv::ARM_APCS:
1876 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1877 case CallingConv::GHC:
1879 report_fatal_error("Can't return in GHC call convention");
1881 return CC_ARM_APCS_GHC;
1882 case CallingConv::CFGuard_Check:
1883 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
1887 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1888 SmallVectorImpl<Register> &ArgRegs,
1889 SmallVectorImpl<MVT> &ArgVTs,
1890 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1891 SmallVectorImpl<Register> &RegArgs,
1895 SmallVector<CCValAssign, 16> ArgLocs;
1896 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1897 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1898 CCAssignFnForCall(CC, false, isVarArg));
1900 // Check that we can handle all of the arguments. If we can't, then bail out
1901 // now before we add code to the MBB.
1902 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1903 CCValAssign &VA = ArgLocs[i];
1904 MVT ArgVT = ArgVTs[VA.getValNo()];
1906 // We don't handle NEON/vector parameters yet.
1907 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1910 // Now copy/store arg to correct locations.
1911 if (VA.isRegLoc() && !VA.needsCustom()) {
1913 } else if (VA.needsCustom()) {
1914 // TODO: We need custom lowering for vector (v2f64) args.
1915 if (VA.getLocVT() != MVT::f64 ||
1916 // TODO: Only handle register args for now.
1917 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1920 switch (ArgVT.SimpleTy) {
1929 if (!Subtarget->hasVFP2Base())
1933 if (!Subtarget->hasVFP2Base())
1940 // At the point, we are able to handle the call's arguments in fast isel.
1942 // Get a count of how many bytes are to be pushed on the stack.
1943 NumBytes = CCInfo.getNextStackOffset();
1945 // Issue CALLSEQ_START
1946 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1947 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1948 TII.get(AdjStackDown))
1949 .addImm(NumBytes).addImm(0));
1951 // Process the args.
1952 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1953 CCValAssign &VA = ArgLocs[i];
1954 const Value *ArgVal = Args[VA.getValNo()];
1955 Register Arg = ArgRegs[VA.getValNo()];
1956 MVT ArgVT = ArgVTs[VA.getValNo()];
1958 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1959 "We don't handle NEON/vector parameters yet.");
1961 // Handle arg promotion, etc.
1962 switch (VA.getLocInfo()) {
1963 case CCValAssign::Full: break;
1964 case CCValAssign::SExt: {
1965 MVT DestVT = VA.getLocVT();
1966 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1967 assert(Arg != 0 && "Failed to emit a sext");
1971 case CCValAssign::AExt:
1972 // Intentional fall-through. Handle AExt and ZExt.
1973 case CCValAssign::ZExt: {
1974 MVT DestVT = VA.getLocVT();
1975 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1976 assert(Arg != 0 && "Failed to emit a zext");
1980 case CCValAssign::BCvt: {
1981 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1982 /*TODO: Kill=*/false);
1983 assert(BC != 0 && "Failed to emit a bitcast!");
1985 ArgVT = VA.getLocVT();
1988 default: llvm_unreachable("Unknown arg promotion!");
1991 // Now copy/store arg to correct locations.
1992 if (VA.isRegLoc() && !VA.needsCustom()) {
1993 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1994 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1995 RegArgs.push_back(VA.getLocReg());
1996 } else if (VA.needsCustom()) {
1997 // TODO: We need custom lowering for vector (v2f64) args.
1998 assert(VA.getLocVT() == MVT::f64 &&
1999 "Custom lowering for v2f64 args not available");
2001 // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
2002 CCValAssign &NextVA = ArgLocs[++i];
2004 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2005 "We only handle register args!");
2007 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2008 TII.get(ARM::VMOVRRD), VA.getLocReg())
2009 .addReg(NextVA.getLocReg(), RegState::Define)
2011 RegArgs.push_back(VA.getLocReg());
2012 RegArgs.push_back(NextVA.getLocReg());
2014 assert(VA.isMemLoc());
2015 // Need to store on the stack.
2017 // Don't emit stores for undef values.
2018 if (isa<UndefValue>(ArgVal))
2022 Addr.BaseType = Address::RegBase;
2023 Addr.Base.Reg = ARM::SP;
2024 Addr.Offset = VA.getLocMemOffset();
2026 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2027 assert(EmitRet && "Could not emit a store for argument!");
2034 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2035 const Instruction *I, CallingConv::ID CC,
2036 unsigned &NumBytes, bool isVarArg) {
2037 // Issue CALLSEQ_END
2038 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2039 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2040 TII.get(AdjStackUp))
2041 .addImm(NumBytes).addImm(0));
2043 // Now the return value.
2044 if (RetVT != MVT::isVoid) {
2045 SmallVector<CCValAssign, 16> RVLocs;
2046 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2047 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2049 // Copy all of the result registers out of their specified physreg.
2050 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2051 // For this move we copy into two registers and then move into the
2052 // double fp reg we want.
2053 MVT DestVT = RVLocs[0].getValVT();
2054 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2055 Register ResultReg = createResultReg(DstRC);
2056 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2057 TII.get(ARM::VMOVDRR), ResultReg)
2058 .addReg(RVLocs[0].getLocReg())
2059 .addReg(RVLocs[1].getLocReg()));
2061 UsedRegs.push_back(RVLocs[0].getLocReg());
2062 UsedRegs.push_back(RVLocs[1].getLocReg());
2064 // Finally update the result.
2065 updateValueMap(I, ResultReg);
2067 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2068 MVT CopyVT = RVLocs[0].getValVT();
2070 // Special handling for extended integers.
2071 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2074 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2076 Register ResultReg = createResultReg(DstRC);
2077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2078 TII.get(TargetOpcode::COPY),
2079 ResultReg).addReg(RVLocs[0].getLocReg());
2080 UsedRegs.push_back(RVLocs[0].getLocReg());
2082 // Finally update the result.
2083 updateValueMap(I, ResultReg);
2090 bool ARMFastISel::SelectRet(const Instruction *I) {
2091 const ReturnInst *Ret = cast<ReturnInst>(I);
2092 const Function &F = *I->getParent()->getParent();
2094 if (!FuncInfo.CanLowerReturn)
2097 if (TLI.supportSwiftError() &&
2098 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
2101 if (TLI.supportSplitCSR(FuncInfo.MF))
2104 // Build a list of return value registers.
2105 SmallVector<unsigned, 4> RetRegs;
2107 CallingConv::ID CC = F.getCallingConv();
2108 if (Ret->getNumOperands() > 0) {
2109 SmallVector<ISD::OutputArg, 4> Outs;
2110 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2112 // Analyze operands of the call, assigning locations to each operand.
2113 SmallVector<CCValAssign, 16> ValLocs;
2114 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2115 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2118 const Value *RV = Ret->getOperand(0);
2119 unsigned Reg = getRegForValue(RV);
2123 // Only handle a single return value for now.
2124 if (ValLocs.size() != 1)
2127 CCValAssign &VA = ValLocs[0];
2129 // Don't bother handling odd stuff for now.
2130 if (VA.getLocInfo() != CCValAssign::Full)
2132 // Only handle register returns for now.
2136 unsigned SrcReg = Reg + VA.getValNo();
2137 EVT RVEVT = TLI.getValueType(DL, RV->getType());
2138 if (!RVEVT.isSimple()) return false;
2139 MVT RVVT = RVEVT.getSimpleVT();
2140 MVT DestVT = VA.getValVT();
2141 // Special handling for extended integers.
2142 if (RVVT != DestVT) {
2143 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2146 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2148 // Perform extension if flagged as either zext or sext. Otherwise, do
2150 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2151 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2152 if (SrcReg == 0) return false;
2157 Register DstReg = VA.getLocReg();
2158 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2159 // Avoid a cross-class copy. This is very unlikely.
2160 if (!SrcRC->contains(DstReg))
2162 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2163 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2165 // Add register to return instruction.
2166 RetRegs.push_back(VA.getLocReg());
2169 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2170 TII.get(Subtarget->getReturnOpcode()));
2171 AddOptionalDefs(MIB);
2172 for (unsigned R : RetRegs)
2173 MIB.addReg(R, RegState::Implicit);
2177 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2179 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2181 return isThumb2 ? ARM::tBL : ARM::BL;
2184 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2185 // Manually compute the global's type to avoid building it when unnecessary.
2186 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2187 EVT LCREVT = TLI.getValueType(DL, GVTy);
2188 if (!LCREVT.isSimple()) return 0;
2190 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2191 GlobalValue::ExternalLinkage, nullptr,
2193 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2194 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2197 // A quick function that will emit a call for a named libcall in F with the
2198 // vector of passed arguments for the Instruction in I. We can assume that we
2199 // can emit a call for any libcall we can produce. This is an abridged version
2200 // of the full call infrastructure since we won't need to worry about things
2201 // like computed function pointers or strange arguments at call sites.
2202 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2204 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2205 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2207 // Handle *simple* calls for now.
2208 Type *RetTy = I->getType();
2210 if (RetTy->isVoidTy())
2211 RetVT = MVT::isVoid;
2212 else if (!isTypeLegal(RetTy, RetVT))
2215 // Can't handle non-double multi-reg retvals.
2216 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2217 SmallVector<CCValAssign, 16> RVLocs;
2218 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2219 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2220 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2224 // Set up the argument vectors.
2225 SmallVector<Value*, 8> Args;
2226 SmallVector<Register, 8> ArgRegs;
2227 SmallVector<MVT, 8> ArgVTs;
2228 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2229 Args.reserve(I->getNumOperands());
2230 ArgRegs.reserve(I->getNumOperands());
2231 ArgVTs.reserve(I->getNumOperands());
2232 ArgFlags.reserve(I->getNumOperands());
2233 for (Value *Op : I->operands()) {
2234 unsigned Arg = getRegForValue(Op);
2235 if (Arg == 0) return false;
2237 Type *ArgTy = Op->getType();
2239 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2241 ISD::ArgFlagsTy Flags;
2242 Flags.setOrigAlign(Align(DL.getABITypeAlignment(ArgTy)));
2245 ArgRegs.push_back(Arg);
2246 ArgVTs.push_back(ArgVT);
2247 ArgFlags.push_back(Flags);
2250 // Handle the arguments now that we've gotten them.
2251 SmallVector<Register, 4> RegArgs;
2253 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2254 RegArgs, CC, NumBytes, false))
2258 if (Subtarget->genLongCalls()) {
2259 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2260 if (CalleeReg == 0) return false;
2264 unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2265 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2266 DbgLoc, TII.get(CallOpc));
2267 // BL / BLX don't take a predicate, but tBL / tBLX do.
2269 MIB.add(predOps(ARMCC::AL));
2270 if (Subtarget->genLongCalls())
2271 MIB.addReg(CalleeReg);
2273 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2275 // Add implicit physical register uses to the call.
2276 for (Register R : RegArgs)
2277 MIB.addReg(R, RegState::Implicit);
2279 // Add a register mask with the call-preserved registers.
2280 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2281 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2283 // Finish off the call including any return values.
2284 SmallVector<Register, 4> UsedRegs;
2285 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2287 // Set all unused physreg defs as dead.
2288 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2293 bool ARMFastISel::SelectCall(const Instruction *I,
2294 const char *IntrMemName = nullptr) {
2295 const CallInst *CI = cast<CallInst>(I);
2296 const Value *Callee = CI->getCalledValue();
2298 // Can't handle inline asm.
2299 if (isa<InlineAsm>(Callee)) return false;
2301 // Allow SelectionDAG isel to handle tail calls.
2302 if (CI->isTailCall()) return false;
2304 // Check the calling convention.
2305 ImmutableCallSite CS(CI);
2306 CallingConv::ID CC = CS.getCallingConv();
2308 // TODO: Avoid some calling conventions?
2310 FunctionType *FTy = CS.getFunctionType();
2311 bool isVarArg = FTy->isVarArg();
2313 // Handle *simple* calls for now.
2314 Type *RetTy = I->getType();
2316 if (RetTy->isVoidTy())
2317 RetVT = MVT::isVoid;
2318 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2319 RetVT != MVT::i8 && RetVT != MVT::i1)
2322 // Can't handle non-double multi-reg retvals.
2323 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2324 RetVT != MVT::i16 && RetVT != MVT::i32) {
2325 SmallVector<CCValAssign, 16> RVLocs;
2326 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2327 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2328 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2332 // Set up the argument vectors.
2333 SmallVector<Value*, 8> Args;
2334 SmallVector<Register, 8> ArgRegs;
2335 SmallVector<MVT, 8> ArgVTs;
2336 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2337 unsigned arg_size = CS.arg_size();
2338 Args.reserve(arg_size);
2339 ArgRegs.reserve(arg_size);
2340 ArgVTs.reserve(arg_size);
2341 ArgFlags.reserve(arg_size);
2342 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2344 // If we're lowering a memory intrinsic instead of a regular call, skip the
2345 // last argument, which shouldn't be passed to the underlying function.
2346 if (IntrMemName && e - i <= 1)
2349 ISD::ArgFlagsTy Flags;
2350 unsigned ArgIdx = i - CS.arg_begin();
2351 if (CS.paramHasAttr(ArgIdx, Attribute::SExt))
2353 if (CS.paramHasAttr(ArgIdx, Attribute::ZExt))
2356 // FIXME: Only handle *easy* calls for now.
2357 if (CS.paramHasAttr(ArgIdx, Attribute::InReg) ||
2358 CS.paramHasAttr(ArgIdx, Attribute::StructRet) ||
2359 CS.paramHasAttr(ArgIdx, Attribute::SwiftSelf) ||
2360 CS.paramHasAttr(ArgIdx, Attribute::SwiftError) ||
2361 CS.paramHasAttr(ArgIdx, Attribute::Nest) ||
2362 CS.paramHasAttr(ArgIdx, Attribute::ByVal))
2365 Type *ArgTy = (*i)->getType();
2367 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2371 Register Arg = getRegForValue(*i);
2375 Flags.setOrigAlign(Align(DL.getABITypeAlignment(ArgTy)));
2378 ArgRegs.push_back(Arg);
2379 ArgVTs.push_back(ArgVT);
2380 ArgFlags.push_back(Flags);
2383 // Handle the arguments now that we've gotten them.
2384 SmallVector<Register, 4> RegArgs;
2386 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2387 RegArgs, CC, NumBytes, isVarArg))
2390 bool UseReg = false;
2391 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2392 if (!GV || Subtarget->genLongCalls()) UseReg = true;
2397 CalleeReg = getLibcallReg(IntrMemName);
2399 CalleeReg = getRegForValue(Callee);
2401 if (CalleeReg == 0) return false;
2405 unsigned CallOpc = ARMSelectCallOp(UseReg);
2406 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2407 DbgLoc, TII.get(CallOpc));
2409 // ARM calls don't take a predicate, but tBL / tBLX do.
2411 MIB.add(predOps(ARMCC::AL));
2413 MIB.addReg(CalleeReg);
2414 else if (!IntrMemName)
2415 MIB.addGlobalAddress(GV, 0, 0);
2417 MIB.addExternalSymbol(IntrMemName, 0);
2419 // Add implicit physical register uses to the call.
2420 for (Register R : RegArgs)
2421 MIB.addReg(R, RegState::Implicit);
2423 // Add a register mask with the call-preserved registers.
2424 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2425 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2427 // Finish off the call including any return values.
2428 SmallVector<Register, 4> UsedRegs;
2429 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2432 // Set all unused physreg defs as dead.
2433 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2438 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2442 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2443 uint64_t Len, unsigned Alignment) {
2444 // Make sure we don't bloat code by inlining very large memcpy's.
2445 if (!ARMIsMemCpySmall(Len))
2450 if (!Alignment || Alignment >= 4) {
2456 assert(Len == 1 && "Expected a length of 1!");
2460 // Bound based on alignment.
2461 if (Len >= 2 && Alignment == 2)
2470 RV = ARMEmitLoad(VT, ResultReg, Src);
2471 assert(RV && "Should be able to handle this load.");
2472 RV = ARMEmitStore(VT, ResultReg, Dest);
2473 assert(RV && "Should be able to handle this store.");
2476 unsigned Size = VT.getSizeInBits()/8;
2478 Dest.Offset += Size;
2485 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2486 // FIXME: Handle more intrinsics.
2487 switch (I.getIntrinsicID()) {
2488 default: return false;
2489 case Intrinsic::frameaddress: {
2490 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
2491 MFI.setFrameAddressIsTaken(true);
2493 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2494 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2495 : &ARM::GPRRegClass;
2497 const ARMBaseRegisterInfo *RegInfo =
2498 static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2499 Register FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2500 unsigned SrcReg = FramePtr;
2502 // Recursively load frame address
2508 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2510 DestReg = createResultReg(RC);
2511 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2512 TII.get(LdrOpc), DestReg)
2513 .addReg(SrcReg).addImm(0));
2516 updateValueMap(&I, SrcReg);
2519 case Intrinsic::memcpy:
2520 case Intrinsic::memmove: {
2521 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2522 // Don't handle volatile.
2523 if (MTI.isVolatile())
2526 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2527 // we would emit dead code because we don't currently handle memmoves.
2528 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2529 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2530 // Small memcpy's are common enough that we want to do them without a call
2532 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2533 if (ARMIsMemCpySmall(Len)) {
2535 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2536 !ARMComputeAddress(MTI.getRawSource(), Src))
2538 unsigned Alignment = MinAlign(MTI.getDestAlignment(),
2539 MTI.getSourceAlignment());
2540 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2545 if (!MTI.getLength()->getType()->isIntegerTy(32))
2548 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2551 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2552 return SelectCall(&I, IntrMemName);
2554 case Intrinsic::memset: {
2555 const MemSetInst &MSI = cast<MemSetInst>(I);
2556 // Don't handle volatile.
2557 if (MSI.isVolatile())
2560 if (!MSI.getLength()->getType()->isIntegerTy(32))
2563 if (MSI.getDestAddressSpace() > 255)
2566 return SelectCall(&I, "memset");
2568 case Intrinsic::trap: {
2570 if (Subtarget->isThumb())
2571 Opcode = ARM::tTRAP;
2573 Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
2574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode));
2580 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2581 // The high bits for a type smaller than the register size are assumed to be
2583 Value *Op = I->getOperand(0);
2586 SrcVT = TLI.getValueType(DL, Op->getType(), true);
2587 DestVT = TLI.getValueType(DL, I->getType(), true);
2589 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2591 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2594 unsigned SrcReg = getRegForValue(Op);
2595 if (!SrcReg) return false;
2597 // Because the high bits are undefined, a truncate doesn't generate
2599 updateValueMap(I, SrcReg);
2603 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2605 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2607 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2610 // Table of which combinations can be emitted as a single instruction,
2611 // and which will require two.
2612 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2614 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2615 // ext: s z s z s z s z
2616 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2617 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2618 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2621 // Target registers for:
2622 // - For ARM can never be PC.
2623 // - For 16-bit Thumb are restricted to lower 8 registers.
2624 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2625 static const TargetRegisterClass *RCTbl[2][2] = {
2626 // Instructions: Two Single
2627 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2628 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2631 // Table governing the instruction(s) to be emitted.
2632 static const struct InstructionTable {
2634 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2635 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2636 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2637 } IT[2][2][3][2] = {
2638 { // Two instructions (first is left shift, second is in this table).
2639 { // ARM Opc S Shift Imm
2640 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2641 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2642 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2643 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2644 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2645 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2647 { // Thumb Opc S Shift Imm
2648 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2649 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2650 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2651 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2652 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2653 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2656 { // Single instruction.
2657 { // ARM Opc S Shift Imm
2658 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2659 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2660 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2661 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2662 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2663 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2665 { // Thumb Opc S Shift Imm
2666 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2667 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2668 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2669 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2670 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2671 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2676 unsigned SrcBits = SrcVT.getSizeInBits();
2677 unsigned DestBits = DestVT.getSizeInBits();
2679 assert((SrcBits < DestBits) && "can only extend to larger types");
2680 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2681 "other sizes unimplemented");
2682 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2683 "other sizes unimplemented");
2685 bool hasV6Ops = Subtarget->hasV6Ops();
2686 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2687 assert((Bitness < 3) && "sanity-check table bounds");
2689 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2690 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2691 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2692 unsigned Opc = ITP->Opc;
2693 assert(ARM::KILL != Opc && "Invalid table entry");
2694 unsigned hasS = ITP->hasS;
2695 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2696 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2697 "only MOVsi has shift operand addressing mode");
2698 unsigned Imm = ITP->Imm;
2700 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2701 bool setsCPSR = &ARM::tGPRRegClass == RC;
2702 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2704 // MOVsi encodes shift and immediate in shift operand addressing mode.
2705 // The following condition has the same value when emitting two
2706 // instruction sequences: both are shifts.
2707 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2709 // Either one or two instructions are emitted.
2710 // They're always of the form:
2712 // CPSR is set only by 16-bit Thumb instructions.
2713 // Predicate, if any, is AL.
2714 // S bit, if available, is always 0.
2715 // When two are emitted the first's result will feed as the second's input,
2716 // that value is then dead.
2717 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2718 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2719 ResultReg = createResultReg(RC);
2720 bool isLsl = (0 == Instr) && !isSingleInstr;
2721 unsigned Opcode = isLsl ? LSLOpc : Opc;
2722 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2723 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2724 bool isKill = 1 == Instr;
2725 MachineInstrBuilder MIB = BuildMI(
2726 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2728 MIB.addReg(ARM::CPSR, RegState::Define);
2729 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2730 MIB.addReg(SrcReg, isKill * RegState::Kill)
2732 .add(predOps(ARMCC::AL));
2734 MIB.add(condCodeOp());
2735 // Second instruction consumes the first's result.
2742 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2743 // On ARM, in general, integer casts don't involve legal types; this code
2744 // handles promotable integers.
2745 Type *DestTy = I->getType();
2746 Value *Src = I->getOperand(0);
2747 Type *SrcTy = Src->getType();
2749 bool isZExt = isa<ZExtInst>(I);
2750 unsigned SrcReg = getRegForValue(Src);
2751 if (!SrcReg) return false;
2753 EVT SrcEVT, DestEVT;
2754 SrcEVT = TLI.getValueType(DL, SrcTy, true);
2755 DestEVT = TLI.getValueType(DL, DestTy, true);
2756 if (!SrcEVT.isSimple()) return false;
2757 if (!DestEVT.isSimple()) return false;
2759 MVT SrcVT = SrcEVT.getSimpleVT();
2760 MVT DestVT = DestEVT.getSimpleVT();
2761 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2762 if (ResultReg == 0) return false;
2763 updateValueMap(I, ResultReg);
2767 bool ARMFastISel::SelectShift(const Instruction *I,
2768 ARM_AM::ShiftOpc ShiftTy) {
2769 // We handle thumb2 mode by target independent selector
2770 // or SelectionDAG ISel.
2774 // Only handle i32 now.
2775 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2776 if (DestVT != MVT::i32)
2779 unsigned Opc = ARM::MOVsr;
2781 Value *Src2Value = I->getOperand(1);
2782 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2783 ShiftImm = CI->getZExtValue();
2785 // Fall back to selection DAG isel if the shift amount
2786 // is zero or greater than the width of the value type.
2787 if (ShiftImm == 0 || ShiftImm >=32)
2793 Value *Src1Value = I->getOperand(0);
2794 unsigned Reg1 = getRegForValue(Src1Value);
2795 if (Reg1 == 0) return false;
2798 if (Opc == ARM::MOVsr) {
2799 Reg2 = getRegForValue(Src2Value);
2800 if (Reg2 == 0) return false;
2803 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2804 if(ResultReg == 0) return false;
2806 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2807 TII.get(Opc), ResultReg)
2810 if (Opc == ARM::MOVsi)
2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2812 else if (Opc == ARM::MOVsr) {
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2817 AddOptionalDefs(MIB);
2818 updateValueMap(I, ResultReg);
2822 // TODO: SoftFP support.
2823 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2824 switch (I->getOpcode()) {
2825 case Instruction::Load:
2826 return SelectLoad(I);
2827 case Instruction::Store:
2828 return SelectStore(I);
2829 case Instruction::Br:
2830 return SelectBranch(I);
2831 case Instruction::IndirectBr:
2832 return SelectIndirectBr(I);
2833 case Instruction::ICmp:
2834 case Instruction::FCmp:
2835 return SelectCmp(I);
2836 case Instruction::FPExt:
2837 return SelectFPExt(I);
2838 case Instruction::FPTrunc:
2839 return SelectFPTrunc(I);
2840 case Instruction::SIToFP:
2841 return SelectIToFP(I, /*isSigned*/ true);
2842 case Instruction::UIToFP:
2843 return SelectIToFP(I, /*isSigned*/ false);
2844 case Instruction::FPToSI:
2845 return SelectFPToI(I, /*isSigned*/ true);
2846 case Instruction::FPToUI:
2847 return SelectFPToI(I, /*isSigned*/ false);
2848 case Instruction::Add:
2849 return SelectBinaryIntOp(I, ISD::ADD);
2850 case Instruction::Or:
2851 return SelectBinaryIntOp(I, ISD::OR);
2852 case Instruction::Sub:
2853 return SelectBinaryIntOp(I, ISD::SUB);
2854 case Instruction::FAdd:
2855 return SelectBinaryFPOp(I, ISD::FADD);
2856 case Instruction::FSub:
2857 return SelectBinaryFPOp(I, ISD::FSUB);
2858 case Instruction::FMul:
2859 return SelectBinaryFPOp(I, ISD::FMUL);
2860 case Instruction::SDiv:
2861 return SelectDiv(I, /*isSigned*/ true);
2862 case Instruction::UDiv:
2863 return SelectDiv(I, /*isSigned*/ false);
2864 case Instruction::SRem:
2865 return SelectRem(I, /*isSigned*/ true);
2866 case Instruction::URem:
2867 return SelectRem(I, /*isSigned*/ false);
2868 case Instruction::Call:
2869 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2870 return SelectIntrinsicCall(*II);
2871 return SelectCall(I);
2872 case Instruction::Select:
2873 return SelectSelect(I);
2874 case Instruction::Ret:
2875 return SelectRet(I);
2876 case Instruction::Trunc:
2877 return SelectTrunc(I);
2878 case Instruction::ZExt:
2879 case Instruction::SExt:
2880 return SelectIntExt(I);
2881 case Instruction::Shl:
2882 return SelectShift(I, ARM_AM::lsl);
2883 case Instruction::LShr:
2884 return SelectShift(I, ARM_AM::lsr);
2885 case Instruction::AShr:
2886 return SelectShift(I, ARM_AM::asr);
2892 // This table describes sign- and zero-extend instructions which can be
2893 // folded into a preceding load. All of these extends have an immediate
2894 // (sometimes a mask and sometimes a shift) that's applied after
2896 static const struct FoldableLoadExtendsStruct {
2897 uint16_t Opc[2]; // ARM, Thumb.
2898 uint8_t ExpectedImm;
2900 uint8_t ExpectedVT : 7;
2901 } FoldableLoadExtends[] = {
2902 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2903 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2904 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2905 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2906 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2909 /// The specified machine instr operand is a vreg, and that
2910 /// vreg is being provided by the specified load instruction. If possible,
2911 /// try to fold the load as an operand to the instruction, returning true if
2913 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2914 const LoadInst *LI) {
2915 // Verify we have a legal type before going any further.
2917 if (!isLoadTypeLegal(LI->getType(), VT))
2920 // Combine load followed by zero- or sign-extend.
2921 // ldrb r1, [r0] ldrb r1, [r0]
2923 // mov r3, r2 mov r3, r1
2924 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2926 const uint64_t Imm = MI->getOperand(2).getImm();
2930 for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
2931 if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2932 (uint64_t)FLE.ExpectedImm == Imm &&
2933 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
2935 isZExt = FLE.isZExt;
2938 if (!Found) return false;
2940 // See if we can handle this address.
2942 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2944 Register ResultReg = MI->getOperand(0).getReg();
2945 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2947 MachineBasicBlock::iterator I(MI);
2948 removeDeadCode(I, std::next(I));
2952 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2953 unsigned Align, MVT VT) {
2954 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
2956 LLVMContext *Context = &MF->getFunction().getContext();
2957 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2958 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2959 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
2960 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
2961 UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
2962 /*AddCurrentAddress=*/UseGOT_PREL);
2964 unsigned ConstAlign =
2965 MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
2966 unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);
2967 MachineMemOperand *CPMMO =
2968 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
2969 MachineMemOperand::MOLoad, 4, 4);
2971 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
2972 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
2973 MachineInstrBuilder MIB =
2974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2975 .addConstantPoolIndex(Idx)
2976 .addMemOperand(CPMMO);
2977 if (Opc == ARM::LDRcp)
2979 MIB.add(predOps(ARMCC::AL));
2981 // Fix the address by adding pc.
2982 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
2983 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
2985 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2986 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2988 .addImm(ARMPCLabelIndex);
2990 if (!Subtarget->isThumb())
2991 MIB.add(predOps(ARMCC::AL));
2993 if (UseGOT_PREL && Subtarget->isThumb()) {
2994 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
2995 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2996 TII.get(ARM::t2LDRi12), NewDestReg)
2999 DestReg = NewDestReg;
3000 AddOptionalDefs(MIB);
3005 bool ARMFastISel::fastLowerArguments() {
3006 if (!FuncInfo.CanLowerReturn)
3009 const Function *F = FuncInfo.Fn;
3013 CallingConv::ID CC = F->getCallingConv();
3017 case CallingConv::Fast:
3018 case CallingConv::C:
3019 case CallingConv::ARM_AAPCS_VFP:
3020 case CallingConv::ARM_AAPCS:
3021 case CallingConv::ARM_APCS:
3022 case CallingConv::Swift:
3026 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3027 // which are passed in r0 - r3.
3028 for (const Argument &Arg : F->args()) {
3029 if (Arg.getArgNo() >= 4)
3032 if (Arg.hasAttribute(Attribute::InReg) ||
3033 Arg.hasAttribute(Attribute::StructRet) ||
3034 Arg.hasAttribute(Attribute::SwiftSelf) ||
3035 Arg.hasAttribute(Attribute::SwiftError) ||
3036 Arg.hasAttribute(Attribute::ByVal))
3039 Type *ArgTy = Arg.getType();
3040 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3043 EVT ArgVT = TLI.getValueType(DL, ArgTy);
3044 if (!ArgVT.isSimple()) return false;
3045 switch (ArgVT.getSimpleVT().SimpleTy) {
3055 static const MCPhysReg GPRArgRegs[] = {
3056 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3059 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3060 for (const Argument &Arg : F->args()) {
3061 unsigned ArgNo = Arg.getArgNo();
3062 unsigned SrcReg = GPRArgRegs[ArgNo];
3063 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3064 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3065 // Without this, EmitLiveInCopies may eliminate the livein if its only
3066 // use is a bitcast (which isn't turned into an instruction).
3067 unsigned ResultReg = createResultReg(RC);
3068 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3069 TII.get(TargetOpcode::COPY),
3070 ResultReg).addReg(DstReg, getKillRegState(true));
3071 updateValueMap(&Arg, ResultReg);
3079 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3080 const TargetLibraryInfo *libInfo) {
3081 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3082 return new ARMFastISel(funcInfo, libInfo);
3087 } // end namespace llvm