1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file implements the targeting of the InstructionSelector class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
13 #include "ARMRegisterBankInfo.h"
14 #include "ARMSubtarget.h"
15 #include "ARMTargetMachine.h"
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/IntrinsicsARM.h"
21 #include "llvm/Support/Debug.h"
23 #define DEBUG_TYPE "arm-isel"
29 #define GET_GLOBALISEL_PREDICATE_BITSET
30 #include "ARMGenGlobalISel.inc"
31 #undef GET_GLOBALISEL_PREDICATE_BITSET
33 class ARMInstructionSelector : public InstructionSelector {
35 ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
36 const ARMRegisterBankInfo &RBI);
38 bool select(MachineInstr &I) override;
39 static const char *getName() { return DEBUG_TYPE; }
42 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
48 MachineRegisterInfo &MRI) const;
50 // Helper for inserting a comparison sequence that sets \p ResReg to either 1
51 // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
52 // \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
53 bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
55 unsigned PrevRes) const;
57 // Set \p DestReg to \p Constant.
58 void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
64 // Check if the types match and both operands have the expected size and
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
67 unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
69 // Check if the register has the expected size and register bank.
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
71 unsigned ExpectedRegBankID) const;
73 const ARMBaseInstrInfo &TII;
74 const ARMBaseRegisterInfo &TRI;
75 const ARMBaseTargetMachine &TM;
76 const ARMRegisterBankInfo &RBI;
77 const ARMSubtarget &STI;
79 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
80 // uses "STI." in the code generated by TableGen. If we want to reuse some of
81 // the custom C++ predicates written for DAGISel, we need to have both around.
82 const ARMSubtarget *Subtarget = &STI;
84 // Store the opcodes that we might need, so we don't have to check what kind
85 // of subtarget (ARM vs Thumb) we have all the time.
93 // Used for implementing ZEXT/SEXT from i1
120 // Used for G_GLOBAL_VALUE
122 unsigned ConstPoolLoad;
123 unsigned MOV_ga_pcrel;
124 unsigned LDRLIT_ga_pcrel;
125 unsigned LDRLIT_ga_abs;
127 OpcodeCache(const ARMSubtarget &STI);
130 // Select the opcode for simple extensions (that translate to a single SXT/UXT
131 // instruction). Extension operations more complicated than that should not
132 // invoke this. Returns the original opcode if it doesn't know how to select a
134 unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) const;
136 // Select the opcode for simple loads and stores. Returns the original opcode
137 // if it doesn't know how to select a better one.
138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
139 unsigned Size) const;
141 void renderVFPF32Imm(MachineInstrBuilder &New, const MachineInstr &Old,
142 int OpIdx = -1) const;
143 void renderVFPF64Imm(MachineInstrBuilder &New, const MachineInstr &Old,
144 int OpIdx = -1) const;
146 #define GET_GLOBALISEL_PREDICATES_DECL
147 #include "ARMGenGlobalISel.inc"
148 #undef GET_GLOBALISEL_PREDICATES_DECL
150 // We declare the temporaries used by selectImpl() in the class to minimize the
151 // cost of constructing placeholder values.
152 #define GET_GLOBALISEL_TEMPORARIES_DECL
153 #include "ARMGenGlobalISel.inc"
154 #undef GET_GLOBALISEL_TEMPORARIES_DECL
156 } // end anonymous namespace
159 InstructionSelector *
160 createARMInstructionSelector(const ARMBaseTargetMachine &TM,
161 const ARMSubtarget &STI,
162 const ARMRegisterBankInfo &RBI) {
163 return new ARMInstructionSelector(TM, STI, RBI);
167 const unsigned zero_reg = 0;
169 #define GET_GLOBALISEL_IMPL
170 #include "ARMGenGlobalISel.inc"
171 #undef GET_GLOBALISEL_IMPL
173 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
174 const ARMSubtarget &STI,
175 const ARMRegisterBankInfo &RBI)
176 : InstructionSelector(), TII(*STI.getInstrInfo()),
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
178 #define GET_GLOBALISEL_PREDICATES_INIT
179 #include "ARMGenGlobalISel.inc"
180 #undef GET_GLOBALISEL_PREDICATES_INIT
181 #define GET_GLOBALISEL_TEMPORARIES_INIT
182 #include "ARMGenGlobalISel.inc"
183 #undef GET_GLOBALISEL_TEMPORARIES_INIT
187 static const TargetRegisterClass *guessRegClass(unsigned Reg,
188 MachineRegisterInfo &MRI,
189 const TargetRegisterInfo &TRI,
190 const RegisterBankInfo &RBI) {
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
192 assert(RegBank && "Can't get reg bank for virtual register");
194 const unsigned Size = MRI.getType(Reg).getSizeInBits();
195 assert((RegBank->getID() == ARM::GPRRegBankID ||
196 RegBank->getID() == ARM::FPRRegBankID) &&
197 "Unsupported reg bank");
199 if (RegBank->getID() == ARM::FPRRegBankID) {
201 return &ARM::SPRRegClass;
203 return &ARM::DPRRegClass;
204 else if (Size == 128)
205 return &ARM::QPRRegClass;
207 llvm_unreachable("Unsupported destination size");
210 return &ARM::GPRRegClass;
213 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
214 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
215 const RegisterBankInfo &RBI) {
216 Register DstReg = I.getOperand(0).getReg();
217 if (Register::isPhysicalRegister(DstReg))
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
222 // No need to constrain SrcReg. It will get constrained when
223 // we hit another of its uses or its defs.
224 // Copies do not have constraints.
225 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
226 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
233 static bool selectMergeValues(MachineInstrBuilder &MIB,
234 const ARMBaseInstrInfo &TII,
235 MachineRegisterInfo &MRI,
236 const TargetRegisterInfo &TRI,
237 const RegisterBankInfo &RBI) {
238 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP");
240 // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
242 Register VReg0 = MIB->getOperand(0).getReg();
244 assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
246 "Unsupported operand for G_MERGE_VALUES");
247 Register VReg1 = MIB->getOperand(1).getReg();
249 assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
251 "Unsupported operand for G_MERGE_VALUES");
252 Register VReg2 = MIB->getOperand(2).getReg();
254 assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
256 "Unsupported operand for G_MERGE_VALUES");
258 MIB->setDesc(TII.get(ARM::VMOVDRR));
259 MIB.add(predOps(ARMCC::AL));
264 static bool selectUnmergeValues(MachineInstrBuilder &MIB,
265 const ARMBaseInstrInfo &TII,
266 MachineRegisterInfo &MRI,
267 const TargetRegisterInfo &TRI,
268 const RegisterBankInfo &RBI) {
269 assert(TII.getSubtarget().hasVFP2Base() &&
270 "Can't select unmerge without VFP");
272 // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
274 Register VReg0 = MIB->getOperand(0).getReg();
276 assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
278 "Unsupported operand for G_UNMERGE_VALUES");
279 Register VReg1 = MIB->getOperand(1).getReg();
281 assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
283 "Unsupported operand for G_UNMERGE_VALUES");
284 Register VReg2 = MIB->getOperand(2).getReg();
286 assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
288 "Unsupported operand for G_UNMERGE_VALUES");
290 MIB->setDesc(TII.get(ARM::VMOVRRD));
291 MIB.add(predOps(ARMCC::AL));
296 ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
297 bool isThumb = STI.isThumb();
299 using namespace TargetOpcode;
301 #define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC
302 STORE_OPCODE(SEXT16, SXTH);
303 STORE_OPCODE(ZEXT16, UXTH);
305 STORE_OPCODE(SEXT8, SXTB);
306 STORE_OPCODE(ZEXT8, UXTB);
308 STORE_OPCODE(AND, ANDri);
309 STORE_OPCODE(RSB, RSBri);
311 STORE_OPCODE(STORE32, STRi12);
312 STORE_OPCODE(LOAD32, LDRi12);
314 // LDRH/STRH are special...
315 STORE16 = isThumb ? ARM::t2STRHi12 : ARM::STRH;
316 LOAD16 = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
318 STORE_OPCODE(STORE8, STRBi12);
319 STORE_OPCODE(LOAD8, LDRBi12);
321 STORE_OPCODE(ADDrr, ADDrr);
322 STORE_OPCODE(ADDri, ADDri);
324 STORE_OPCODE(CMPrr, CMPrr);
325 STORE_OPCODE(MOVi, MOVi);
326 STORE_OPCODE(MOVCCi, MOVCCi);
328 STORE_OPCODE(MOVCCr, MOVCCr);
330 STORE_OPCODE(TSTri, TSTri);
331 STORE_OPCODE(Bcc, Bcc);
333 STORE_OPCODE(MOVi32imm, MOVi32imm);
334 ConstPoolLoad = isThumb ? ARM::t2LDRpci : ARM::LDRi12;
335 STORE_OPCODE(MOV_ga_pcrel, MOV_ga_pcrel);
336 LDRLIT_ga_pcrel = isThumb ? ARM::tLDRLIT_ga_pcrel : ARM::LDRLIT_ga_pcrel;
337 LDRLIT_ga_abs = isThumb ? ARM::tLDRLIT_ga_abs : ARM::LDRLIT_ga_abs;
341 unsigned ARMInstructionSelector::selectSimpleExtOpc(unsigned Opc,
342 unsigned Size) const {
343 using namespace TargetOpcode;
345 if (Size != 8 && Size != 16)
349 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
352 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
357 unsigned ARMInstructionSelector::selectLoadStoreOpCode(unsigned Opc,
359 unsigned Size) const {
360 bool isStore = Opc == TargetOpcode::G_STORE;
362 if (RegBank == ARM::GPRRegBankID) {
366 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
368 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
370 return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
376 if (RegBank == ARM::FPRRegBankID) {
379 return isStore ? ARM::VSTRS : ARM::VLDRS;
381 return isStore ? ARM::VSTRD : ARM::VLDRD;
390 // When lowering comparisons, we sometimes need to perform two compares instead
391 // of just one. Get the condition codes for both comparisons. If only one is
392 // needed, the second member of the pair is ARMCC::AL.
393 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
394 getComparePreds(CmpInst::Predicate Pred) {
395 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
397 case CmpInst::FCMP_ONE:
398 Preds = {ARMCC::GT, ARMCC::MI};
400 case CmpInst::FCMP_UEQ:
401 Preds = {ARMCC::EQ, ARMCC::VS};
403 case CmpInst::ICMP_EQ:
404 case CmpInst::FCMP_OEQ:
405 Preds.first = ARMCC::EQ;
407 case CmpInst::ICMP_SGT:
408 case CmpInst::FCMP_OGT:
409 Preds.first = ARMCC::GT;
411 case CmpInst::ICMP_SGE:
412 case CmpInst::FCMP_OGE:
413 Preds.first = ARMCC::GE;
415 case CmpInst::ICMP_UGT:
416 case CmpInst::FCMP_UGT:
417 Preds.first = ARMCC::HI;
419 case CmpInst::FCMP_OLT:
420 Preds.first = ARMCC::MI;
422 case CmpInst::ICMP_ULE:
423 case CmpInst::FCMP_OLE:
424 Preds.first = ARMCC::LS;
426 case CmpInst::FCMP_ORD:
427 Preds.first = ARMCC::VC;
429 case CmpInst::FCMP_UNO:
430 Preds.first = ARMCC::VS;
432 case CmpInst::FCMP_UGE:
433 Preds.first = ARMCC::PL;
435 case CmpInst::ICMP_SLT:
436 case CmpInst::FCMP_ULT:
437 Preds.first = ARMCC::LT;
439 case CmpInst::ICMP_SLE:
440 case CmpInst::FCMP_ULE:
441 Preds.first = ARMCC::LE;
443 case CmpInst::FCMP_UNE:
444 case CmpInst::ICMP_NE:
445 Preds.first = ARMCC::NE;
447 case CmpInst::ICMP_UGE:
448 Preds.first = ARMCC::HS;
450 case CmpInst::ICMP_ULT:
451 Preds.first = ARMCC::LO;
456 assert(Preds.first != ARMCC::AL && "No comparisons needed?");
460 struct ARMInstructionSelector::CmpConstants {
461 CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode,
462 unsigned OpRegBank, unsigned OpSize)
463 : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
464 SelectResultOpcode(SelectOpcode), OperandRegBankID(OpRegBank),
465 OperandSize(OpSize) {}
467 // The opcode used for performing the comparison.
468 const unsigned ComparisonOpcode;
470 // The opcode used for reading the flags set by the comparison. May be
471 // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
472 const unsigned ReadFlagsOpcode;
474 // The opcode used for materializing the result of the comparison.
475 const unsigned SelectResultOpcode;
477 // The assumed register bank ID for the operands.
478 const unsigned OperandRegBankID;
480 // The assumed size in bits for the operands.
481 const unsigned OperandSize;
484 struct ARMInstructionSelector::InsertInfo {
485 InsertInfo(MachineInstrBuilder &MIB)
486 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
487 DbgLoc(MIB->getDebugLoc()) {}
489 MachineBasicBlock &MBB;
490 const MachineBasicBlock::instr_iterator InsertBefore;
491 const DebugLoc &DbgLoc;
494 void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
495 unsigned Constant) const {
496 (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Opcodes.MOVi))
499 .add(predOps(ARMCC::AL))
503 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
504 unsigned LHSReg, unsigned RHSReg,
505 unsigned ExpectedSize,
506 unsigned ExpectedRegBankID) const {
507 return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
508 validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
509 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
512 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
513 unsigned ExpectedSize,
514 unsigned ExpectedRegBankID) const {
515 if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
516 LLVM_DEBUG(dbgs() << "Unexpected size for register");
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
521 LLVM_DEBUG(dbgs() << "Unexpected register bank for register");
528 bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
529 MachineInstrBuilder &MIB,
530 MachineRegisterInfo &MRI) const {
531 const InsertInfo I(MIB);
533 auto ResReg = MIB->getOperand(0).getReg();
534 if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
538 static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
539 if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
540 putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
541 MIB->eraseFromParent();
545 auto LHSReg = MIB->getOperand(2).getReg();
546 auto RHSReg = MIB->getOperand(3).getReg();
547 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
548 Helper.OperandRegBankID))
551 auto ARMConds = getComparePreds(Cond);
552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
553 putConstant(I, ZeroReg, 0);
555 if (ARMConds.second == ARMCC::AL) {
556 // Simple case, we only need one comparison and we're done.
557 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
561 // Not so simple, we need two successive comparisons.
562 auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
563 if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
566 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
571 MIB->eraseFromParent();
575 bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
577 ARMCC::CondCodes Cond,
578 unsigned LHSReg, unsigned RHSReg,
579 unsigned PrevRes) const {
580 // Perform the comparison.
582 BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
585 .add(predOps(ARMCC::AL));
586 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
589 // Read the comparison flags (if necessary).
590 if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
591 auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
592 TII.get(Helper.ReadFlagsOpcode))
593 .add(predOps(ARMCC::AL));
594 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
598 // Select either 1 or the previous result based on the value of the flags.
599 auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
600 TII.get(Helper.SelectResultOpcode))
604 .add(predOps(Cond, ARM::CPSR));
605 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
611 bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
612 MachineRegisterInfo &MRI) const {
613 if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) {
614 LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n");
618 auto GV = MIB->getOperand(1).getGlobal();
619 if (GV->isThreadLocal()) {
620 LLVM_DEBUG(dbgs() << "TLS variables not supported yet\n");
624 auto &MBB = *MIB->getParent();
625 auto &MF = *MBB.getParent();
627 bool UseMovt = STI.useMovt();
629 unsigned Size = TM.getPointerSize(0);
630 unsigned Alignment = 4;
632 auto addOpsForConstantPoolLoad = [&MF, Alignment,
633 Size](MachineInstrBuilder &MIB,
634 const GlobalValue *GV, bool IsSBREL) {
635 assert((MIB->getOpcode() == ARM::LDRi12 ||
636 MIB->getOpcode() == ARM::t2LDRpci) &&
637 "Unsupported instruction");
638 auto ConstPool = MF.getConstantPool();
640 // For SB relative entries we need a target-specific constant pool.
641 // Otherwise, just use a regular constant pool entry.
643 ? ConstPool->getConstantPoolIndex(
644 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL), Alignment)
645 : ConstPool->getConstantPoolIndex(GV, Alignment);
646 MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
647 .addMemOperand(MF.getMachineMemOperand(
648 MachinePointerInfo::getConstantPool(MF), MachineMemOperand::MOLoad,
650 if (MIB->getOpcode() == ARM::LDRi12)
652 MIB.add(predOps(ARMCC::AL));
655 auto addGOTMemOperand = [this, &MF, Alignment](MachineInstrBuilder &MIB) {
656 MIB.addMemOperand(MF.getMachineMemOperand(
657 MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad,
658 TM.getProgramPointerSize(), Alignment));
661 if (TM.isPositionIndependent()) {
662 bool Indirect = STI.isGVIndirectSymbol(GV);
664 // For ARM mode, we have different pseudoinstructions for direct accesses
665 // and indirect accesses, and the ones for indirect accesses include the
666 // load from GOT. For Thumb mode, we use the same pseudoinstruction for both
667 // direct and indirect accesses, and we need to manually generate the load
669 bool UseOpcodeThatLoads = Indirect && !STI.isThumb();
671 // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
672 // support it yet. See PR28229.
674 UseMovt && !STI.isTargetELF()
675 ? (UseOpcodeThatLoads ? (unsigned)ARM::MOV_ga_pcrel_ldr
676 : Opcodes.MOV_ga_pcrel)
677 : (UseOpcodeThatLoads ? (unsigned)ARM::LDRLIT_ga_pcrel_ldr
678 : Opcodes.LDRLIT_ga_pcrel);
679 MIB->setDesc(TII.get(Opc));
681 int TargetFlags = ARMII::MO_NO_FLAG;
682 if (STI.isTargetDarwin())
683 TargetFlags |= ARMII::MO_NONLAZY;
684 if (STI.isGVInGOT(GV))
685 TargetFlags |= ARMII::MO_GOT;
686 MIB->getOperand(1).setTargetFlags(TargetFlags);
689 if (!UseOpcodeThatLoads) {
690 auto ResultReg = MIB->getOperand(0).getReg();
691 auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
693 MIB->getOperand(0).setReg(AddressReg);
695 auto InsertBefore = std::next(MIB->getIterator());
696 auto MIBLoad = BuildMI(MBB, InsertBefore, MIB->getDebugLoc(),
697 TII.get(Opcodes.LOAD32))
701 .add(predOps(ARMCC::AL));
702 addGOTMemOperand(MIBLoad);
704 if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI))
707 addGOTMemOperand(MIB);
711 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
714 bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV);
715 if (STI.isROPI() && isReadOnly) {
716 unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel;
717 MIB->setDesc(TII.get(Opc));
718 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
720 if (STI.isRWPI() && !isReadOnly) {
721 auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
722 MachineInstrBuilder OffsetMIB;
724 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
725 TII.get(Opcodes.MOVi32imm), Offset);
726 OffsetMIB.addGlobalAddress(GV, /*Offset*/ 0, ARMII::MO_SBREL);
728 // Load the offset from the constant pool.
729 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
730 TII.get(Opcodes.ConstPoolLoad), Offset);
731 addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true);
733 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
736 // Add the offset to the SB register.
737 MIB->setDesc(TII.get(Opcodes.ADDrr));
738 MIB->RemoveOperand(1);
739 MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
741 .add(predOps(ARMCC::AL))
744 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
747 if (STI.isTargetELF()) {
749 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
751 // Load the global's address from the constant pool.
752 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
753 MIB->RemoveOperand(1);
754 addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
756 } else if (STI.isTargetMachO()) {
758 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
760 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
762 LLVM_DEBUG(dbgs() << "Object format not supported yet\n");
766 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
769 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
770 MachineRegisterInfo &MRI) const {
771 auto &MBB = *MIB->getParent();
772 auto InsertBefore = std::next(MIB->getIterator());
773 auto &DbgLoc = MIB->getDebugLoc();
775 // Compare the condition to 1.
776 auto CondReg = MIB->getOperand(1).getReg();
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
778 "Unsupported types for select operation");
779 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
782 .add(predOps(ARMCC::AL));
783 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
786 // Move a value into the result register based on the result of the
788 auto ResReg = MIB->getOperand(0).getReg();
789 auto TrueReg = MIB->getOperand(2).getReg();
790 auto FalseReg = MIB->getOperand(3).getReg();
791 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
793 "Unsupported types for select operation");
794 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr))
798 .add(predOps(ARMCC::EQ, ARM::CPSR));
799 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
802 MIB->eraseFromParent();
806 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
807 MachineInstrBuilder &MIB) const {
808 assert(!STI.isThumb() && "Unsupported subtarget");
809 MIB->setDesc(TII.get(ARM::MOVsr));
810 MIB.addImm(ShiftOpc);
811 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
812 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
815 void ARMInstructionSelector::renderVFPF32Imm(
816 MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst,
818 assert(OldInst.getOpcode() == TargetOpcode::G_FCONSTANT &&
819 OpIdx == -1 && "Expected G_FCONSTANT");
821 APFloat FPImmValue = OldInst.getOperand(1).getFPImm()->getValueAPF();
822 int FPImmEncoding = ARM_AM::getFP32Imm(FPImmValue);
823 assert(FPImmEncoding != -1 && "Invalid immediate value");
825 NewInstBuilder.addImm(FPImmEncoding);
828 void ARMInstructionSelector::renderVFPF64Imm(
829 MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst, int OpIdx) const {
830 assert(OldInst.getOpcode() == TargetOpcode::G_FCONSTANT &&
831 OpIdx == -1 && "Expected G_FCONSTANT");
833 APFloat FPImmValue = OldInst.getOperand(1).getFPImm()->getValueAPF();
834 int FPImmEncoding = ARM_AM::getFP64Imm(FPImmValue);
835 assert(FPImmEncoding != -1 && "Invalid immediate value");
837 NewInstBuilder.addImm(FPImmEncoding);
840 bool ARMInstructionSelector::select(MachineInstr &I) {
841 assert(I.getParent() && "Instruction should be in a basic block!");
842 assert(I.getParent()->getParent() && "Instruction should be in a function!");
844 auto &MBB = *I.getParent();
845 auto &MF = *MBB.getParent();
846 auto &MRI = MF.getRegInfo();
848 if (!isPreISelGenericOpcode(I.getOpcode())) {
850 return selectCopy(I, TII, MRI, TRI, RBI);
855 using namespace TargetOpcode;
857 if (selectImpl(I, *CoverageInfo))
860 MachineInstrBuilder MIB{MF, I};
863 switch (I.getOpcode()) {
868 assert(MRI.getType(I.getOperand(0).getReg()).getSizeInBits() <= 32 &&
869 "Unsupported destination size for extension");
871 LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
872 unsigned SrcSize = SrcTy.getSizeInBits();
875 // ZExt boils down to & 0x1; for SExt we also subtract that from 0
876 I.setDesc(TII.get(Opcodes.AND));
877 MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
880 Register SExtResult = I.getOperand(0).getReg();
882 // Use a new virtual register for the result of the AND
883 Register AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
884 I.getOperand(0).setReg(AndResult);
886 auto InsertBefore = std::next(I.getIterator());
888 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB))
892 .add(predOps(ARMCC::AL))
894 if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
901 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
902 if (NewOpc == I.getOpcode())
904 I.setDesc(TII.get(NewOpc));
905 MIB.addImm(0).add(predOps(ARMCC::AL));
909 LLVM_DEBUG(dbgs() << "Unsupported source size for extension");
916 // The high bits are undefined, so there's nothing special to do, just
917 // treat it as a copy.
918 auto SrcReg = I.getOperand(1).getReg();
919 auto DstReg = I.getOperand(0).getReg();
921 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
922 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
924 if (SrcRegBank.getID() == ARM::FPRRegBankID) {
925 // This should only happen in the obscure case where we have put a 64-bit
926 // integer into a D register. Get it out of there and keep only the
928 assert(I.getOpcode() == G_TRUNC && "Unsupported operand for G_ANYEXT");
929 assert(DstRegBank.getID() == ARM::GPRRegBankID &&
930 "Unsupported combination of register banks");
931 assert(MRI.getType(SrcReg).getSizeInBits() == 64 && "Unsupported size");
932 assert(MRI.getType(DstReg).getSizeInBits() <= 32 && "Unsupported size");
934 Register IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
935 auto InsertBefore = std::next(I.getIterator());
937 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD))
941 .add(predOps(ARMCC::AL));
942 if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI))
945 MIB->eraseFromParent();
949 if (SrcRegBank.getID() != DstRegBank.getID()) {
951 dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
955 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
956 LLVM_DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
960 I.setDesc(TII.get(COPY));
961 return selectCopy(I, TII, MRI, TRI, RBI);
964 if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) {
965 // Non-pointer constants should be handled by TableGen.
966 LLVM_DEBUG(dbgs() << "Unsupported constant type\n");
970 auto &Val = I.getOperand(1);
972 if (!Val.getCImm()->isZero()) {
973 LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
976 Val.ChangeToImmediate(0);
978 assert(Val.isImm() && "Unexpected operand for G_CONSTANT");
979 if (Val.getImm() != 0) {
980 LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
985 assert(!STI.isThumb() && "Unsupported subtarget");
986 I.setDesc(TII.get(ARM::MOVi));
987 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
991 // Load from constant pool
992 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8;
993 unsigned Alignment = Size;
995 assert((Size == 4 || Size == 8) && "Unsupported FP constant type");
996 auto LoadOpcode = Size == 4 ? ARM::VLDRS : ARM::VLDRD;
998 auto ConstPool = MF.getConstantPool();
1000 ConstPool->getConstantPoolIndex(I.getOperand(1).getFPImm(), Alignment);
1001 MIB->setDesc(TII.get(LoadOpcode));
1002 MIB->RemoveOperand(1);
1003 MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
1005 MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
1006 MachineMemOperand::MOLoad, Size, Alignment))
1008 .add(predOps(ARMCC::AL));
1013 auto SrcReg = I.getOperand(1).getReg();
1014 auto DstReg = I.getOperand(0).getReg();
1016 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
1017 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1019 if (SrcRegBank.getID() != DstRegBank.getID()) {
1022 << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
1026 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
1028 dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
1032 I.setDesc(TII.get(COPY));
1033 return selectCopy(I, TII, MRI, TRI, RBI);
1036 return selectSelect(MIB, MRI);
1038 CmpConstants Helper(Opcodes.CMPrr, ARM::INSTRUCTION_LIST_END,
1039 Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
1040 return selectCmp(Helper, MIB, MRI);
1043 assert(STI.hasVFP2Base() && "Can't select fcmp without VFP");
1045 Register OpReg = I.getOperand(2).getReg();
1046 unsigned Size = MRI.getType(OpReg).getSizeInBits();
1048 if (Size == 64 && !STI.hasFP64()) {
1049 LLVM_DEBUG(dbgs() << "Subtarget only supports single precision");
1052 if (Size != 32 && Size != 64) {
1053 LLVM_DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
1057 CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
1058 Opcodes.MOVCCi, ARM::FPRRegBankID, Size);
1059 return selectCmp(Helper, MIB, MRI);
1062 return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
1064 return selectShift(ARM_AM::ShiftOpc::asr, MIB);
1066 return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
1069 I.setDesc(TII.get(Opcodes.ADDrr));
1070 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
1073 // Add 0 to the given frame index and hope it will eventually be folded into
1075 I.setDesc(TII.get(Opcodes.ADDri));
1076 MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
1078 case G_GLOBAL_VALUE:
1079 return selectGlobal(MIB, MRI);
1082 const auto &MemOp = **I.memoperands_begin();
1083 if (MemOp.isAtomic()) {
1084 LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
1088 Register Reg = I.getOperand(0).getReg();
1089 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
1091 LLT ValTy = MRI.getType(Reg);
1092 const auto ValSize = ValTy.getSizeInBits();
1094 assert((ValSize != 64 || STI.hasVFP2Base()) &&
1095 "Don't know how to load/store 64-bit value without VFP");
1097 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
1098 if (NewOpc == G_LOAD || NewOpc == G_STORE)
1101 if (ValSize == 1 && NewOpc == Opcodes.STORE8) {
1102 // Before storing a 1-bit value, make sure to clear out any unneeded bits.
1103 Register OriginalValue = I.getOperand(0).getReg();
1105 Register ValueToStore = MRI.createVirtualRegister(&ARM::GPRRegClass);
1106 I.getOperand(0).setReg(ValueToStore);
1108 auto InsertBefore = I.getIterator();
1109 auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND))
1110 .addDef(ValueToStore)
1111 .addUse(OriginalValue)
1113 .add(predOps(ARMCC::AL))
1115 if (!constrainSelectedInstRegOperands(*AndI, TII, TRI, RBI))
1119 I.setDesc(TII.get(NewOpc));
1121 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
1122 // LDRH has a funny addressing mode (there's already a FIXME for it).
1124 MIB.addImm(0).add(predOps(ARMCC::AL));
1127 case G_MERGE_VALUES: {
1128 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
1132 case G_UNMERGE_VALUES: {
1133 if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
1138 if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
1139 LLVM_DEBUG(dbgs() << "Unsupported condition register for G_BRCOND");
1145 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
1146 .addReg(I.getOperand(0).getReg())
1148 .add(predOps(ARMCC::AL));
1149 if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
1152 // Branch conditionally.
1154 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
1155 .add(I.getOperand(1))
1156 .add(predOps(ARMCC::NE, ARM::CPSR));
1157 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
1159 I.eraseFromParent();
1163 I.setDesc(TII.get(PHI));
1165 Register DstReg = I.getOperand(0).getReg();
1166 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
1167 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1177 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);