1 //===-- ARMLowOverheadLoops.cpp - CodeGen Low-overhead Loops ---*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// Finalize v8.1-m low-overhead loops by converting the associated pseudo
10 /// instructions into machine operations.
11 /// The expectation is that the loop contains three pseudo instructions:
12 /// - t2*LoopStart - placed in the preheader or pre-preheader. The do-loop
13 /// form should be in the preheader, whereas the while form should be in the
14 /// preheaders only predecessor. TODO: Could DoLoopStart get moved into the
16 /// - t2LoopDec - placed within in the loop body.
17 /// - t2LoopEnd - the loop latch terminator.
19 //===----------------------------------------------------------------------===//
22 #include "ARMBaseInstrInfo.h"
23 #include "ARMBaseRegisterInfo.h"
24 #include "ARMBasicBlockInfo.h"
25 #include "ARMSubtarget.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #define DEBUG_TYPE "arm-low-overhead-loops"
33 #define ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"
37 class ARMLowOverheadLoops : public MachineFunctionPass {
38 const ARMBaseInstrInfo *TII = nullptr;
39 MachineRegisterInfo *MRI = nullptr;
40 std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
45 ARMLowOverheadLoops() : MachineFunctionPass(ID) { }
47 void getAnalysisUsage(AnalysisUsage &AU) const override {
49 AU.addRequired<MachineLoopInfo>();
50 MachineFunctionPass::getAnalysisUsage(AU);
53 bool runOnMachineFunction(MachineFunction &MF) override;
55 bool ProcessLoop(MachineLoop *ML);
57 void RevertWhile(MachineInstr *MI) const;
59 void RevertLoopDec(MachineInstr *MI) const;
61 void RevertLoopEnd(MachineInstr *MI) const;
63 void Expand(MachineLoop *ML, MachineInstr *Start,
64 MachineInstr *Dec, MachineInstr *End, bool Revert);
66 MachineFunctionProperties getRequiredProperties() const override {
67 return MachineFunctionProperties().set(
68 MachineFunctionProperties::Property::NoVRegs);
71 StringRef getPassName() const override {
72 return ARM_LOW_OVERHEAD_LOOPS_NAME;
77 char ARMLowOverheadLoops::ID = 0;
79 INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,
82 bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &MF) {
83 if (!static_cast<const ARMSubtarget&>(MF.getSubtarget()).hasLOB())
86 LLVM_DEBUG(dbgs() << "ARM Loops on " << MF.getName() << " ------------- \n");
88 auto &MLI = getAnalysis<MachineLoopInfo>();
89 MRI = &MF.getRegInfo();
90 TII = static_cast<const ARMBaseInstrInfo*>(
91 MF.getSubtarget().getInstrInfo());
92 BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(MF));
93 BBUtils->computeAllBlockSizes();
94 BBUtils->adjustBBOffsetsAfter(&MF.front());
98 if (!ML->getParentLoop())
99 Changed |= ProcessLoop(ML);
104 bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
106 bool Changed = false;
108 // Process inner loops first.
109 for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
110 Changed |= ProcessLoop(*I);
112 LLVM_DEBUG(dbgs() << "ARM Loops: Processing " << *ML);
114 auto IsLoopStart = [](MachineInstr &MI) {
115 return MI.getOpcode() == ARM::t2DoLoopStart ||
116 MI.getOpcode() == ARM::t2WhileLoopStart;
119 // Search the given block for a loop start instruction. If one isn't found,
120 // and there's only one predecessor block, search that one too.
121 std::function<MachineInstr*(MachineBasicBlock*)> SearchForStart =
122 [&IsLoopStart, &SearchForStart](MachineBasicBlock *MBB) -> MachineInstr* {
123 for (auto &MI : *MBB) {
127 if (MBB->pred_size() == 1)
128 return SearchForStart(*MBB->pred_begin());
132 MachineInstr *Start = nullptr;
133 MachineInstr *Dec = nullptr;
134 MachineInstr *End = nullptr;
137 // Search the preheader for the start intrinsic, or look through the
138 // predecessors of the header to find exactly one set.iterations intrinsic.
139 // FIXME: I don't see why we shouldn't be supporting multiple predecessors
140 // with potentially multiple set.loop.iterations, so we need to enable this.
141 if (auto *Preheader = ML->getLoopPreheader()) {
142 Start = SearchForStart(Preheader);
144 LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find loop preheader!\n"
145 << " - Performing manual predecessor search.\n");
146 MachineBasicBlock *Pred = nullptr;
147 for (auto *MBB : ML->getHeader()->predecessors()) {
148 if (!ML->contains(MBB)) {
150 LLVM_DEBUG(dbgs() << " - Found multiple out-of-loop preds.\n");
155 Start = SearchForStart(MBB);
160 // Find the low-overhead loop components and decide whether or not to fall
161 // back to a normal loop.
162 for (auto *MBB : reverse(ML->getBlocks())) {
163 for (auto &MI : *MBB) {
164 if (MI.getOpcode() == ARM::t2LoopDec)
166 else if (MI.getOpcode() == ARM::t2LoopEnd)
168 else if (MI.getDesc().isCall())
169 // TODO: Though the call will require LE to execute again, does this
170 // mean we should revert? Always executing LE hopefully should be
171 // faster than performing a sub,cmp,br or even subs,br.
177 // If we find that we load/store LR between LoopDec and LoopEnd, expect
178 // that the decremented value has been spilled to the stack. Because
179 // this value isn't actually going to be produced until the latch, by LE,
180 // we would need to generate a real sub. The value is also likely to be
181 // reloaded for use of LoopEnd - in which in case we'd need to perform
182 // an add because it gets negated again by LE! The other option is to
183 // then generate the other form of LE which doesn't perform the sub.
184 if (MI.mayLoad() || MI.mayStore())
186 MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == ARM::LR;
189 if (Dec && End && Revert)
193 if (!Start && !Dec && !End) {
194 LLVM_DEBUG(dbgs() << "ARM Loops: Not a low-overhead loop.\n");
196 } if (!(Start && Dec && End)) {
197 report_fatal_error("Failed to find all loop components");
200 if (!End->getOperand(1).isMBB() ||
201 End->getOperand(1).getMBB() != ML->getHeader())
202 report_fatal_error("Expected LoopEnd to target Loop Header");
204 // The WLS and LE instructions have 12-bits for the label offset. WLS
205 // requires a positive offset, while LE uses negative.
206 if (BBUtils->getOffsetOf(End) < BBUtils->getOffsetOf(ML->getHeader()) ||
207 !BBUtils->isBBInRange(End, ML->getHeader(), 4094)) {
208 LLVM_DEBUG(dbgs() << "ARM Loops: LE offset is out-of-range\n");
211 if (Start->getOpcode() == ARM::t2WhileLoopStart &&
212 (BBUtils->getOffsetOf(Start) >
213 BBUtils->getOffsetOf(Start->getOperand(1).getMBB()) ||
214 !BBUtils->isBBInRange(Start, Start->getOperand(1).getMBB(), 4094))) {
215 LLVM_DEBUG(dbgs() << "ARM Loops: WLS offset is out-of-range!\n");
219 LLVM_DEBUG(dbgs() << "ARM Loops:\n - Found Loop Start: " << *Start
220 << " - Found Loop Dec: " << *Dec
221 << " - Found Loop End: " << *End);
223 Expand(ML, Start, Dec, End, Revert);
227 // WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
228 // beq that branches to the exit branch.
229 // FIXME: Need to check that we're not trashing the CPSR when generating the
230 // cmp. We could also try to generate a cbz if the value in LR is also in
231 // another low register.
232 void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
233 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
234 MachineBasicBlock *MBB = MI->getParent();
235 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
236 TII->get(ARM::t2CMPri));
239 MIB.addImm(ARMCC::AL);
240 MIB.addReg(ARM::CPSR);
242 // TODO: Try to use tBcc instead
243 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
244 MIB.add(MI->getOperand(1)); // branch target
245 MIB.addImm(ARMCC::EQ); // condition code
246 MIB.addReg(ARM::CPSR);
247 MI->eraseFromParent();
250 // TODO: Check flags so that we can possibly generate a tSubs or tSub.
251 void ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
252 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
253 MachineBasicBlock *MBB = MI->getParent();
254 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
255 TII->get(ARM::t2SUBri));
257 MIB.add(MI->getOperand(1));
258 MIB.add(MI->getOperand(2));
259 MIB.addImm(ARMCC::AL);
262 MI->eraseFromParent();
265 // Generate a subs, or sub and cmp, and a branch instead of an LE.
266 // FIXME: Need to check that we're not trashing the CPSR when generating
268 void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
269 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
272 MachineBasicBlock *MBB = MI->getParent();
273 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
274 TII->get(ARM::t2CMPri));
277 MIB.addImm(ARMCC::AL);
278 MIB.addReg(ARM::CPSR);
280 // TODO Try to use tBcc instead.
282 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
283 MIB.add(MI->getOperand(1)); // branch target
284 MIB.addImm(ARMCC::NE); // condition code
285 MIB.addReg(ARM::CPSR);
286 MI->eraseFromParent();
289 void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
290 MachineInstr *Dec, MachineInstr *End,
293 auto ExpandLoopStart = [this](MachineLoop *ML, MachineInstr *Start) {
294 // The trip count should already been held in LR since the instructions
295 // within the loop can only read and write to LR. So, there should be a
296 // mov to setup the count. WLS/DLS perform this move, so find the original
297 // and delete it - inserting WLS/DLS in its place.
298 MachineBasicBlock *MBB = Start->getParent();
299 MachineInstr *InsertPt = Start;
300 for (auto &I : MRI->def_instructions(ARM::LR)) {
301 if (I.getParent() != MBB)
305 if (!I.getOperand(2).isImm() || I.getOperand(2).getImm() != ARMCC::AL)
308 // Only handle move reg, if the trip count it will need moving into a reg
309 // before the setup instruction anyway.
310 if (!I.getDesc().isMoveReg() ||
311 !I.getOperand(1).isIdenticalTo(Start->getOperand(0)))
317 unsigned Opc = Start->getOpcode() == ARM::t2DoLoopStart ?
318 ARM::t2DLS : ARM::t2WLS;
319 MachineInstrBuilder MIB =
320 BuildMI(*MBB, InsertPt, InsertPt->getDebugLoc(), TII->get(Opc));
323 MIB.add(Start->getOperand(0));
324 if (Opc == ARM::t2WLS)
325 MIB.add(Start->getOperand(1));
327 if (InsertPt != Start)
328 InsertPt->eraseFromParent();
329 Start->eraseFromParent();
330 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB);
334 // Combine the LoopDec and LoopEnd instructions into LE(TP).
335 auto ExpandLoopEnd = [this](MachineLoop *ML, MachineInstr *Dec,
337 MachineBasicBlock *MBB = End->getParent();
338 MachineInstrBuilder MIB = BuildMI(*MBB, End, End->getDebugLoc(),
339 TII->get(ARM::t2LEUpdate));
341 MIB.add(End->getOperand(0));
342 MIB.add(End->getOperand(1));
343 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted LE: " << *MIB);
345 End->eraseFromParent();
346 Dec->eraseFromParent();
350 // TODO: We should be able to automatically remove these branches before we
351 // get here - probably by teaching analyzeBranch about the pseudo
353 // If there is an unconditional branch, after I, that just branches to the
354 // next block, remove it.
355 auto RemoveDeadBranch = [](MachineInstr *I) {
356 MachineBasicBlock *BB = I->getParent();
357 MachineInstr *Terminator = &BB->instr_back();
358 if (Terminator->isUnconditionalBranch() && I != Terminator) {
359 MachineBasicBlock *Succ = Terminator->getOperand(0).getMBB();
360 if (BB->isLayoutSuccessor(Succ)) {
361 LLVM_DEBUG(dbgs() << "ARM Loops: Removing branch: " << *Terminator);
362 Terminator->eraseFromParent();
368 if (Start->getOpcode() == ARM::t2WhileLoopStart)
371 Start->eraseFromParent();
375 Start = ExpandLoopStart(ML, Start);
376 RemoveDeadBranch(Start);
377 End = ExpandLoopEnd(ML, Dec, End);
378 RemoveDeadBranch(End);
382 FunctionPass *llvm::createARMLowOverheadLoopsPass() {
383 return new ARMLowOverheadLoops();