1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //===----------------------------------------------------------------------===//
15 #include "ARMCallLowering.h"
16 #include "ARMLegalizerInfo.h"
17 #include "ARMRegisterBankInfo.h"
18 #include "ARMSubtarget.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCTargetOptions.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/TargetParser.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define DEBUG_TYPE "arm-subtarget"
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "ARMGenSubtargetInfo.inc"
50 UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
59 static cl::opt<ITMode>
60 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
62 cl::values(clEnumValN(DefaultIT, "arm-default-it",
63 "Generate IT block based on arch"),
64 clEnumValN(RestrictedIT, "arm-restrict-it",
65 "Disallow deprecated IT based on ARMv8"),
66 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
67 "Allow IT blocks based on ARMv7")));
69 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
70 /// currently supported (for testing only).
72 ForceFastISel("arm-force-fast-isel",
73 cl::init(false), cl::Hidden);
75 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
76 /// so that we can use initializer lists for subtarget initialization.
77 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
79 initializeEnvironment();
80 initSubtargetFeatures(CPU, FS);
84 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
86 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
87 if (STI.isThumb1Only())
88 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
90 return new ARMFrameLowering(STI);
93 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
94 const std::string &FS,
95 const ARMBaseTargetMachine &TM, bool IsLittle,
97 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
98 CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
99 TargetTriple(TT), Options(TM.Options), TM(TM),
100 FrameLowering(initializeFrameLowering(CPU, FS)),
101 // At this point initializeSubtargetDependencies has been called so
102 // we can query directly.
103 InstrInfo(isThumb1Only()
104 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
106 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
107 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
110 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
111 Legalizer.reset(new ARMLegalizerInfo(*this));
113 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
115 // FIXME: At this point, we can't rely on Subtarget having RBI.
116 // It's awkward to mix passing RBI and the Subtarget; should we pass
118 InstSelector.reset(createARMInstructionSelector(
119 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
121 RegBankInfo.reset(RBI);
124 const CallLowering *ARMSubtarget::getCallLowering() const {
125 return CallLoweringInfo.get();
128 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
129 return InstSelector.get();
132 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
133 return Legalizer.get();
136 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
137 return RegBankInfo.get();
140 bool ARMSubtarget::isXRaySupported() const {
141 // We don't currently suppport Thumb, but Windows requires Thumb.
142 return hasV6Ops() && hasARMOps() && !isTargetWindows();
145 void ARMSubtarget::initializeEnvironment() {
146 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
147 // directly from it, but we can try to make sure they're consistent when both
149 UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
150 Options.ExceptionModel == ExceptionHandling::None) ||
151 Options.ExceptionModel == ExceptionHandling::SjLj;
152 assert((!TM.getMCAsmInfo() ||
153 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
154 ExceptionHandling::SjLj) == UseSjLjEH) &&
155 "inconsistent sjlj choice between CodeGen and MC");
158 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
159 if (CPUString.empty()) {
160 CPUString = "generic";
162 if (isTargetDarwin()) {
163 StringRef ArchName = TargetTriple.getArchName();
164 ARM::ArchKind AK = ARM::parseArch(ArchName);
165 if (AK == ARM::ArchKind::ARMV7S)
166 // Default to the Swift CPU when targeting armv7s/thumbv7s.
168 else if (AK == ARM::ArchKind::ARMV7K)
169 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
170 // ARMv7k does not use SjLj exception handling.
171 CPUString = "cortex-a7";
175 // Insert the architecture feature derived from the target triple into the
176 // feature string. This is important for setting features that are implied
177 // based on the architecture version.
178 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
181 ArchFS = (Twine(ArchFS) + "," + FS).str();
185 ParseSubtargetFeatures(CPUString, ArchFS);
187 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
188 // Assert this for now to make the change obvious.
189 assert(hasV6T2Ops() || !hasThumb2());
191 // Execute only support requires movt support
192 if (genExecuteOnly()) {
194 assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
197 // Keep a pointer to static instruction cost data for the specified CPU.
198 SchedModel = getSchedModelForCPU(CPUString);
200 // Initialize scheduling itinerary for the specified CPU.
201 InstrItins = getInstrItineraryForCPU(CPUString);
203 // FIXME: this is invalid for WindowsCE
204 if (isTargetWindows())
209 if (isTargetNaCl() || isAAPCS16_ABI())
212 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
213 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
214 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
215 // support in the assembler and linker to be used. This would need to be
216 // fixed to fully support tail calls in Thumb1.
218 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
219 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
220 // means if we need to reload LR, it takes extra instructions, which outweighs
221 // the value of the tail call; but here we don't know yet whether LR is going
222 // to be used. We take the optimistic approach of generating the tail call and
223 // perhaps taking a hit if we need to restore the LR.
225 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
226 // but we need to make sure there are enough registers; the only valid
227 // registers are the 4 used for parameters. We don't currently do this
230 SupportsTailCall = !isThumb() || hasV8MBaselineOps();
232 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
233 SupportsTailCall = false;
237 RestrictIT = hasV8Ops();
247 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
248 const FeatureBitset &Bits = getFeatureBits();
249 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
250 (Options.UnsafeFPMath || isTargetDarwin()))
251 UseNEONForSinglePrecisionFP = true;
256 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
257 switch (ARMProcFamily) {
262 LdStMultipleTiming = DoubleIssue;
265 LdStMultipleTiming = DoubleIssue;
268 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
269 PreISelOperandLatencyAdjustment = 1;
274 MaxInterleaveFactor = 2;
275 PreISelOperandLatencyAdjustment = 1;
276 PartialUpdateClearance = 12;
296 LdStMultipleTiming = SingleIssuePlusExtras;
297 MaxInterleaveFactor = 4;
299 PrefLoopAlignment = 3;
304 PreISelOperandLatencyAdjustment = 1;
307 MaxInterleaveFactor = 2;
308 LdStMultipleTiming = SingleIssuePlusExtras;
309 PreISelOperandLatencyAdjustment = 1;
310 PartialUpdateClearance = 12;
315 bool ARMSubtarget::isTargetHardFloat() const { return TM.isTargetHardFloat(); }
317 bool ARMSubtarget::isAPCS_ABI() const {
318 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
319 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
321 bool ARMSubtarget::isAAPCS_ABI() const {
322 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
323 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
324 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
326 bool ARMSubtarget::isAAPCS16_ABI() const {
327 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
328 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
331 bool ARMSubtarget::isROPI() const {
332 return TM.getRelocationModel() == Reloc::ROPI ||
333 TM.getRelocationModel() == Reloc::ROPI_RWPI;
335 bool ARMSubtarget::isRWPI() const {
336 return TM.getRelocationModel() == Reloc::RWPI ||
337 TM.getRelocationModel() == Reloc::ROPI_RWPI;
340 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
341 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
344 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
345 // the section that is being relocated. This means we have to use o load even
346 // for GVs that are known to be local to the dso.
347 if (isTargetMachO() && TM.isPositionIndependent() &&
348 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
354 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
355 return isTargetELF() && TM.isPositionIndependent() &&
356 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
359 unsigned ARMSubtarget::getMispredictionPenalty() const {
360 return SchedModel.MispredictPenalty;
363 bool ARMSubtarget::enableMachineScheduler() const {
364 // The MachineScheduler can increase register usage, so we use more high
365 // registers and end up with more T2 instructions that cannot be converted to
366 // T1 instructions. At least until we do better at converting to thumb1
367 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
368 // Machine scheduler, relying on the DAG register pressure scheduler instead.
369 if (isMClass() && hasMinSize())
371 // Enable the MachineScheduler before register allocation for subtargets
372 // with the use-misched feature.
373 return useMachineScheduler();
376 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
377 bool ARMSubtarget::enablePostRAScheduler() const {
378 if (disablePostRAScheduler())
380 // Don't reschedule potential IT blocks.
381 return !isThumb1Only();
384 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
386 bool ARMSubtarget::useStride4VFPs() const {
387 // For general targets, the prologue can grow when VFPs are allocated with
388 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
389 // format which it's more important to get right.
390 return isTargetWatchABI() ||
391 (useWideStrideVFP() && !OptMinSize);
394 bool ARMSubtarget::useMovt() const {
395 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
396 // immediates as it is inherently position independent, and may be out of
398 return !NoMovt && hasV8MBaselineOps() &&
399 (isTargetWindows() || !OptMinSize || genExecuteOnly());
402 bool ARMSubtarget::useFastISel() const {
403 // Enable fast-isel for any target, for testing only.
407 // Limit fast-isel to the targets that are or have been tested.
411 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
412 return TM.Options.EnableFastISel &&
413 ((isTargetMachO() && !isThumb1Only()) ||
414 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
417 unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const {
418 // The GPR register class has multiple possible allocation orders, with
419 // tradeoffs preferred by different sub-architectures and optimisation goals.
420 // The allocation orders are:
421 // 0: (the default tablegen order, not used)
424 // 3: r0-r7, r12, lr, r8-r11
425 // Note that the register allocator will change this order so that
426 // callee-saved registers are used later, as they require extra work in the
427 // prologue/epilogue (though we sometimes override that).
429 // For thumb1-only targets, only the low registers are allocatable.
433 // Allocate low registers first, so we can select more 16-bit instructions.
434 // We also (in ignoreCSRForAllocationOrder) override the default behaviour
435 // with regards to callee-saved registers, because pushing extra registers is
436 // much cheaper (in terms of code size) than using high registers. After
437 // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
438 // can return with the pop, don't need an extra "bx lr") and then the rest of
439 // the high registers.
440 if (isThumb2() && MF.getFunction().hasMinSize())
443 // Otherwise, allocate in the default order, using LR first because saving it
444 // allows a shorter epilogue sequence.
448 bool ARMSubtarget::ignoreCSRForAllocationOrder(const MachineFunction &MF,
449 unsigned PhysReg) const {
450 // To minimize code size in Thumb2, we prefer the usage of low regs (lower
451 // cost per use) so we can use narrow encoding. By default, caller-saved
452 // registers (e.g. lr, r12) are always allocated first, regardless of
453 // their cost per use. When optForMinSize, we prefer the low regs even if
454 // they are CSR because usually push/pop can be folded into existing ones.
455 return isThumb2() && MF.getFunction().hasMinSize() &&
456 ARM::GPRRegClass.contains(PhysReg);