1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineInstrBundle.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCRegisterInfo.h"
33 #define DEBUG_TYPE "thumb2-it"
34 #define PASS_NAME "Thumb IT blocks insertion pass"
36 STATISTIC(NumITs, "Number of IT blocks inserted");
37 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
39 using RegisterSet = SmallSet<unsigned, 4>;
43 class Thumb2ITBlock : public MachineFunctionPass {
48 const Thumb2InstrInfo *TII;
49 const TargetRegisterInfo *TRI;
52 Thumb2ITBlock() : MachineFunctionPass(ID) {}
54 bool runOnMachineFunction(MachineFunction &Fn) override;
56 MachineFunctionProperties getRequiredProperties() const override {
57 return MachineFunctionProperties().set(
58 MachineFunctionProperties::Property::NoVRegs);
61 StringRef getPassName() const override {
66 bool MoveCopyOutOfITBlock(MachineInstr *MI,
67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
68 RegisterSet &Defs, RegisterSet &Uses);
69 bool InsertITInstructions(MachineBasicBlock &Block);
72 char Thumb2ITBlock::ID = 0;
74 } // end anonymous namespace
76 INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false)
78 /// TrackDefUses - Tracking what registers are being defined and used by
79 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
80 /// in the IT block that are defined before the IT instruction.
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
82 const TargetRegisterInfo *TRI) {
83 using RegList = SmallVector<unsigned, 4>;
87 for (auto &MO : MI->operands()) {
90 unsigned Reg = MO.getReg();
91 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
94 LocalUses.push_back(Reg);
96 LocalDefs.push_back(Reg);
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
100 for (unsigned Reg : Regs)
101 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
102 Subreg.isValid(); ++Subreg)
103 UsesDefs.insert(*Subreg);
106 InsertUsesDefs(LocalDefs, Defs);
107 InsertUsesDefs(LocalUses, Uses);
110 /// Clear kill flags for any uses in the given set. This will likely
111 /// conservatively remove more kill flags than are necessary, but removing them
112 /// is safer than incorrect kill flags remaining on instructions.
113 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) {
114 for (MachineOperand &MO : MI->operands()) {
115 if (!MO.isReg() || MO.isDef() || !MO.isKill())
117 if (!Uses.count(MO.getReg()))
123 static bool isCopy(MachineInstr *MI) {
124 switch (MI->getOpcode()) {
136 Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI,
137 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
138 RegisterSet &Defs, RegisterSet &Uses) {
141 // llvm models select's as two-address instructions. That means a copy
142 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
143 // between selects we would end up creating multiple IT blocks.
144 assert(MI->getOperand(0).getSubReg() == 0 &&
145 MI->getOperand(1).getSubReg() == 0 &&
146 "Sub-register indices still around?");
148 unsigned DstReg = MI->getOperand(0).getReg();
149 unsigned SrcReg = MI->getOperand(1).getReg();
151 // First check if it's safe to move it.
152 if (Uses.count(DstReg) || Defs.count(SrcReg))
155 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
163 // we don't want this to be converted to:
171 const MCInstrDesc &MCID = MI->getDesc();
172 if (MI->hasOptionalDef() &&
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
176 // Then peek at the next instruction to see if it's predicated on CC or OCC.
177 // If not, then there is nothing to be gained by moving the copy.
178 MachineBasicBlock::iterator I = MI;
180 MachineBasicBlock::iterator E = MI->getParent()->end();
182 while (I != E && I->isDebugInstr())
186 unsigned NPredReg = 0;
187 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
188 if (NCC == CC || NCC == OCC)
194 bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
195 bool Modified = false;
196 RegisterSet Defs, Uses;
197 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
200 MachineInstr *MI = &*MBBI;
201 DebugLoc dl = MI->getDebugLoc();
202 unsigned PredReg = 0;
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
204 if (CC == ARMCC::AL) {
211 TrackDefUses(MI, Defs, Uses, TRI);
213 // Insert an IT instruction.
214 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
217 // Add implicit use of ITSTATE to IT block instructions.
218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
219 true/*isImp*/, false/*isKill*/));
221 MachineInstr *LastITMI = MI;
222 MachineBasicBlock::iterator InsertPos = MIB.getInstr();
226 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
227 unsigned Mask = 0, Pos = 3;
229 // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
230 // is set: skip the loop
232 // Branches, including tricky ones like LDM_RET, need to end an IT
233 // block so check the instruction we just put in the block.
234 for (; MBBI != E && Pos &&
235 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
236 if (MBBI->isDebugInstr())
239 MachineInstr *NMI = &*MBBI;
242 unsigned NPredReg = 0;
243 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
244 if (NCC == CC || NCC == OCC) {
245 Mask |= ((NCC ^ CC) & 1) << Pos;
246 // Add implicit use of ITSTATE.
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
248 true/*isImp*/, false/*isKill*/));
251 if (NCC == ARMCC::AL &&
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
255 MBB.insert(InsertPos, NMI);
256 ClearKillFlags(MI, Uses);
262 TrackDefUses(NMI, Defs, Uses, TRI);
271 // Last instruction in IT block kills ITSTATE.
272 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
274 // Finalize the bundle.
275 finalizeBundle(MBB, InsertPos.getInstrIterator(),
276 ++LastITMI->getIterator());
285 bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
286 const ARMSubtarget &STI =
287 static_cast<const ARMSubtarget &>(Fn.getSubtarget());
290 AFI = Fn.getInfo<ARMFunctionInfo>();
291 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
292 TRI = STI.getRegisterInfo();
293 restrictIT = STI.restrictIT();
295 if (!AFI->isThumbFunction())
298 bool Modified = false;
299 for (auto &MBB : Fn )
300 Modified |= InsertITInstructions(MBB);
303 AFI->setHasITBlocks(true);
308 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
310 FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); }
313 #define DEBUG_TYPE "arm-mve-vpt"
316 class MVEVPTBlock : public MachineFunctionPass {
319 const Thumb2InstrInfo *TII;
320 const TargetRegisterInfo *TRI;
322 MVEVPTBlock() : MachineFunctionPass(ID) {}
324 bool runOnMachineFunction(MachineFunction &Fn) override;
326 MachineFunctionProperties getRequiredProperties() const override {
327 return MachineFunctionProperties().set(
328 MachineFunctionProperties::Property::NoVRegs);
331 StringRef getPassName() const override {
332 return "MVE VPT block insertion pass";
336 bool InsertVPTBlocks(MachineBasicBlock &MBB);
339 char MVEVPTBlock::ID = 0;
341 } // end anonymous namespace
343 INITIALIZE_PASS(MVEVPTBlock, DEBUG_TYPE, "ARM MVE VPT block pass", false, false)
363 bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
364 bool Modified = false;
365 MachineBasicBlock::iterator MBIter = Block.begin();
366 MachineBasicBlock::iterator EndIter = Block.end();
368 while (MBIter != EndIter) {
369 MachineInstr *MI = &*MBIter;
370 unsigned PredReg = 0;
371 DebugLoc dl = MI->getDebugLoc();
373 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg);
375 // The idea of the predicate is that None, Then and Else are for use when
376 // handling assembly language: they correspond to the three possible
377 // suffixes "", "t" and "e" on the mnemonic. So when instructions are read
378 // from assembly source or disassembled from object code, you expect to see
379 // a mixture whenever there's a long VPT block. But in code generation, we
380 // hope we'll never generate an Else as input to this pass.
382 assert(Pred != ARMVCC::Else && "VPT block pass does not expect Else preds");
384 if (Pred == ARMVCC::None) {
389 MachineInstrBuilder MIBuilder =
390 BuildMI(Block, MBIter, dl, TII->get(ARM::MVE_VPST));
391 // The mask value for the VPST instruction is T = 0b1000 = 8
392 MIBuilder.addImm(VPTMaskValue::T);
394 MachineBasicBlock::iterator VPSTInsertPos = MIBuilder.getInstr();
396 ARMVCC::VPTCodes NextPred;
400 NextPred = getVPTInstrPredicate(*MBIter, PredReg);
401 } while (NextPred != ARMVCC::None && NextPred == Pred && ++VPTInstCnt < 4);
403 MachineInstr *LastMI = &*MBIter;
404 finalizeBundle(Block, VPSTInsertPos.getInstrIterator(),
405 ++LastMI->getIterator());
408 LLVM_DEBUG(dbgs() << "VPT block created for: "; MI->dump(););
415 bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
416 const ARMSubtarget &STI =
417 static_cast<const ARMSubtarget &>(Fn.getSubtarget());
419 if (!STI.isThumb2() || !STI.hasMVEIntegerOps())
422 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
423 TRI = STI.getRegisterInfo();
425 LLVM_DEBUG(dbgs() << "********** ARM MVE VPT BLOCKS **********\n"
426 << "********** Function: " << Fn.getName() << '\n');
428 bool Modified = false;
429 for (MachineBasicBlock &MBB : Fn)
430 Modified |= InsertVPTBlocks(MBB);
432 LLVM_DEBUG(dbgs() << "**************************************\n");
436 /// createMVEVPTBlock - Returns an instance of the MVE VPT block
438 FunctionPass *llvm::createMVEVPTBlockPass() { return new MVEVPTBlock(); }