1 //===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the BPF instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 include "BPFInstrFormats.td"
15 // Instruction Operands and Patterns
17 // These are target-independent nodes, but have target-specific formats.
18 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
23 def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
26 def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
27 SDTCisVT<3, OtherVT>]>;
28 def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
30 def SDT_BPFMEMCPY : SDTypeProfile<0, 4, [SDTCisVT<0, i64>,
35 def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
36 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
38 def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
39 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
40 def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
41 [SDNPHasChain, SDNPOutGlue]>;
42 def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
43 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
44 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
45 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
47 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
48 def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
49 def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY,
50 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
51 SDNPMayStore, SDNPMayLoad]>;
52 def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">;
53 def BPFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
54 def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">;
55 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
57 def brtarget : Operand<OtherVT> {
58 let PrintMethod = "printBrTargetOperand";
60 def calltarget : Operand<i64>;
62 def u64imm : Operand<i64> {
63 let PrintMethod = "printImm64Operand";
66 def i64immSExt32 : PatLeaf<(i64 imm),
67 [{return isInt<32>(N->getSExtValue()); }]>;
68 def i32immSExt32 : PatLeaf<(i32 imm),
69 [{return isInt<32>(N->getSExtValue()); }]>;
72 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
73 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
76 def MEMri : Operand<i64> {
77 let PrintMethod = "printMemOperand";
78 let EncoderMethod = "getMemoryOpValue";
79 let DecoderMethod = "decodeMemoryOpValue";
80 let MIOperandInfo = (ops GPR, i16imm);
83 // Conditional code predicates - used for pattern matching for jump instructions
84 def BPF_CC_EQ : PatLeaf<(i64 imm),
85 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
86 def BPF_CC_NE : PatLeaf<(i64 imm),
87 [{return (N->getZExtValue() == ISD::SETNE);}]>;
88 def BPF_CC_GE : PatLeaf<(i64 imm),
89 [{return (N->getZExtValue() == ISD::SETGE);}]>;
90 def BPF_CC_GT : PatLeaf<(i64 imm),
91 [{return (N->getZExtValue() == ISD::SETGT);}]>;
92 def BPF_CC_GTU : PatLeaf<(i64 imm),
93 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
94 def BPF_CC_GEU : PatLeaf<(i64 imm),
95 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
96 def BPF_CC_LE : PatLeaf<(i64 imm),
97 [{return (N->getZExtValue() == ISD::SETLE);}]>;
98 def BPF_CC_LT : PatLeaf<(i64 imm),
99 [{return (N->getZExtValue() == ISD::SETLT);}]>;
100 def BPF_CC_LTU : PatLeaf<(i64 imm),
101 [{return (N->getZExtValue() == ISD::SETULT);}]>;
102 def BPF_CC_LEU : PatLeaf<(i64 imm),
103 [{return (N->getZExtValue() == ISD::SETULE);}]>;
104 def BPF_CC_EQ_32 : PatLeaf<(i32 imm),
105 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
106 def BPF_CC_NE_32 : PatLeaf<(i32 imm),
107 [{return (N->getZExtValue() == ISD::SETNE);}]>;
108 def BPF_CC_GE_32 : PatLeaf<(i32 imm),
109 [{return (N->getZExtValue() == ISD::SETGE);}]>;
110 def BPF_CC_GT_32 : PatLeaf<(i32 imm),
111 [{return (N->getZExtValue() == ISD::SETGT);}]>;
112 def BPF_CC_GTU_32 : PatLeaf<(i32 imm),
113 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
114 def BPF_CC_GEU_32 : PatLeaf<(i32 imm),
115 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
116 def BPF_CC_LE_32 : PatLeaf<(i32 imm),
117 [{return (N->getZExtValue() == ISD::SETLE);}]>;
118 def BPF_CC_LT_32 : PatLeaf<(i32 imm),
119 [{return (N->getZExtValue() == ISD::SETLT);}]>;
120 def BPF_CC_LTU_32 : PatLeaf<(i32 imm),
121 [{return (N->getZExtValue() == ISD::SETULT);}]>;
122 def BPF_CC_LEU_32 : PatLeaf<(i32 imm),
123 [{return (N->getZExtValue() == ISD::SETULE);}]>;
125 // For arithmetic and jump instructions the 8-bit 'code'
126 // field is divided into three parts:
128 // +----------------+--------+--------------------+
129 // | 4 bits | 1 bit | 3 bits |
130 // | operation code | source | instruction class |
131 // +----------------+--------+--------------------+
133 class TYPE_ALU_JMP<bits<4> op, bits<1> srctype,
134 dag outs, dag ins, string asmstr, list<dag> pattern>
135 : InstBPF<outs, ins, asmstr, pattern> {
137 let Inst{63-60} = op;
138 let Inst{59} = srctype;
141 //For load and store instructions the 8-bit 'code' field is divided as:
143 // +--------+--------+-------------------+
144 // | 3 bits | 2 bits | 3 bits |
145 // | mode | size | instruction class |
146 // +--------+--------+-------------------+
148 class TYPE_LD_ST<bits<3> mode, bits<2> size,
149 dag outs, dag ins, string asmstr, list<dag> pattern>
150 : InstBPF<outs, ins, asmstr, pattern> {
152 let Inst{63-61} = mode;
153 let Inst{60-59} = size;
157 class JMP_RR<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
158 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value,
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
161 "if $dst "#OpcodeStr#" $src goto $BrDst",
162 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
167 let Inst{55-52} = src;
168 let Inst{51-48} = dst;
169 let Inst{47-32} = BrDst;
170 let BPFClass = BPF_JMP;
173 class JMP_RI<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
174 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
177 "if $dst "#OpcodeStr#" $imm goto $BrDst",
178 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
183 let Inst{51-48} = dst;
184 let Inst{47-32} = BrDst;
185 let Inst{31-0} = imm;
186 let BPFClass = BPF_JMP;
189 class JMP_RR_32<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
190 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value,
192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
193 "if $dst "#OpcodeStr#" $src goto $BrDst",
194 [(BPFbrcc i32:$dst, i32:$src, Cond, bb:$BrDst)]> {
199 let Inst{55-52} = src;
200 let Inst{51-48} = dst;
201 let Inst{47-32} = BrDst;
202 let BPFClass = BPF_JMP32;
205 class JMP_RI_32<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
206 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
208 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst),
209 "if $dst "#OpcodeStr#" $imm goto $BrDst",
210 [(BPFbrcc i32:$dst, i32immSExt32:$imm, Cond, bb:$BrDst)]> {
215 let Inst{51-48} = dst;
216 let Inst{47-32} = BrDst;
217 let Inst{31-0} = imm;
218 let BPFClass = BPF_JMP32;
221 multiclass J<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond, PatLeaf Cond32> {
222 def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
223 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
224 def _rr_32 : JMP_RR_32<Opc, OpcodeStr, Cond32>;
225 def _ri_32 : JMP_RI_32<Opc, OpcodeStr, Cond32>;
228 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
229 // cmp+goto instructions
230 defm JEQ : J<BPF_JEQ, "==", BPF_CC_EQ, BPF_CC_EQ_32>;
231 defm JUGT : J<BPF_JGT, ">", BPF_CC_GTU, BPF_CC_GTU_32>;
232 defm JUGE : J<BPF_JGE, ">=", BPF_CC_GEU, BPF_CC_GEU_32>;
233 defm JNE : J<BPF_JNE, "!=", BPF_CC_NE, BPF_CC_NE_32>;
234 defm JSGT : J<BPF_JSGT, "s>", BPF_CC_GT, BPF_CC_GT_32>;
235 defm JSGE : J<BPF_JSGE, "s>=", BPF_CC_GE, BPF_CC_GE_32>;
236 defm JULT : J<BPF_JLT, "<", BPF_CC_LTU, BPF_CC_LTU_32>;
237 defm JULE : J<BPF_JLE, "<=", BPF_CC_LEU, BPF_CC_LEU_32>;
238 defm JSLT : J<BPF_JSLT, "s<", BPF_CC_LT, BPF_CC_LT_32>;
239 defm JSLE : J<BPF_JSLE, "s<=", BPF_CC_LE, BPF_CC_LE_32>;
243 class ALU_RI<BPFOpClass Class, BPFArithOp Opc,
244 dag outs, dag ins, string asmstr, list<dag> pattern>
245 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, outs, ins, asmstr, pattern> {
249 let Inst{51-48} = dst;
250 let Inst{31-0} = imm;
251 let BPFClass = Class;
254 class ALU_RR<BPFOpClass Class, BPFArithOp Opc,
255 dag outs, dag ins, string asmstr, list<dag> pattern>
256 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, outs, ins, asmstr, pattern> {
260 let Inst{55-52} = src;
261 let Inst{51-48} = dst;
262 let BPFClass = Class;
265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
266 def _rr : ALU_RR<BPF_ALU64, Opc,
268 (ins GPR:$src2, GPR:$src),
269 "$dst "#OpcodeStr#" $src",
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
271 def _ri : ALU_RI<BPF_ALU64, Opc,
273 (ins GPR:$src2, i64imm:$imm),
274 "$dst "#OpcodeStr#" $imm",
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
276 def _rr_32 : ALU_RR<BPF_ALU, Opc,
278 (ins GPR32:$src2, GPR32:$src),
279 "$dst "#OpcodeStr#" $src",
280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
281 def _ri_32 : ALU_RI<BPF_ALU, Opc,
283 (ins GPR32:$src2, i32imm:$imm),
284 "$dst "#OpcodeStr#" $imm",
285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
288 let Constraints = "$dst = $src2" in {
289 let isAsCheapAsAMove = 1 in {
290 defm ADD : ALU<BPF_ADD, "+=", add>;
291 defm SUB : ALU<BPF_SUB, "-=", sub>;
292 defm OR : ALU<BPF_OR, "|=", or>;
293 defm AND : ALU<BPF_AND, "&=", and>;
294 defm SLL : ALU<BPF_LSH, "<<=", shl>;
295 defm SRL : ALU<BPF_RSH, ">>=", srl>;
296 defm XOR : ALU<BPF_XOR, "^=", xor>;
297 defm SRA : ALU<BPF_ARSH, "s>>=", sra>;
299 defm MUL : ALU<BPF_MUL, "*=", mul>;
300 defm DIV : ALU<BPF_DIV, "/=", udiv>;
303 class NEG_RR<BPFOpClass Class, BPFArithOp Opc,
304 dag outs, dag ins, string asmstr, list<dag> pattern>
305 : TYPE_ALU_JMP<Opc.Value, 0, outs, ins, asmstr, pattern> {
308 let Inst{51-48} = dst;
309 let BPFClass = Class;
312 let Constraints = "$dst = $src", isAsCheapAsAMove = 1 in {
313 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
315 [(set GPR:$dst, (ineg i64:$src))]>;
316 def NEG_32: NEG_RR<BPF_ALU, BPF_NEG, (outs GPR32:$dst), (ins GPR32:$src),
318 [(set GPR32:$dst, (ineg i32:$src))]>;
321 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
322 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
325 "$dst "#OpcodeStr#" ${imm} ll",
326 [(set GPR:$dst, (i64 imm:$imm))]> {
331 let Inst{51-48} = dst;
332 let Inst{55-52} = Pseudo;
334 let Inst{31-0} = imm{31-0};
335 let BPFClass = BPF_LD;
338 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
339 def LD_imm64 : LD_IMM64<0, "=">;
340 def MOV_rr : ALU_RR<BPF_ALU64, BPF_MOV,
345 def MOV_ri : ALU_RI<BPF_ALU64, BPF_MOV,
349 [(set GPR:$dst, (i64 i64immSExt32:$imm))]>;
350 def MOV_rr_32 : ALU_RR<BPF_ALU, BPF_MOV,
355 def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV,
359 [(set GPR32:$dst, (i32 i32immSExt32:$imm))]>;
363 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
367 [(set i64:$dst, FIri:$addr)]> {
368 // This is a tentative instruction, and will be replaced
369 // with MOV_rr and ADD_ri in PEI phase
374 let BPFClass = BPF_LD;
378 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
380 (ins i64imm:$pseudo, u64imm:$imm),
381 "ld_pseudo\t$dst, $pseudo, $imm",
382 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
388 let Inst{51-48} = dst;
389 let Inst{55-52} = pseudo;
391 let Inst{31-0} = imm{31-0};
392 let BPFClass = BPF_LD;
395 // STORE instructions
396 class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
397 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
399 (ins GPR:$src, MEMri:$addr),
400 "*("#OpcodeStr#" *)($addr) = $src",
405 let Inst{51-48} = addr{19-16}; // base reg
406 let Inst{55-52} = src;
407 let Inst{47-32} = addr{15-0}; // offset
408 let BPFClass = BPF_STX;
411 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
412 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
414 let Predicates = [BPFNoALU32] in {
415 def STW : STOREi64<BPF_W, "u32", truncstorei32>;
416 def STH : STOREi64<BPF_H, "u16", truncstorei16>;
417 def STB : STOREi64<BPF_B, "u8", truncstorei8>;
419 def STD : STOREi64<BPF_DW, "u64", store>;
422 class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
423 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
426 "$dst = *("#OpcodeStr#" *)($addr)",
431 let Inst{51-48} = dst;
432 let Inst{55-52} = addr{19-16};
433 let Inst{47-32} = addr{15-0};
434 let BPFClass = BPF_LDX;
437 class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
438 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
440 let isCodeGenOnly = 1 in {
441 def CORE_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value,
443 (ins u64imm:$opcode, GPR:$src, u64imm:$offset),
444 "$dst = core_mem($opcode, $src, $offset)",
446 def CORE_ALU32_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value,
448 (ins u64imm:$opcode, GPR:$src, u64imm:$offset),
449 "$dst = core_alu32_mem($opcode, $src, $offset)",
451 let Constraints = "$dst = $src" in {
452 def CORE_SHIFT : ALU_RR<BPF_ALU64, BPF_LSH,
454 (ins u64imm:$opcode, GPR:$src, u64imm:$offset),
455 "$dst = core_shift($opcode, $src, $offset)",
460 let Predicates = [BPFNoALU32] in {
461 def LDW : LOADi64<BPF_W, "u32", zextloadi32>;
462 def LDH : LOADi64<BPF_H, "u16", zextloadi16>;
463 def LDB : LOADi64<BPF_B, "u8", zextloadi8>;
466 def LDD : LOADi64<BPF_DW, "u64", load>;
468 class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern>
469 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
471 (ins brtarget:$BrDst),
472 !strconcat(OpcodeStr, " $BrDst"),
476 let Inst{47-32} = BrDst;
477 let BPFClass = BPF_JMP;
480 class CALL<string OpcodeStr>
481 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_K.Value,
483 (ins calltarget:$BrDst),
484 !strconcat(OpcodeStr, " $BrDst"),
488 let Inst{31-0} = BrDst;
489 let BPFClass = BPF_JMP;
492 class CALLX<string OpcodeStr>
493 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_X.Value,
496 !strconcat(OpcodeStr, " $BrDst"),
500 let Inst{31-0} = BrDst;
501 let BPFClass = BPF_JMP;
505 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
506 def JMP : BRANCH<BPF_JA, "goto", [(br bb:$BrDst)]>;
510 let isCall=1, hasDelaySlot=0, Uses = [R11],
511 // Potentially clobbered registers
512 Defs = [R0, R1, R2, R3, R4, R5] in {
513 def JAL : CALL<"call">;
514 def JALX : CALLX<"callx">;
517 class NOP_I<string OpcodeStr>
518 : TYPE_ALU_JMP<BPF_MOV.Value, BPF_X.Value,
521 !strconcat(OpcodeStr, "\t$imm"),
526 let BPFClass = BPF_ALU64;
529 let hasSideEffects = 0 in
530 def NOP : NOP_I<"nop">;
532 class RET<string OpcodeStr>
533 : TYPE_ALU_JMP<BPF_EXIT.Value, BPF_K.Value,
536 !strconcat(OpcodeStr, ""),
539 let BPFClass = BPF_JMP;
542 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
543 isNotDuplicable = 1 in {
544 def RET : RET<"exit">;
547 // ADJCALLSTACKDOWN/UP pseudo insns
548 let Defs = [R11], Uses = [R11], isCodeGenOnly = 1 in {
549 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
550 "#ADJCALLSTACKDOWN $amt1 $amt2",
551 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
552 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
553 "#ADJCALLSTACKUP $amt1 $amt2",
554 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
557 let usesCustomInserter = 1, isCodeGenOnly = 1 in {
558 def Select : Pseudo<(outs GPR:$dst),
559 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
560 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
562 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
563 def Select_Ri : Pseudo<(outs GPR:$dst),
564 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
565 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
567 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>;
568 def Select_64_32 : Pseudo<(outs GPR32:$dst),
569 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2),
570 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
572 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i32:$src, i32:$src2))]>;
573 def Select_Ri_64_32 : Pseudo<(outs GPR32:$dst),
574 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2),
575 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
577 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i32:$src, i32:$src2))]>;
578 def Select_32 : Pseudo<(outs GPR32:$dst),
579 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2),
580 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
582 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i32:$src, i32:$src2))]>;
583 def Select_Ri_32 : Pseudo<(outs GPR32:$dst),
584 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2),
585 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
587 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i32:$src, i32:$src2))]>;
588 def Select_32_64 : Pseudo<(outs GPR:$dst),
589 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR:$src, GPR:$src2),
590 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
592 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i64:$src, i64:$src2))]>;
593 def Select_Ri_32_64 : Pseudo<(outs GPR:$dst),
594 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR:$src, GPR:$src2),
595 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
597 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i64:$src, i64:$src2))]>;
600 // load 64-bit global addr into register
601 def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
603 // 0xffffFFFF doesn't fit into simm32, optimize common case
604 def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
605 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
608 def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
609 def : Pat<(BPFcall texternalsym:$dst), (JAL texternalsym:$dst)>;
610 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
611 def : Pat<(BPFcall GPR:$dst), (JALX GPR:$dst)>;
614 let Predicates = [BPFNoALU32] in {
615 def : Pat<(i64 (extloadi8 ADDRri:$src)), (i64 (LDB ADDRri:$src))>;
616 def : Pat<(i64 (extloadi16 ADDRri:$src)), (i64 (LDH ADDRri:$src))>;
617 def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>;
621 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
622 : TYPE_LD_ST<BPF_XADD.Value, SizeOp.Value,
624 (ins MEMri:$addr, GPR:$val),
625 "lock *("#OpcodeStr#" *)($addr) += $val",
626 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
630 let Inst{51-48} = addr{19-16}; // base reg
631 let Inst{55-52} = dst;
632 let Inst{47-32} = addr{15-0}; // offset
633 let BPFClass = BPF_STX;
636 class XADD32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
637 : TYPE_LD_ST<BPF_XADD.Value, SizeOp.Value,
639 (ins MEMri:$addr, GPR32:$val),
640 "lock *("#OpcodeStr#" *)($addr) += $val",
641 [(set GPR32:$dst, (OpNode ADDRri:$addr, GPR32:$val))]> {
645 let Inst{51-48} = addr{19-16}; // base reg
646 let Inst{55-52} = dst;
647 let Inst{47-32} = addr{15-0}; // offset
648 let BPFClass = BPF_STX;
651 let Constraints = "$dst = $val" in {
652 let Predicates = [BPFNoALU32] in {
653 def XADDW : XADD<BPF_W, "u32", atomic_load_add_32>;
656 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
657 def XADDW32 : XADD32<BPF_W, "u32", atomic_load_add_32>;
660 def XADDD : XADD<BPF_DW, "u64", atomic_load_add_64>;
663 // bswap16, bswap32, bswap64
664 class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern>
665 : TYPE_ALU_JMP<BPF_END.Value, SrcType.Value,
668 "$dst = "#OpcodeStr#" $src",
672 let Inst{51-48} = dst;
673 let Inst{31-0} = SizeOp;
674 let BPFClass = BPF_ALU;
678 let Constraints = "$dst = $src" in {
679 let Predicates = [BPFIsLittleEndian] in {
680 def BE16 : BSWAP<16, "be16", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
681 def BE32 : BSWAP<32, "be32", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
682 def BE64 : BSWAP<64, "be64", BPF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>;
684 let Predicates = [BPFIsBigEndian] in {
685 def LE16 : BSWAP<16, "le16", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
686 def LE32 : BSWAP<32, "le32", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
687 def LE64 : BSWAP<64, "le64", BPF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>;
691 let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
692 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
693 class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
694 : TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value,
696 (ins GPR:$skb, i64imm:$imm),
697 "r0 = *("#OpcodeStr#" *)skb[$imm]",
698 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
701 let Inst{31-0} = imm;
702 let BPFClass = BPF_LD;
705 class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
706 : TYPE_LD_ST<BPF_IND.Value, SizeOp.Value,
708 (ins GPR:$skb, GPR:$val),
709 "r0 = *("#OpcodeStr#" *)skb[$val]",
710 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
713 let Inst{55-52} = val;
714 let BPFClass = BPF_LD;
718 def LD_ABS_B : LOAD_ABS<BPF_B, "u8", int_bpf_load_byte>;
719 def LD_ABS_H : LOAD_ABS<BPF_H, "u16", int_bpf_load_half>;
720 def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>;
722 def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>;
723 def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>;
724 def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>;
726 let isCodeGenOnly = 1 in {
727 def MOV_32_64 : ALU_RR<BPF_ALU, BPF_MOV,
728 (outs GPR:$dst), (ins GPR32:$src),
732 def : Pat<(i64 (sext GPR32:$src)),
733 (SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>;
735 def : Pat<(i64 (zext GPR32:$src)),
736 (SRL_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>;
738 // For i64 -> i32 truncation, use the 32-bit subregister directly.
739 def : Pat<(i32 (trunc GPR:$src)),
740 (i32 (EXTRACT_SUBREG GPR:$src, sub_32))>;
742 // For i32 -> i64 anyext, we don't care about the high bits.
743 def : Pat<(i64 (anyext GPR32:$src)),
744 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
746 class STORE32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
747 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
749 (ins GPR32:$src, MEMri:$addr),
750 "*("#OpcodeStr#" *)($addr) = $src",
755 let Inst{51-48} = addr{19-16}; // base reg
756 let Inst{55-52} = src;
757 let Inst{47-32} = addr{15-0}; // offset
758 let BPFClass = BPF_STX;
761 class STOREi32<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
762 : STORE32<Opc, OpcodeStr, [(OpNode i32:$src, ADDRri:$addr)]>;
764 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
765 def STW32 : STOREi32<BPF_W, "u32", store>;
766 def STH32 : STOREi32<BPF_H, "u16", truncstorei16>;
767 def STB32 : STOREi32<BPF_B, "u8", truncstorei8>;
770 class LOAD32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
771 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
774 "$dst = *("#OpcodeStr#" *)($addr)",
779 let Inst{51-48} = dst;
780 let Inst{55-52} = addr{19-16};
781 let Inst{47-32} = addr{15-0};
782 let BPFClass = BPF_LDX;
785 class LOADi32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
786 : LOAD32<SizeOp, OpcodeStr, [(set i32:$dst, (OpNode ADDRri:$addr))]>;
788 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
789 def LDW32 : LOADi32<BPF_W, "u32", load>;
790 def LDH32 : LOADi32<BPF_H, "u16", zextloadi16>;
791 def LDB32 : LOADi32<BPF_B, "u8", zextloadi8>;
794 let Predicates = [BPFHasALU32] in {
795 def : Pat<(truncstorei8 GPR:$src, ADDRri:$dst),
796 (STB32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>;
797 def : Pat<(truncstorei16 GPR:$src, ADDRri:$dst),
798 (STH32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>;
799 def : Pat<(truncstorei32 GPR:$src, ADDRri:$dst),
800 (STW32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>;
801 def : Pat<(i32 (extloadi8 ADDRri:$src)), (i32 (LDB32 ADDRri:$src))>;
802 def : Pat<(i32 (extloadi16 ADDRri:$src)), (i32 (LDH32 ADDRri:$src))>;
803 def : Pat<(i64 (zextloadi8 ADDRri:$src)),
804 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>;
805 def : Pat<(i64 (zextloadi16 ADDRri:$src)),
806 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>;
807 def : Pat<(i64 (zextloadi32 ADDRri:$src)),
808 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>;
809 def : Pat<(i64 (extloadi8 ADDRri:$src)),
810 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>;
811 def : Pat<(i64 (extloadi16 ADDRri:$src)),
812 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>;
813 def : Pat<(i64 (extloadi32 ADDRri:$src)),
814 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>;
817 let usesCustomInserter = 1, isCodeGenOnly = 1 in {
820 (ins GPR:$dst, GPR:$src, i64imm:$len, i64imm:$align, variable_ops),
821 "#memcpy dst: $dst, src: $src, len: $len, align: $align",
822 [(BPFmemcpy GPR:$dst, GPR:$src, imm:$len, imm:$align)]>;