1 //===----- BPFMISimplifyPatchable.cpp - MI Simplify Patchable Insts -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This pass targets a subset of instructions like below
10 // ld_imm64 r1, @global
12 // add r3, struct_base_reg, r2
14 // Here @global should represent an AMA (abstruct member access).
15 // Such an access is subject to bpf load time patching. After this pass, the
17 // ld_imm64 r1, @global
18 // add r3, struct_base_reg, r1
20 // Eventually, at BTF output stage, a relocation record will be generated
21 // for ld_imm64 which should be replaced later by bpf loader:
22 // r1 = <calculated field_info>
23 // add r3, struct_base_reg, r1
25 // This pass also removes the intermediate load generated in IR pass for
26 // __builtin_btf_type_id() intrinsic.
28 //===----------------------------------------------------------------------===//
32 #include "BPFInstrInfo.h"
33 #include "BPFTargetMachine.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Support/Debug.h"
42 #define DEBUG_TYPE "bpf-mi-simplify-patchable"
46 struct BPFMISimplifyPatchable : public MachineFunctionPass {
49 const BPFInstrInfo *TII;
52 BPFMISimplifyPatchable() : MachineFunctionPass(ID) {
53 initializeBPFMISimplifyPatchablePass(*PassRegistry::getPassRegistry());
57 std::set<MachineInstr *> SkipInsts;
59 // Initialize class variables.
60 void initialize(MachineFunction &MFParm);
62 bool isLoadInst(unsigned Opcode);
64 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
65 MachineInstr &MI, Register &SrcReg, Register &DstReg,
66 const GlobalValue *GVal, bool IsAma);
67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
68 Register &SrcReg, const GlobalValue *GVal,
69 bool doSrcRegProp, bool IsAma);
70 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
71 MachineOperand *RelocOp, const GlobalValue *GVal);
72 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
73 const GlobalValue *GVal);
74 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
75 MachineOperand *RelocOp, const GlobalValue *GVal,
79 // Main entry point for this pass.
80 bool runOnMachineFunction(MachineFunction &MF) override {
81 if (skipFunction(MF.getFunction()))
89 // Initialize class variables.
90 void BPFMISimplifyPatchable::initialize(MachineFunction &MFParm) {
92 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
93 LLVM_DEBUG(dbgs() << "*** BPF simplify patchable insts pass ***\n\n");
96 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) {
97 return Opcode == BPF::LDD || Opcode == BPF::LDW || Opcode == BPF::LDH ||
98 Opcode == BPF::LDB || Opcode == BPF::LDW32 || Opcode == BPF::LDH32 ||
102 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI,
103 MachineOperand *RelocOp, const GlobalValue *GVal) {
104 const MachineInstr *Inst = RelocOp->getParent();
105 const MachineOperand *Op1 = &Inst->getOperand(1);
106 const MachineOperand *Op2 = &Inst->getOperand(2);
107 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1;
109 // Go through all uses of %1 as in %1 = ADD_rr %2, %3
110 const MachineOperand Op0 = Inst->getOperand(0);
111 for (MachineOperand &MO :
112 llvm::make_early_inc_range(MRI->use_operands(Op0.getReg()))) {
113 // The candidate needs to have a unique definition.
114 if (!MRI->getUniqueVRegDef(MO.getReg()))
117 MachineInstr *DefInst = MO.getParent();
118 unsigned Opcode = DefInst->getOpcode();
120 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW ||
121 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH ||
122 Opcode == BPF::STW || Opcode == BPF::STD)
123 COREOp = BPF::CORE_MEM;
124 else if (Opcode == BPF::LDB32 || Opcode == BPF::LDH32 ||
125 Opcode == BPF::LDW32 || Opcode == BPF::STB32 ||
126 Opcode == BPF::STH32 || Opcode == BPF::STW32)
127 COREOp = BPF::CORE_ALU32_MEM;
131 // It must be a form of %2 = *(type *)(%1 + 0) or *(type *)(%1 + 0) = %2.
132 const MachineOperand &ImmOp = DefInst->getOperand(2);
133 if (!ImmOp.isImm() || ImmOp.getImm() != 0)
137 // %1 = ADD_rr %2, %3
138 // *(type *)(%2 + 0) = %1
139 if (Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW ||
140 Opcode == BPF::STD || Opcode == BPF::STB32 || Opcode == BPF::STH32 ||
141 Opcode == BPF::STW32) {
142 const MachineOperand &Opnd = DefInst->getOperand(0);
143 if (Opnd.isReg() && Opnd.getReg() == MO.getReg())
147 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp))
148 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp)
149 .addGlobalAddress(GVal);
150 DefInst->eraseFromParent();
154 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI,
155 MachineBasicBlock &MBB, MachineOperand *RelocOp, const GlobalValue *GVal,
157 // Relocation operand should be the operand #2.
158 MachineInstr *Inst = RelocOp->getParent();
159 if (RelocOp != &Inst->getOperand(2))
162 BuildMI(MBB, *Inst, Inst->getDebugLoc(), TII->get(BPF::CORE_SHIFT))
163 .add(Inst->getOperand(0)).addImm(Opcode)
164 .add(Inst->getOperand(1)).addGlobalAddress(GVal);
165 Inst->eraseFromParent();
168 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI,
169 MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg,
170 Register &DstReg, const GlobalValue *GVal, bool IsAma) {
171 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
173 // We can optimize such a pattern:
174 // %1:gpr = LD_imm64 @"llvm.s:0:4$0:2"
175 // %2:gpr32 = LDW32 %1:gpr, 0
176 // %3:gpr = SUBREG_TO_REG 0, %2:gpr32, %subreg.sub_32
177 // %4:gpr = ADD_rr %0:gpr, %3:gpr
178 // or similar patterns below for non-alu32 case.
179 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end();
181 for (auto I = Begin; I != End; I = NextI) {
182 NextI = std::next(I);
183 if (!MRI->getUniqueVRegDef(I->getReg()))
186 unsigned Opcode = I->getParent()->getOpcode();
187 if (Opcode == BPF::SUBREG_TO_REG) {
188 Register TmpReg = I->getParent()->getOperand(0).getReg();
189 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma);
194 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
195 .addReg(SrcReg, 0, BPF::sub_32);
199 // All uses of DstReg replaced by SrcReg
200 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma);
203 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI,
204 Register &DstReg, Register &SrcReg, const GlobalValue *GVal,
205 bool doSrcRegProp, bool IsAma) {
206 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end();
208 for (auto I = Begin; I != End; I = NextI) {
209 NextI = std::next(I);
213 // The candidate needs to have a unique definition.
214 if (IsAma && MRI->getUniqueVRegDef(I->getReg()))
215 processInst(MRI, I->getParent(), &*I, GVal);
219 // Check to see whether we could do some optimization
220 // to attach relocation to downstream dependent instructions.
221 // Two kinds of patterns are recognized below:
223 // %1 = LD_imm64 @"llvm.b:0:4$0:1" <== patch_imm = 4
224 // %2 = LDD %1, 0 <== this insn will be removed
225 // %3 = ADD_rr %0, %2
226 // %4 = LDW[32] %3, 0 OR STW[32] %4, %3, 0
227 // The `%4 = ...` will be transformed to
228 // CORE_[ALU32_]MEM(%4, mem_opcode, %0, @"llvm.b:0:4$0:1")
229 // and later on, BTF emit phase will translate to
230 // %4 = LDW[32] %0, 4 STW[32] %4, %0, 4
231 // and attach a relocation to it.
233 // %15 = LD_imm64 @"llvm.t:5:63$0:2" <== relocation type 5
234 // %16 = LDD %15, 0 <== this insn will be removed
235 // %17 = SRA_rr %14, %16
236 // The `%17 = ...` will be transformed to
237 // %17 = CORE_SHIFT(SRA_ri, %14, @"llvm.t:5:63$0:2")
238 // and later on, BTF emit phase will translate to
239 // %r4 = SRA_ri %r4, 63
240 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI,
241 MachineInstr *Inst, MachineOperand *RelocOp, const GlobalValue *GVal) {
242 unsigned Opcode = Inst->getOpcode();
243 if (isLoadInst(Opcode)) {
244 SkipInsts.insert(Inst);
248 if (Opcode == BPF::ADD_rr)
249 checkADDrr(MRI, RelocOp, GVal);
250 else if (Opcode == BPF::SLL_rr)
251 checkShift(MRI, *Inst->getParent(), RelocOp, GVal, BPF::SLL_ri);
252 else if (Opcode == BPF::SRA_rr)
253 checkShift(MRI, *Inst->getParent(), RelocOp, GVal, BPF::SRA_ri);
254 else if (Opcode == BPF::SRL_rr)
255 checkShift(MRI, *Inst->getParent(), RelocOp, GVal, BPF::SRL_ri);
258 /// Remove unneeded Load instructions.
259 bool BPFMISimplifyPatchable::removeLD() {
260 MachineRegisterInfo *MRI = &MF->getRegInfo();
261 MachineInstr *ToErase = nullptr;
262 bool Changed = false;
264 for (MachineBasicBlock &MBB : *MF) {
265 for (MachineInstr &MI : MBB) {
267 ToErase->eraseFromParent();
271 // Ensure the register format is LOAD <reg>, <reg>, 0
272 if (!isLoadInst(MI.getOpcode()))
275 if (SkipInsts.find(&MI) != SkipInsts.end())
278 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg())
281 if (!MI.getOperand(2).isImm() || MI.getOperand(2).getImm())
284 Register DstReg = MI.getOperand(0).getReg();
285 Register SrcReg = MI.getOperand(1).getReg();
287 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg);
291 if (DefInst->getOpcode() != BPF::LD_imm64)
294 const MachineOperand &MO = DefInst->getOperand(1);
298 const GlobalValue *GVal = MO.getGlobal();
299 auto *GVar = dyn_cast<GlobalVariable>(GVal);
303 // Global variables representing structure offset or type id.
305 if (GVar->hasAttribute(BPFCoreSharedInfo::AmaAttr))
307 else if (!GVar->hasAttribute(BPFCoreSharedInfo::TypeIdAttr))
310 processCandidate(MRI, MBB, MI, SrcReg, DstReg, GVal, IsAma);
322 INITIALIZE_PASS(BPFMISimplifyPatchable, DEBUG_TYPE,
323 "BPF PreEmit SimplifyPatchable", false, false)
325 char BPFMISimplifyPatchable::ID = 0;
326 FunctionPass *llvm::createBPFMISimplifyPatchablePass() {
327 return new BPFMISimplifyPatchable();