1 //===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains small standalone helper functions and enum definitions for
10 // the Hexagon target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
17 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
19 #include "HexagonDepITypes.h"
20 #include "MCTargetDesc/HexagonMCTargetDesc.h"
24 /// HexagonII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
27 unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY;
28 unsigned const TypeCVI_LAST = TypeCVI_ZW;
36 NoAddrMode = 0, // No addressing mode
37 Absolute = 1, // Absolute addressing mode
38 AbsoluteSet = 2, // Absolute set addressing mode
39 BaseImmOffset = 3, // Indirect with offset
40 BaseLongOffset = 4, // Indirect with long offset
41 BaseRegOffset = 5, // Indirect with register offset
42 PostInc = 6 // Post increment addressing mode
54 // MCInstrDesc TSFlags
55 // *** Must match HexagonInstrFormat*.td ***
57 // This 7-bit field describes the insn type.
64 // Packed only with A or X-type instructions.
67 // Only A-type instruction in first slot or nothing.
68 RestrictSlot1AOKPos = 9,
69 RestrictSlot1AOKMask = 0x1,
71 // Predicated instructions.
74 PredicatedFalsePos = 11,
75 PredicatedFalseMask = 0x1,
76 PredicatedNewPos = 12,
77 PredicatedNewMask = 0x1,
78 PredicateLatePos = 13,
79 PredicateLateMask = 0x1,
81 // New-Value consumer instructions.
84 // New-Value producer instructions.
86 hasNewValueMask = 0x1,
87 // Which operand consumes or produces a new value.
90 // Stores that can become new-value stores.
93 // New-value store instructions.
96 // Loads that can become current-value loads.
99 // Current-value load instructions.
105 ExtendableMask = 0x1,
106 // Insns must be extended.
109 // Which operand may be extended.
110 ExtendableOpPos = 25,
111 ExtendableOpMask = 0x7,
112 // Signed or unsigned range.
113 ExtentSignedPos = 28,
114 ExtentSignedMask = 0x1,
115 // Number of bits of range before extending operand.
117 ExtentBitsMask = 0x1f,
118 // Alignment power-of-two before extending operand.
120 ExtentAlignMask = 0x3,
129 RestrictNoSlot1StorePos = 39,
130 RestrictNoSlot1StoreMask = 0x1,
132 // Addressing mode for load/store instructions.
135 // Access size for load/store instructions.
136 MemAccessSizePos = 45,
137 MemAccesSizeMask = 0xf,
139 // Branch predicted taken.
143 // Floating-point instructions.
147 // New-Value producer-2 instructions.
148 hasNewValuePos2 = 52,
149 hasNewValueMask2 = 0x1,
150 // Which operand consumes or produces a new value.
152 NewValueOpMask2 = 0x7,
154 // Accumulator instructions.
156 AccumulatorMask = 0x1,
158 // Complex XU, prevent xu competition by preferring slot3
159 PrefersSlot3Pos = 57,
160 PrefersSlot3Mask = 0x1,
170 // *** The code above must match HexagonInstrFormat*.td *** //
172 // Hexagon specific MO operand flag mask.
173 enum HexagonMOTargetFlagVal {
174 // Hexagon-specific MachineOperand target flags.
176 // When changing these, make sure to update
177 // getSerializableDirectMachineOperandTargetFlags and
178 // getSerializableBitmaskMachineOperandTargetFlags if needed.
181 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
182 /// Used for computing a global address for PIC compilations
185 /// MO_GOT - Indicates a GOT-relative relocation
188 // Low or high part of a symbol.
192 // Offset from the base of the SDA.
195 // MO_GDGOT - indicates GOT relative relocation for TLS
196 // GeneralDynamic method
199 // MO_GDPLT - indicates PLT relative relocation for TLS
200 // GeneralDynamic method
203 // MO_IE - indicates non PIC relocation for TLS
204 // Initial Executable method
207 // MO_IEGOT - indicates PIC relocation for TLS
208 // Initial Executable method
211 // MO_TPREL - indicates relocation for TLS
212 // local Executable method
215 // HMOTF_ConstExtended
216 // Addendum to above, indicates a const extended op
217 // Can be used as a mask.
218 HMOTF_ConstExtended = 0x80,
220 // Union of all bitmasks (currently only HMOTF_ConstExtended).
221 MO_Bitmasks = HMOTF_ConstExtended
224 // Hexagon Sub-instruction classes.
225 enum SubInstructionGroup {
235 // Hexagon Compound classes.
244 INST_PARSE_MASK = 0x0000c000,
245 INST_PARSE_PACKET_END = 0x0000c000,
246 INST_PARSE_LOOP_END = 0x00008000,
247 INST_PARSE_NOT_END = 0x00004000,
248 INST_PARSE_DUPLEX = 0x00000000,
249 INST_PARSE_EXTENDER = 0x00000000
252 enum InstIClassBits : unsigned {
253 INST_ICLASS_MASK = 0xf0000000,
254 INST_ICLASS_EXTENDER = 0x00000000,
255 INST_ICLASS_J_1 = 0x10000000,
256 INST_ICLASS_J_2 = 0x20000000,
257 INST_ICLASS_LD_ST_1 = 0x30000000,
258 INST_ICLASS_LD_ST_2 = 0x40000000,
259 INST_ICLASS_J_3 = 0x50000000,
260 INST_ICLASS_CR = 0x60000000,
261 INST_ICLASS_ALU32_1 = 0x70000000,
262 INST_ICLASS_XTYPE_1 = 0x80000000,
263 INST_ICLASS_LD = 0x90000000,
264 INST_ICLASS_ST = 0xa0000000,
265 INST_ICLASS_ALU32_2 = 0xb0000000,
266 INST_ICLASS_XTYPE_2 = 0xc0000000,
267 INST_ICLASS_XTYPE_3 = 0xd0000000,
268 INST_ICLASS_XTYPE_4 = 0xe0000000,
269 INST_ICLASS_ALU32_3 = 0xf0000000
272 LLVM_ATTRIBUTE_UNUSED
273 static unsigned getMemAccessSizeInBytes(MemAccessSize S) {
275 case ByteAccess: return 1;
276 case HalfWordAccess: return 2;
277 case WordAccess: return 4;
278 case DoubleWordAccess: return 8;
282 } // end namespace HexagonII
284 } // end namespace llvm
286 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H