1 //===-- LanaiInstrInfo.cpp - Lanai Instruction Information ------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the Lanai implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "LanaiInstrInfo.h"
14 #include "LanaiAluCode.h"
15 #include "LanaiCondCode.h"
16 #include "MCTargetDesc/LanaiBaseInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "LanaiGenInstrInfo.inc"
30 LanaiInstrInfo::LanaiInstrInfo()
31 : LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
34 void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator Position,
37 unsigned DestinationRegister,
38 unsigned SourceRegister,
39 bool KillSource) const {
40 if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
41 llvm_unreachable("Impossible reg-to-reg copy");
44 BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
45 .addReg(SourceRegister, getKillRegState(KillSource))
49 void LanaiInstrInfo::storeRegToStackSlot(
50 MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
51 unsigned SourceRegister, bool IsKill, int FrameIndex,
52 const TargetRegisterClass *RegisterClass,
53 const TargetRegisterInfo * /*RegisterInfo*/) const {
55 if (Position != MBB.end()) {
56 DL = Position->getDebugLoc();
59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
60 llvm_unreachable("Can't store this register to stack slot");
62 BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
63 .addReg(SourceRegister, getKillRegState(IsKill))
64 .addFrameIndex(FrameIndex)
69 void LanaiInstrInfo::loadRegFromStackSlot(
70 MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
71 unsigned DestinationRegister, int FrameIndex,
72 const TargetRegisterClass *RegisterClass,
73 const TargetRegisterInfo * /*RegisterInfo*/) const {
75 if (Position != MBB.end()) {
76 DL = Position->getDebugLoc();
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
80 llvm_unreachable("Can't load this register from stack slot");
82 BuildMI(MBB, Position, DL, get(Lanai::LDW_RI), DestinationRegister)
83 .addFrameIndex(FrameIndex)
88 bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
89 const MachineInstr &MIa, const MachineInstr &MIb) const {
90 assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
97 // Retrieve the base register, offset from the base register and width. Width
98 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
99 // base registers are identical, and the offset of a lower memory access +
100 // the width doesn't overlap the offset of a higher memory access,
101 // then the memory accesses are different.
102 const TargetRegisterInfo *TRI = &getRegisterInfo();
103 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
104 int64_t OffsetA = 0, OffsetB = 0;
105 unsigned int WidthA = 0, WidthB = 0;
106 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
108 if (BaseOpA->isIdenticalTo(*BaseOpB)) {
109 int LowOffset = std::min(OffsetA, OffsetB);
110 int HighOffset = std::max(OffsetA, OffsetB);
111 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
112 if (LowOffset + LowWidth <= HighOffset)
119 bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr & /*MI*/) const {
123 static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) {
125 case LPCC::ICC_T: // true
127 case LPCC::ICC_F: // false
129 case LPCC::ICC_HI: // high
131 case LPCC::ICC_LS: // low or same
133 case LPCC::ICC_CC: // carry cleared
135 case LPCC::ICC_CS: // carry set
137 case LPCC::ICC_NE: // not equal
139 case LPCC::ICC_EQ: // equal
141 case LPCC::ICC_VC: // oVerflow cleared
143 case LPCC::ICC_VS: // oVerflow set
145 case LPCC::ICC_PL: // plus (note: 0 is "minus" too here)
147 case LPCC::ICC_MI: // minus
149 case LPCC::ICC_GE: // greater than or equal
151 case LPCC::ICC_LT: // less than
153 case LPCC::ICC_GT: // greater than
155 case LPCC::ICC_LE: // less than or equal
158 llvm_unreachable("Invalid condtional code");
162 std::pair<unsigned, unsigned>
163 LanaiInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
164 return std::make_pair(TF, 0u);
167 ArrayRef<std::pair<unsigned, const char *>>
168 LanaiInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
169 using namespace LanaiII;
170 static const std::pair<unsigned, const char *> TargetFlags[] = {
171 {MO_ABS_HI, "lanai-hi"},
172 {MO_ABS_LO, "lanai-lo"},
173 {MO_NO_FLAG, "lanai-nf"}};
174 return makeArrayRef(TargetFlags);
177 bool LanaiInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
178 unsigned &SrcReg2, int &CmpMask,
179 int &CmpValue) const {
180 switch (MI.getOpcode()) {
183 case Lanai::SFSUB_F_RI_LO:
184 case Lanai::SFSUB_F_RI_HI:
185 SrcReg = MI.getOperand(0).getReg();
188 CmpValue = MI.getOperand(1).getImm();
190 case Lanai::SFSUB_F_RR:
191 SrcReg = MI.getOperand(0).getReg();
192 SrcReg2 = MI.getOperand(1).getReg();
201 // isRedundantFlagInstr - check whether the first instruction, whose only
202 // purpose is to update flags, can be made redundant.
203 // * SFSUB_F_RR can be made redundant by SUB_RI if the operands are the same.
204 // * SFSUB_F_RI can be made redundant by SUB_I if the operands are the same.
205 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
206 unsigned SrcReg2, int ImmValue,
208 if (CmpI->getOpcode() == Lanai::SFSUB_F_RR &&
209 OI->getOpcode() == Lanai::SUB_R &&
210 ((OI->getOperand(1).getReg() == SrcReg &&
211 OI->getOperand(2).getReg() == SrcReg2) ||
212 (OI->getOperand(1).getReg() == SrcReg2 &&
213 OI->getOperand(2).getReg() == SrcReg)))
216 if (((CmpI->getOpcode() == Lanai::SFSUB_F_RI_LO &&
217 OI->getOpcode() == Lanai::SUB_I_LO) ||
218 (CmpI->getOpcode() == Lanai::SFSUB_F_RI_HI &&
219 OI->getOpcode() == Lanai::SUB_I_HI)) &&
220 OI->getOperand(1).getReg() == SrcReg &&
221 OI->getOperand(2).getImm() == ImmValue)
226 inline static unsigned flagSettingOpcodeVariant(unsigned OldOpcode) {
228 case Lanai::ADD_I_HI:
229 return Lanai::ADD_F_I_HI;
230 case Lanai::ADD_I_LO:
231 return Lanai::ADD_F_I_LO;
233 return Lanai::ADD_F_R;
234 case Lanai::ADDC_I_HI:
235 return Lanai::ADDC_F_I_HI;
236 case Lanai::ADDC_I_LO:
237 return Lanai::ADDC_F_I_LO;
239 return Lanai::ADDC_F_R;
240 case Lanai::AND_I_HI:
241 return Lanai::AND_F_I_HI;
242 case Lanai::AND_I_LO:
243 return Lanai::AND_F_I_LO;
245 return Lanai::AND_F_R;
247 return Lanai::OR_F_I_HI;
249 return Lanai::OR_F_I_LO;
251 return Lanai::OR_F_R;
253 return Lanai::SL_F_I;
255 return Lanai::SRL_F_R;
257 return Lanai::SA_F_I;
259 return Lanai::SRA_F_R;
260 case Lanai::SUB_I_HI:
261 return Lanai::SUB_F_I_HI;
262 case Lanai::SUB_I_LO:
263 return Lanai::SUB_F_I_LO;
265 return Lanai::SUB_F_R;
266 case Lanai::SUBB_I_HI:
267 return Lanai::SUBB_F_I_HI;
268 case Lanai::SUBB_I_LO:
269 return Lanai::SUBB_F_I_LO;
271 return Lanai::SUBB_F_R;
272 case Lanai::XOR_I_HI:
273 return Lanai::XOR_F_I_HI;
274 case Lanai::XOR_I_LO:
275 return Lanai::XOR_F_I_LO;
277 return Lanai::XOR_F_R;
283 bool LanaiInstrInfo::optimizeCompareInstr(
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/,
285 int CmpValue, const MachineRegisterInfo *MRI) const {
286 // Get the unique definition of SrcReg.
287 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
291 // Get ready to iterate backward from CmpInstr.
292 MachineBasicBlock::iterator I = CmpInstr, E = MI,
293 B = CmpInstr.getParent()->begin();
295 // Early exit if CmpInstr is at the beginning of the BB.
299 // There are two possible candidates which can be changed to set SR:
300 // One is MI, the other is a SUB instruction.
301 // * For SFSUB_F_RR(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
302 // * For SFSUB_F_RI(r1, CmpValue), we are looking for SUB(r1, CmpValue).
303 MachineInstr *Sub = nullptr;
305 // MI is not a candidate to transform into a flag setting instruction.
307 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
308 // Conservatively refuse to convert an instruction which isn't in the same
309 // BB as the comparison. Don't return if SFSUB_F_RI and CmpValue != 0 as Sub
310 // may still be a candidate.
311 if (CmpInstr.getOpcode() == Lanai::SFSUB_F_RI_LO)
317 // Check that SR isn't set between the comparison instruction and the
318 // instruction we want to change while searching for Sub.
319 const TargetRegisterInfo *TRI = &getRegisterInfo();
320 for (--I; I != E; --I) {
321 const MachineInstr &Instr = *I;
323 if (Instr.modifiesRegister(Lanai::SR, TRI) ||
324 Instr.readsRegister(Lanai::SR, TRI))
325 // This instruction modifies or uses SR after the one we want to change.
326 // We can't do this transformation.
329 // Check whether CmpInstr can be made redundant by the current instruction.
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
335 // Don't search outside the containing basic block.
340 // Return false if no candidates exist.
344 // The single candidate is called MI.
348 if (flagSettingOpcodeVariant(MI->getOpcode()) != Lanai::NOP) {
351 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4>
354 E = CmpInstr.getParent()->end();
355 while (!isSafe && ++I != E) {
356 const MachineInstr &Instr = *I;
357 for (unsigned IO = 0, EO = Instr.getNumOperands(); !isSafe && IO != EO;
359 const MachineOperand &MO = Instr.getOperand(IO);
360 if (MO.isRegMask() && MO.clobbersPhysReg(Lanai::SR)) {
364 if (!MO.isReg() || MO.getReg() != Lanai::SR)
370 // Condition code is after the operand before SR.
372 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
375 LPCC::CondCode NewCC = getOppositeCondition(CC);
376 if (NewCC == LPCC::ICC_T)
378 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on
379 // CMP needs to be updated to be based on SUB. Push the condition
380 // code operands to OperandsToUpdate. If it is safe to remove
381 // CmpInstr, the condition code of these operands will be modified.
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
383 Sub->getOperand(2).getReg() == SrcReg) {
384 OperandsToUpdate.push_back(
385 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
388 // No Sub, so this is x = <op> y, z; cmp x, 0.
390 case LPCC::ICC_EQ: // Z
391 case LPCC::ICC_NE: // Z
392 case LPCC::ICC_MI: // N
393 case LPCC::ICC_PL: // N
394 case LPCC::ICC_F: // none
395 case LPCC::ICC_T: // none
396 // SR can be used multiple times, we should continue.
398 case LPCC::ICC_CS: // C
399 case LPCC::ICC_CC: // C
400 case LPCC::ICC_VS: // V
401 case LPCC::ICC_VC: // V
402 case LPCC::ICC_HI: // C Z
403 case LPCC::ICC_LS: // C Z
404 case LPCC::ICC_GE: // N V
405 case LPCC::ICC_LT: // N V
406 case LPCC::ICC_GT: // Z N V
407 case LPCC::ICC_LE: // Z N V
408 // The instruction uses the V bit or C bit which is not safe.
417 // If SR is not killed nor re-defined, we should check whether it is
418 // live-out. If it is live-out, do not optimize.
420 MachineBasicBlock *MBB = CmpInstr.getParent();
421 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
422 SE = MBB->succ_end();
424 if ((*SI)->isLiveIn(Lanai::SR))
428 // Toggle the optional operand to SR.
429 MI->setDesc(get(flagSettingOpcodeVariant(MI->getOpcode())));
430 MI->addRegisterDefined(Lanai::SR);
431 CmpInstr.eraseFromParent();
438 bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI,
439 SmallVectorImpl<MachineOperand> &Cond,
440 unsigned &TrueOp, unsigned &FalseOp,
441 bool &Optimizable) const {
442 assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
447 // 3: Condition code.
450 Cond.push_back(MI.getOperand(3));
455 // Identify instructions that can be folded into a SELECT instruction, and
456 // return the defining instruction.
457 static MachineInstr *canFoldIntoSelect(unsigned Reg,
458 const MachineRegisterInfo &MRI) {
459 if (!Register::isVirtualRegister(Reg))
461 if (!MRI.hasOneNonDBGUse(Reg))
463 MachineInstr *MI = MRI.getVRegDef(Reg);
466 // MI is folded into the SELECT by predicating it.
467 if (!MI->isPredicable())
469 // Check if MI has any non-dead defs or physreg uses. This also detects
470 // predicated instructions which will be reading SR.
471 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
472 const MachineOperand &MO = MI->getOperand(i);
473 // Reject frame index operands.
474 if (MO.isFI() || MO.isCPI() || MO.isJTI())
478 // MI can't have any tied operands, that would conflict with predication.
481 if (Register::isPhysicalRegister(MO.getReg()))
483 if (MO.isDef() && !MO.isDead())
486 bool DontMoveAcrossStores = true;
487 if (!MI->isSafeToMove(/*AliasAnalysis=*/nullptr, DontMoveAcrossStores))
493 LanaiInstrInfo::optimizeSelect(MachineInstr &MI,
494 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
495 bool /*PreferFalse*/) const {
496 assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
497 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
499 bool Invert = !DefMI;
501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
505 // Find new register class to use.
506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
507 Register DestReg = MI.getOperand(0).getReg();
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
509 if (!MRI.constrainRegClass(DestReg, PreviousClass))
512 // Create a new predicated version of DefMI.
513 MachineInstrBuilder NewMI =
514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
516 // Copy all the DefMI operands, excluding its (null) predicate.
517 const MCInstrDesc &DefDesc = DefMI->getDesc();
518 for (unsigned i = 1, e = DefDesc.getNumOperands();
519 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
520 NewMI.add(DefMI->getOperand(i));
522 unsigned CondCode = MI.getOperand(3).getImm();
524 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
526 NewMI.addImm(CondCode);
527 NewMI.copyImplicitOps(MI);
529 // The output register value when the predicate is false is an implicit
530 // register operand tied to the first def. The tie makes the register
531 // allocator ensure the FalseReg is allocated the same register as operand 0.
532 FalseReg.setImplicit();
534 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
536 // Update SeenMIs set: register newly created MI and erase removed DefMI.
537 SeenMIs.insert(NewMI);
538 SeenMIs.erase(DefMI);
540 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
541 // DefMI would be invalid when transferred inside the loop. Checking for a
542 // loop is expensive, but at least remove kill flags if they are in different
544 if (DefMI->getParent() != MI.getParent())
545 NewMI->clearKillInfo();
547 // The caller will erase MI, but not DefMI.
548 DefMI->eraseFromParent();
552 // The analyzeBranch function is used to examine conditional instructions and
553 // remove unnecessary instructions. This method is used by BranchFolder and
554 // IfConverter machine function passes to improve the CFG.
555 // - TrueBlock is set to the destination if condition evaluates true (it is the
556 // nullptr if the destination is the fall-through branch);
557 // - FalseBlock is set to the destination if condition evaluates to false (it
558 // is the nullptr if the branch is unconditional);
559 // - condition is populated with machine operands needed to generate the branch
560 // to insert in insertBranch;
561 // Returns: false if branch could successfully be analyzed.
562 bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
563 MachineBasicBlock *&TrueBlock,
564 MachineBasicBlock *&FalseBlock,
565 SmallVectorImpl<MachineOperand> &Condition,
566 bool AllowModify) const {
567 // Iterator to current instruction being considered.
568 MachineBasicBlock::iterator Instruction = MBB.end();
570 // Start from the bottom of the block and work up, examining the
571 // terminator instructions.
572 while (Instruction != MBB.begin()) {
575 // Skip over debug instructions.
576 if (Instruction->isDebugInstr())
579 // Working from the bottom, when we see a non-terminator
580 // instruction, we're done.
581 if (!isUnpredicatedTerminator(*Instruction))
584 // A terminator that isn't a branch can't easily be handled
586 if (!Instruction->isBranch())
589 // Handle unconditional branches.
590 if (Instruction->getOpcode() == Lanai::BT) {
592 TrueBlock = Instruction->getOperand(0).getMBB();
596 // If the block has any instructions after a branch, delete them.
597 while (std::next(Instruction) != MBB.end()) {
598 std::next(Instruction)->eraseFromParent();
602 FalseBlock = nullptr;
604 // Delete the jump if it's equivalent to a fall-through.
605 if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) {
607 Instruction->eraseFromParent();
608 Instruction = MBB.end();
612 // TrueBlock is used to indicate the unconditional destination.
613 TrueBlock = Instruction->getOperand(0).getMBB();
617 // Handle conditional branches
618 unsigned Opcode = Instruction->getOpcode();
619 if (Opcode != Lanai::BRCC)
620 return true; // Unknown opcode.
622 // Multiple conditional branches are not handled here so only proceed if
623 // there are no conditions enqueued.
624 if (Condition.empty()) {
625 LPCC::CondCode BranchCond =
626 static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm());
628 // TrueBlock is the target of the previously seen unconditional branch.
629 FalseBlock = TrueBlock;
630 TrueBlock = Instruction->getOperand(0).getMBB();
631 Condition.push_back(MachineOperand::CreateImm(BranchCond));
635 // Multiple conditional branches are not handled.
639 // Return false indicating branch successfully analyzed.
643 // reverseBranchCondition - Reverses the branch condition of the specified
644 // condition list, returning false on success and true if it cannot be
646 bool LanaiInstrInfo::reverseBranchCondition(
647 SmallVectorImpl<llvm::MachineOperand> &Condition) const {
648 assert((Condition.size() == 1) &&
649 "Lanai branch conditions should have one component.");
651 LPCC::CondCode BranchCond =
652 static_cast<LPCC::CondCode>(Condition[0].getImm());
653 Condition[0].setImm(getOppositeCondition(BranchCond));
657 // Insert the branch with condition specified in condition and given targets
658 // (TrueBlock and FalseBlock). This function returns the number of machine
659 // instructions inserted.
660 unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
661 MachineBasicBlock *TrueBlock,
662 MachineBasicBlock *FalseBlock,
663 ArrayRef<MachineOperand> Condition,
665 int *BytesAdded) const {
666 // Shouldn't be a fall through.
667 assert(TrueBlock && "insertBranch must not be told to insert a fallthrough");
668 assert(!BytesAdded && "code size not handled");
670 // If condition is empty then an unconditional branch is being inserted.
671 if (Condition.empty()) {
672 assert(!FalseBlock && "Unconditional branch with multiple successors!");
673 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
677 // Else a conditional branch is inserted.
678 assert((Condition.size() == 1) &&
679 "Lanai branch conditions should have one component.");
680 unsigned ConditionalCode = Condition[0].getImm();
681 BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
683 // If no false block, then false behavior is fall through and no branch needs
688 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
692 unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
693 int *BytesRemoved) const {
694 assert(!BytesRemoved && "code size not handled");
696 MachineBasicBlock::iterator Instruction = MBB.end();
699 while (Instruction != MBB.begin()) {
701 if (Instruction->isDebugInstr())
703 if (Instruction->getOpcode() != Lanai::BT &&
704 Instruction->getOpcode() != Lanai::BRCC) {
708 // Remove the branch.
709 Instruction->eraseFromParent();
710 Instruction = MBB.end();
717 unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
718 int &FrameIndex) const {
719 if (MI.getOpcode() == Lanai::LDW_RI)
720 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
721 MI.getOperand(2).getImm() == 0) {
722 FrameIndex = MI.getOperand(1).getIndex();
723 return MI.getOperand(0).getReg();
728 unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
729 int &FrameIndex) const {
730 if (MI.getOpcode() == Lanai::LDW_RI) {
732 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
734 // Check for post-frame index elimination operations
735 SmallVector<const MachineMemOperand *, 1> Accesses;
736 if (hasLoadFromStackSlot(MI, Accesses)){
738 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
746 unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
747 int &FrameIndex) const {
748 if (MI.getOpcode() == Lanai::SW_RI)
749 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
750 MI.getOperand(1).getImm() == 0) {
751 FrameIndex = MI.getOperand(0).getIndex();
752 return MI.getOperand(2).getReg();
757 bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
759 unsigned &Width, const TargetRegisterInfo * /*TRI*/) const {
760 // Handle only loads/stores with base register followed by immediate offset
761 // and with add as ALU op.
762 if (LdSt.getNumOperands() != 4)
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
768 switch (LdSt.getOpcode()) {
789 BaseOp = &LdSt.getOperand(1);
790 Offset = LdSt.getOperand(2).getImm();
791 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
792 "operands of type register.");
796 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt,
797 const MachineOperand *&BaseOp,
799 const TargetRegisterInfo *TRI) const {
800 switch (LdSt.getOpcode()) {
813 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI);