1 //===-- LanaiMemAluCombiner.cpp - Pass to combine memory & ALU operations -===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 // Simple pass to combine memory and ALU operations
10 // The Lanai ISA supports instructions where a load/store modifies the base
11 // register used in the load/store operation. This pass finds suitable
12 // load/store and ALU instructions and combines them into one instruction.
15 // ld [ %r6 -- ], %r12
16 // is a supported instruction that is not currently generated by the instruction
17 // selection pass of this backend. This pass generates these instructions by
22 // in the same machine basic block into one machine instruction.
23 //===----------------------------------------------------------------------===//
25 #include "LanaiAluCode.h"
26 #include "LanaiTargetMachine.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/TargetInstrInfo.h"
33 #include "llvm/Support/CommandLine.h"
36 #define GET_INSTRMAP_INFO
37 #include "LanaiGenInstrInfo.inc"
39 #define DEBUG_TYPE "lanai-mem-alu-combiner"
41 STATISTIC(NumLdStAluCombined, "Number of memory and ALU instructions combined");
43 static llvm::cl::opt<bool> DisableMemAluCombiner(
44 "disable-lanai-mem-alu-combiner", llvm::cl::init(false),
45 llvm::cl::desc("Do not combine ALU and memory operators"),
49 void initializeLanaiMemAluCombinerPass(PassRegistry &);
53 typedef MachineBasicBlock::iterator MbbIterator;
54 typedef MachineFunction::iterator MfIterator;
56 class LanaiMemAluCombiner : public MachineFunctionPass {
59 explicit LanaiMemAluCombiner() : MachineFunctionPass(ID) {
60 initializeLanaiMemAluCombinerPass(*PassRegistry::getPassRegistry());
63 StringRef getPassName() const override {
64 return "Lanai load / store optimization pass";
67 bool runOnMachineFunction(MachineFunction &F) override;
69 MachineFunctionProperties getRequiredProperties() const override {
70 return MachineFunctionProperties().set(
71 MachineFunctionProperties::Property::NoVRegs);
75 MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB,
76 const MbbIterator &MemInstr,
78 void insertMergedInstruction(MachineBasicBlock *BB,
79 const MbbIterator &MemInstr,
80 const MbbIterator &AluInstr, bool Before);
81 bool combineMemAluInBasicBlock(MachineBasicBlock *BB);
83 // Target machine description which we query for register names, data
85 const TargetInstrInfo *TII;
89 char LanaiMemAluCombiner::ID = 0;
91 INITIALIZE_PASS(LanaiMemAluCombiner, DEBUG_TYPE,
92 "Lanai memory ALU combiner pass", false, false)
95 bool isSpls(uint16_t Opcode) { return Lanai::splsIdempotent(Opcode) == Opcode; }
97 // Determine the opcode for the merged instruction created by considering the
98 // old memory operation's opcode and whether the merged opcode will have an
100 unsigned mergedOpcode(unsigned OldOpcode, bool ImmediateOffset) {
105 return Lanai::LDW_RI;
106 return Lanai::LDW_RR;
110 return Lanai::LDHs_RI;
111 return Lanai::LDHs_RR;
115 return Lanai::LDHz_RI;
116 return Lanai::LDHz_RR;
120 return Lanai::LDBs_RI;
121 return Lanai::LDBs_RR;
125 return Lanai::LDBz_RI;
126 return Lanai::LDBz_RR;
135 return Lanai::STB_RI;
136 return Lanai::STB_RR;
140 return Lanai::STH_RI;
141 return Lanai::STH_RR;
147 // Check if the machine instruction has non-volatile memory operands of the type
148 // supported for combining with ALU instructions.
149 bool isNonVolatileMemoryOp(const MachineInstr &MI) {
150 if (!MI.hasOneMemOperand())
153 // Determine if the machine instruction is a supported memory operation by
154 // testing if the computed merge opcode is a valid memory operation opcode.
155 if (mergedOpcode(MI.getOpcode(), false) == 0)
158 const MachineMemOperand *MemOperand = *MI.memoperands_begin();
160 // Don't move volatile memory accesses
161 // TODO: unclear if we need to be as conservative about atomics
162 if (MemOperand->isVolatile() || MemOperand->isAtomic())
168 // Test to see if two machine operands are of the same type. This test is less
169 // strict than the MachineOperand::isIdenticalTo function.
170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
171 if (Op1.getType() != Op2.getType())
174 switch (Op1.getType()) {
175 case MachineOperand::MO_Register:
176 return Op1.getReg() == Op2.getReg();
177 case MachineOperand::MO_Immediate:
178 return Op1.getImm() == Op2.getImm();
184 bool isZeroOperand(const MachineOperand &Op) {
185 return ((Op.isReg() && Op.getReg() == Lanai::R0) ||
186 (Op.isImm() && Op.getImm() == 0));
189 // Determines whether a register is used by an instruction.
190 bool InstrUsesReg(const MbbIterator &Instr, const MachineOperand *Reg) {
191 for (MachineInstr::const_mop_iterator Mop = Instr->operands_begin();
192 Mop != Instr->operands_end(); ++Mop) {
193 if (isSameOperand(*Mop, *Reg))
199 // Converts between machine opcode and AluCode.
200 // Flag using/modifying ALU operations should not be considered for merging and
201 // are omitted from this list.
202 LPAC::AluCode mergedAluCode(unsigned AluOpcode) {
204 case Lanai::ADD_I_LO:
207 case Lanai::SUB_I_LO:
210 case Lanai::AND_I_LO:
216 case Lanai::XOR_I_LO:
228 return LPAC::UNKNOWN;
232 // Insert a new combined memory and ALU operation instruction.
234 // This function builds a new machine instruction using the MachineInstrBuilder
235 // class and inserts it before the memory instruction.
236 void LanaiMemAluCombiner::insertMergedInstruction(MachineBasicBlock *BB,
237 const MbbIterator &MemInstr,
238 const MbbIterator &AluInstr,
240 // Insert new combined load/store + alu operation
241 MachineOperand Dest = MemInstr->getOperand(0);
242 MachineOperand Base = MemInstr->getOperand(1);
243 MachineOperand MemOffset = MemInstr->getOperand(2);
244 MachineOperand AluOffset = AluInstr->getOperand(2);
246 // Abort if ALU offset is not a register or immediate
247 assert((AluOffset.isReg() || AluOffset.isImm()) &&
248 "Unsupported operand type in merge");
250 // Determined merged instructions opcode and ALU code
251 LPAC::AluCode AluOpcode = mergedAluCode(AluInstr->getOpcode());
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm());
254 assert(AluOpcode != LPAC::UNKNOWN && "Unknown ALU code in merging");
255 assert(NewOpc != 0 && "Unknown merged node opcode");
257 // Build and insert new machine instruction
258 MachineInstrBuilder InstrBuilder =
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true));
261 InstrBuilder.addReg(Base.getReg(), getKillRegState(true));
263 // Add offset to machine instruction
264 if (AluOffset.isReg())
265 InstrBuilder.addReg(AluOffset.getReg());
266 else if (AluOffset.isImm())
267 InstrBuilder.addImm(AluOffset.getImm());
269 llvm_unreachable("Unsupported ld/st ALU merge.");
271 // Create a pre-op if the ALU operation preceded the memory operation or the
272 // MemOffset is non-zero (i.e. the memory value should be adjusted before
273 // accessing it), else create a post-op.
274 if (Before || !isZeroOperand(MemOffset))
275 InstrBuilder.addImm(LPAC::makePreOp(AluOpcode));
277 InstrBuilder.addImm(LPAC::makePostOp(AluOpcode));
279 // Transfer memory operands.
280 InstrBuilder.setMemRefs(MemInstr->memoperands());
283 // Function determines if ALU operation (in alu_iter) can be combined with
284 // a load/store with base and offset.
285 bool isSuitableAluInstr(bool IsSpls, const MbbIterator &AluIter,
286 const MachineOperand &Base,
287 const MachineOperand &Offset) {
288 // ALU operations have 3 operands
289 if (AluIter->getNumOperands() != 3)
292 MachineOperand &Dest = AluIter->getOperand(0);
293 MachineOperand &Op1 = AluIter->getOperand(1);
294 MachineOperand &Op2 = AluIter->getOperand(2);
296 // Only match instructions using the base register as destination and with the
297 // base and first operand equal
298 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1))
302 // It is not a match if the 2nd operand in the ALU operation is an
303 // immediate but the ALU operation is not an addition.
304 if (AluIter->getOpcode() != Lanai::ADD_I_LO)
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0)
310 if (Offset.isImm() &&
311 ((Offset.getImm() == 0 &&
312 // Check that the Op2 would fit in the immediate field of the
314 ((IsSpls && isInt<10>(Op2.getImm())) ||
315 (!IsSpls && isInt<16>(Op2.getImm())))) ||
316 Offset.getImm() == Op2.getImm()))
318 } else if (Op2.isReg()) {
319 // The Offset and 2nd operand are both registers and equal
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg())
323 // Only consider operations with register or immediate values
329 MbbIterator LanaiMemAluCombiner::findClosestSuitableAluInstr(
330 MachineBasicBlock *BB, const MbbIterator &MemInstr, const bool Decrement) {
331 MachineOperand *Base = &MemInstr->getOperand(1);
332 MachineOperand *Offset = &MemInstr->getOperand(2);
333 bool IsSpls = isSpls(MemInstr->getOpcode());
335 MbbIterator First = MemInstr;
336 MbbIterator Last = Decrement ? BB->begin() : BB->end();
338 while (First != Last) {
339 Decrement ? --First : ++First;
344 // Skip over debug instructions
345 if (First->isDebugInstr())
348 if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) {
352 // Usage of the base or offset register is not a form suitable for merging.
354 if (InstrUsesReg(First, Base))
356 if (Offset->isReg() && InstrUsesReg(First, Offset))
364 bool LanaiMemAluCombiner::combineMemAluInBasicBlock(MachineBasicBlock *BB) {
365 bool Modified = false;
367 MbbIterator MBBIter = BB->begin(), End = BB->end();
368 while (MBBIter != End) {
369 bool IsMemOp = isNonVolatileMemoryOp(*MBBIter);
372 MachineOperand AluOperand = MBBIter->getOperand(3);
373 unsigned int DestReg = MBBIter->getOperand(0).getReg(),
374 BaseReg = MBBIter->getOperand(1).getReg();
375 assert(AluOperand.isImm() && "Unexpected memory operator type");
376 LPAC::AluCode AluOpcode = static_cast<LPAC::AluCode>(AluOperand.getImm());
378 // Skip memory operations that already modify the base register or if
379 // the destination and base register are the same
380 if (!LPAC::modifiesOp(AluOpcode) && DestReg != BaseReg) {
381 for (int Inc = 0; Inc <= 1; ++Inc) {
382 MbbIterator AluIter =
383 findClosestSuitableAluInstr(BB, MBBIter, Inc == 0);
384 if (AluIter != MBBIter) {
385 insertMergedInstruction(BB, MBBIter, AluIter, Inc == 0);
387 ++NumLdStAluCombined;
390 // Erase the matching ALU instruction
392 // Erase old load/store instruction
393 BB->erase(MBBIter++);
407 // Driver function that iterates over the machine basic building blocks of a
409 bool LanaiMemAluCombiner::runOnMachineFunction(MachineFunction &MF) {
410 if (DisableMemAluCombiner)
413 TII = MF.getSubtarget<LanaiSubtarget>().getInstrInfo();
414 bool Modified = false;
415 for (MfIterator MFI = MF.begin(); MFI != MF.end(); ++MFI) {
416 Modified |= combineMemAluInBasicBlock(&*MFI);
422 FunctionPass *llvm::createLanaiMemAluCombinerPass() {
423 return new LanaiMemAluCombiner();