1 //===-- M68kAsmParser.cpp - Parse M68k assembly to MCInst instructions ----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "M68kInstrInfo.h"
10 #include "M68kRegisterInfo.h"
11 #include "TargetInfo/M68kTargetInfo.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCParser/MCAsmLexer.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/TargetRegistry.h"
22 #define DEBUG_TYPE "m68k-asm-parser"
26 static cl::opt<bool> RegisterPrefixOptional(
27 "m68k-register-prefix-optional", cl::Hidden,
28 cl::desc("Enable specifying registers without the % prefix"),
32 /// Parses M68k assembly from a stream.
33 class M68kAsmParser : public MCTargetAsmParser {
34 const MCSubtargetInfo &STI;
36 const MCRegisterInfo *MRI;
38 #define GET_ASSEMBLER_HEADER
39 #include "M68kGenAsmMatcher.inc"
41 // Helpers for Match&Emit.
42 bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
43 const uint64_t &ErrorInfo);
44 bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
45 bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
46 bool parseRegisterName(MCRegister &RegNo, SMLoc Loc, StringRef RegisterName);
47 ParseStatus parseRegister(MCRegister &RegNo);
53 ParseStatus parseImm(OperandVector &Operands);
54 ParseStatus parseMemOp(OperandVector &Operands);
55 ParseStatus parseRegOrMoveMask(OperandVector &Operands);
58 M68kAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
59 const MCInstrInfo &MII, const MCTargetOptions &Options)
60 : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
61 MCAsmParserExtension::Initialize(Parser);
62 MRI = getContext().getRegisterInfo();
64 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
67 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
68 unsigned Kind) override;
69 bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
70 SMLoc &EndLoc) override;
71 OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
72 SMLoc &EndLoc) override;
73 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
74 SMLoc NameLoc, OperandVector &Operands) override;
75 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
76 OperandVector &Operands, MCStreamer &Out,
78 bool MatchingInlineAsm) override;
89 RegIndirectDisplacement,
90 RegIndirectDisplacementIndex,
93 // These variables are used for the following forms:
95 // RegMask: RegMask (as register mask)
97 // RegIndirect: (%OuterReg)
98 // RegPostIncrement: (%OuterReg)+
99 // RegPreDecrement: -(%OuterReg)
100 // RegIndirectDisplacement: OuterDisp(%OuterReg)
101 // RegIndirectDisplacementIndex:
102 // OuterDisp(%OuterReg, %InnerReg.Size * Scale, InnerDisp)
107 const MCExpr *OuterDisp;
108 const MCExpr *InnerDisp;
115 M68kMemOp(Kind Op) : Op(Op) {}
117 void print(raw_ostream &OS) const;
120 /// An parsed M68k assembly operand.
121 class M68kOperand : public MCParsedAsmOperand {
122 typedef MCParsedAsmOperand Base;
139 template <unsigned N> bool isAddrN() const;
142 M68kOperand(KindTy Kind, SMLoc Start, SMLoc End)
143 : Base(), Kind(Kind), Start(Start), End(End) {}
145 SMLoc getStartLoc() const override { return Start; }
146 SMLoc getEndLoc() const override { return End; }
148 void print(raw_ostream &OS) const override;
150 bool isMem() const override { return false; }
151 bool isMemOp() const { return Kind == KindTy::MemOp; }
153 static void addExpr(MCInst &Inst, const MCExpr *Expr);
156 bool isReg() const override;
159 bool isFPDReg() const;
160 unsigned getReg() const override;
161 void addRegOperands(MCInst &Inst, unsigned N) const;
163 static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
167 bool isToken() const override;
168 StringRef getToken() const;
169 static std::unique_ptr<M68kOperand> createToken(StringRef Token, SMLoc Start,
173 bool isImm() const override;
174 void addImmOperands(MCInst &Inst, unsigned N) const;
176 static std::unique_ptr<M68kOperand> createImm(const MCExpr *Expr, SMLoc Start,
179 // Imm for TRAP instruction
180 bool isTrapImm() const;
181 // Imm for BKPT instruction
182 bool isBkptImm() const;
185 bool isMoveMask() const;
186 void addMoveMaskOperands(MCInst &Inst, unsigned N) const;
190 bool isAddr8() const { return isAddrN<8>(); }
191 bool isAddr16() const { return isAddrN<16>(); }
192 bool isAddr32() const { return isAddrN<32>(); }
193 void addAddrOperands(MCInst &Inst, unsigned N) const;
197 void addARIOperands(MCInst &Inst, unsigned N) const;
201 void addARIDOperands(MCInst &Inst, unsigned N) const;
205 void addARIIOperands(MCInst &Inst, unsigned N) const;
208 bool isARIPD() const;
209 void addARIPDOperands(MCInst &Inst, unsigned N) const;
212 bool isARIPI() const;
213 void addARIPIOperands(MCInst &Inst, unsigned N) const;
217 void addPCDOperands(MCInst &Inst, unsigned N) const;
221 void addPCIOperands(MCInst &Inst, unsigned N) const;
224 } // end anonymous namespace.
226 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kAsmParser() {
227 RegisterMCAsmParser<M68kAsmParser> X(getTheM68kTarget());
230 #define GET_REGISTER_MATCHER
231 #define GET_MATCHER_IMPLEMENTATION
232 #include "M68kGenAsmMatcher.inc"
234 static inline unsigned getRegisterByIndex(unsigned RegisterIndex) {
235 static unsigned RegistersByIndex[] = {
236 M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
237 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
238 M68k::A4, M68k::A5, M68k::A6, M68k::SP, M68k::FP0, M68k::FP1,
239 M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7};
240 assert(RegisterIndex <=
241 sizeof(RegistersByIndex) / sizeof(RegistersByIndex[0]));
242 return RegistersByIndex[RegisterIndex];
245 static inline unsigned getRegisterIndex(unsigned Register) {
246 if (Register >= M68k::D0 && Register <= M68k::D7)
247 return Register - M68k::D0;
248 if (Register >= M68k::A0 && Register <= M68k::A6)
249 return Register - M68k::A0 + 8;
250 if (Register >= M68k::FP0 && Register <= M68k::FP7)
251 return Register - M68k::FP0 + 16;
255 // SP is sadly not contiguous with the rest of the An registers
263 llvm_unreachable("unexpected register number");
267 void M68kMemOp::print(raw_ostream &OS) const {
273 OS << "RegMask(" << format("%04x", RegMask) << ")";
276 OS << '%' << OuterReg;
278 case Kind::RegIndirect:
279 OS << "(%" << OuterReg << ')';
281 case Kind::RegPostIncrement:
282 OS << "(%" << OuterReg << ")+";
284 case Kind::RegPreDecrement:
285 OS << "-(%" << OuterReg << ")";
287 case Kind::RegIndirectDisplacement:
288 OS << OuterDisp << "(%" << OuterReg << ")";
290 case Kind::RegIndirectDisplacementIndex:
291 OS << OuterDisp << "(%" << OuterReg << ", " << InnerReg << "." << Size
292 << ", " << InnerDisp << ")";
297 void M68kOperand::addExpr(MCInst &Inst, const MCExpr *Expr) {
298 if (auto Const = dyn_cast<MCConstantExpr>(Expr)) {
299 Inst.addOperand(MCOperand::createImm(Const->getValue()));
303 Inst.addOperand(MCOperand::createExpr(Expr));
307 bool M68kOperand::isReg() const {
308 return Kind == KindTy::MemOp && MemOp.Op == M68kMemOp::Kind::Reg;
311 unsigned M68kOperand::getReg() const {
313 return MemOp.OuterReg;
316 void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const {
317 assert(isReg() && "wrong operand kind");
318 assert((N == 1) && "can only handle one register operand");
320 Inst.addOperand(MCOperand::createReg(getReg()));
323 std::unique_ptr<M68kOperand> M68kOperand::createMemOp(M68kMemOp MemOp,
324 SMLoc Start, SMLoc End) {
325 auto Op = std::make_unique<M68kOperand>(KindTy::MemOp, Start, End);
331 bool M68kOperand::isToken() const { return Kind == KindTy::Token; }
332 StringRef M68kOperand::getToken() const {
337 std::unique_ptr<M68kOperand> M68kOperand::createToken(StringRef Token,
338 SMLoc Start, SMLoc End) {
339 auto Op = std::make_unique<M68kOperand>(KindTy::Token, Start, End);
345 bool M68kOperand::isImm() const { return Kind == KindTy::Imm; }
346 void M68kOperand::addImmOperands(MCInst &Inst, unsigned N) const {
347 assert(isImm() && "wrong operand kind");
348 assert((N == 1) && "can only handle one register operand");
350 M68kOperand::addExpr(Inst, Expr);
353 std::unique_ptr<M68kOperand> M68kOperand::createImm(const MCExpr *Expr,
354 SMLoc Start, SMLoc End) {
355 auto Op = std::make_unique<M68kOperand>(KindTy::Imm, Start, End);
360 bool M68kOperand::isTrapImm() const {
362 if (!isImm() || !Expr->evaluateAsAbsolute(Value))
365 return isUInt<4>(Value);
368 bool M68kOperand::isBkptImm() const {
370 if (!isImm() || !Expr->evaluateAsAbsolute(Value))
373 return isUInt<3>(Value);
377 bool M68kOperand::isMoveMask() const {
381 if (MemOp.Op == M68kMemOp::Kind::RegMask)
384 if (MemOp.Op != M68kMemOp::Kind::Reg)
387 // Only regular address / data registers are allowed to be used
388 // in register masks.
389 return getRegisterIndex(MemOp.OuterReg) < 16;
392 void M68kOperand::addMoveMaskOperands(MCInst &Inst, unsigned N) const {
393 assert(isMoveMask() && "wrong operand kind");
394 assert((N == 1) && "can only handle one immediate operand");
396 uint16_t MoveMask = MemOp.RegMask;
397 if (MemOp.Op == M68kMemOp::Kind::Reg)
398 MoveMask = 1 << getRegisterIndex(MemOp.OuterReg);
400 Inst.addOperand(MCOperand::createImm(MoveMask));
404 bool M68kOperand::isAddr() const {
405 return isMemOp() && MemOp.Op == M68kMemOp::Kind::Addr;
407 // TODO: Maybe we can also store the size of OuterDisp
409 template <unsigned N> bool M68kOperand::isAddrN() const {
412 if (MemOp.OuterDisp->evaluateAsAbsolute(Res))
413 return isInt<N>(Res);
418 void M68kOperand::addAddrOperands(MCInst &Inst, unsigned N) const {
419 M68kOperand::addExpr(Inst, MemOp.OuterDisp);
423 bool M68kOperand::isARI() const {
424 return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirect &&
425 M68k::AR32RegClass.contains(MemOp.OuterReg);
427 void M68kOperand::addARIOperands(MCInst &Inst, unsigned N) const {
428 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
432 bool M68kOperand::isARID() const {
433 return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
434 M68k::AR32RegClass.contains(MemOp.OuterReg);
436 void M68kOperand::addARIDOperands(MCInst &Inst, unsigned N) const {
437 M68kOperand::addExpr(Inst, MemOp.OuterDisp);
438 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
442 bool M68kOperand::isARII() const {
444 MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
445 M68k::AR32RegClass.contains(MemOp.OuterReg);
447 void M68kOperand::addARIIOperands(MCInst &Inst, unsigned N) const {
448 M68kOperand::addExpr(Inst, MemOp.OuterDisp);
449 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
450 Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
454 bool M68kOperand::isARIPD() const {
455 return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPreDecrement &&
456 M68k::AR32RegClass.contains(MemOp.OuterReg);
458 void M68kOperand::addARIPDOperands(MCInst &Inst, unsigned N) const {
459 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
463 bool M68kOperand::isARIPI() const {
464 return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPostIncrement &&
465 M68k::AR32RegClass.contains(MemOp.OuterReg);
467 void M68kOperand::addARIPIOperands(MCInst &Inst, unsigned N) const {
468 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
472 bool M68kOperand::isPCD() const {
473 return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
474 MemOp.OuterReg == M68k::PC;
476 void M68kOperand::addPCDOperands(MCInst &Inst, unsigned N) const {
477 M68kOperand::addExpr(Inst, MemOp.OuterDisp);
481 bool M68kOperand::isPCI() const {
483 MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
484 MemOp.OuterReg == M68k::PC;
486 void M68kOperand::addPCIOperands(MCInst &Inst, unsigned N) const {
487 M68kOperand::addExpr(Inst, MemOp.OuterDisp);
488 Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
491 static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
492 bool SP, bool FPDR = false) {
531 llvm_unreachable("unexpected register type");
536 bool M68kOperand::isAReg() const {
537 return isReg() && checkRegisterClass(getReg(),
539 /*Address=*/true, /*SP=*/true);
542 bool M68kOperand::isDReg() const {
543 return isReg() && checkRegisterClass(getReg(),
545 /*Address=*/false, /*SP=*/false);
548 bool M68kOperand::isFPDReg() const {
549 return isReg() && checkRegisterClass(getReg(),
551 /*Address=*/false, /*SP=*/false,
555 unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
557 M68kOperand &Operand = (M68kOperand &)Op;
562 if (Operand.isReg() &&
563 checkRegisterClass(Operand.getReg(), true, true, true)) {
564 return Match_Success;
570 if (Operand.isReg() &&
571 checkRegisterClass(Operand.getReg(), false, true, true)) {
572 return Match_Success;
577 if (Operand.isReg() &&
578 checkRegisterClass(Operand.getReg(), false, true, false)) {
579 return Match_Success;
586 if (Operand.isReg() &&
587 checkRegisterClass(Operand.getReg(), true, false, false)) {
588 return Match_Success;
593 if (Operand.isReg() &&
594 ((Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) {
595 return Match_Success;
600 if (Operand.isReg() &&
601 ((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1))) {
602 return Match_Success;
607 if (Operand.isReg() &&
608 ((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1) ||
609 (Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) {
610 return Match_Success;
615 return Match_InvalidOperand;
618 bool M68kAsmParser::parseRegisterName(MCRegister &RegNo, SMLoc Loc,
619 StringRef RegisterName) {
620 auto RegisterNameLower = RegisterName.lower();
623 if (RegisterNameLower == "ccr") {
628 // Parse simple general-purpose registers.
629 if (RegisterNameLower.size() == 2) {
631 switch (RegisterNameLower[0]) {
634 if (isdigit(RegisterNameLower[1])) {
635 unsigned IndexOffset = (RegisterNameLower[0] == 'a') ? 8 : 0;
636 unsigned RegIndex = (unsigned)(RegisterNameLower[1] - '0');
638 RegNo = getRegisterByIndex(IndexOffset + RegIndex);
646 if (RegisterNameLower[1] == 'p') {
649 } else if (RegisterNameLower[1] == 'r') {
656 if (RegisterNameLower[1] == 'c') {
662 } else if (StringRef(RegisterNameLower).starts_with("fp") &&
663 RegisterNameLower.size() > 2) {
664 // Floating point data register.
665 auto RegIndex = unsigned(RegisterNameLower[2] - '0');
666 if (RegIndex >= 8 || RegisterNameLower.size() > 3)
668 RegNo = getRegisterByIndex(16 + RegIndex);
675 ParseStatus M68kAsmParser::parseRegister(MCRegister &RegNo) {
676 bool HasPercent = false;
677 AsmToken PercentToken;
679 LLVM_DEBUG(dbgs() << "parseRegister "; getTok().dump(dbgs()); dbgs() << "\n");
681 if (getTok().is(AsmToken::Percent)) {
683 PercentToken = Lex();
684 } else if (!RegisterPrefixOptional.getValue()) {
685 return ParseStatus::NoMatch;
688 if (!Parser.getTok().is(AsmToken::Identifier)) {
690 getLexer().UnLex(PercentToken);
692 return ParseStatus::NoMatch;
695 auto RegisterName = Parser.getTok().getString();
696 if (!parseRegisterName(RegNo, Parser.getLexer().getLoc(), RegisterName)) {
698 getLexer().UnLex(PercentToken);
700 return ParseStatus::NoMatch;
704 return ParseStatus::Success;
707 bool M68kAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
709 auto Result = tryParseRegister(RegNo, StartLoc, EndLoc);
710 if (Result != MatchOperand_Success) {
711 return Error(StartLoc, "expected register");
717 OperandMatchResultTy M68kAsmParser::tryParseRegister(MCRegister &RegNo,
720 StartLoc = getLexer().getLoc();
721 ParseStatus Result = parseRegister(RegNo);
722 EndLoc = getLexer().getLoc();
726 bool M68kAsmParser::isExpr() {
727 switch (Parser.getTok().getKind()) {
728 case AsmToken::Identifier:
729 case AsmToken::Integer:
731 case AsmToken::Minus:
732 return getLexer().peekTok().getKind() == AsmToken::Integer;
739 ParseStatus M68kAsmParser::parseImm(OperandVector &Operands) {
740 if (getLexer().isNot(AsmToken::Hash))
741 return ParseStatus::NoMatch;
742 SMLoc Start = getLexer().getLoc();
748 if (getParser().parseExpression(Expr, End))
749 return ParseStatus::Failure;
751 Operands.push_back(M68kOperand::createImm(Expr, Start, End));
752 return ParseStatus::Success;
755 ParseStatus M68kAsmParser::parseMemOp(OperandVector &Operands) {
756 SMLoc Start = getLexer().getLoc();
760 // Check for a plain register or register mask.
761 ParseStatus Result = parseRegOrMoveMask(Operands);
762 if (!Result.isNoMatch())
765 // Check for pre-decrement & outer displacement.
766 bool HasDisplacement = false;
767 if (getLexer().is(AsmToken::Minus)) {
770 } else if (isExpr()) {
771 if (Parser.parseExpression(MemOp.OuterDisp))
772 return ParseStatus::Failure;
773 HasDisplacement = true;
776 if (getLexer().isNot(AsmToken::LParen)) {
777 if (HasDisplacement) {
778 MemOp.Op = M68kMemOp::Kind::Addr;
780 M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
781 return ParseStatus::Success;
784 return Error(getLexer().getLoc(), "expected (");
786 return ParseStatus::NoMatch;
790 // Check for constant dereference & MIT-style displacement
791 if (!HasDisplacement && isExpr()) {
792 if (Parser.parseExpression(MemOp.OuterDisp))
793 return ParseStatus::Failure;
794 HasDisplacement = true;
796 // If we're not followed by a comma, we're a constant dereference.
797 if (getLexer().isNot(AsmToken::Comma)) {
798 MemOp.Op = M68kMemOp::Kind::Addr;
800 M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
801 return ParseStatus::Success;
807 Result = parseRegister(MemOp.OuterReg);
808 if (Result.isFailure())
809 return ParseStatus::Failure;
811 if (!Result.isSuccess())
812 return Error(getLexer().getLoc(), "expected register");
815 bool HasIndex = false;
816 if (Parser.getTok().is(AsmToken::Comma)) {
819 Result = parseRegister(MemOp.InnerReg);
820 if (Result.isFailure())
823 if (Result.isNoMatch())
824 return Error(getLexer().getLoc(), "expected register");
826 // TODO: parse size, scale and inner displacement.
829 MemOp.InnerDisp = MCConstantExpr::create(0, Parser.getContext(), true, 4);
833 if (Parser.getTok().isNot(AsmToken::RParen))
834 return Error(getLexer().getLoc(), "expected )");
838 if (!IsPD && Parser.getTok().is(AsmToken::Plus)) {
843 SMLoc End = getLexer().getLoc();
845 unsigned OpCount = IsPD + IsPI + (HasIndex || HasDisplacement);
847 return Error(Start, "only one of post-increment, pre-decrement or "
848 "displacement can be used");
851 MemOp.Op = M68kMemOp::Kind::RegPreDecrement;
853 MemOp.Op = M68kMemOp::Kind::RegPostIncrement;
854 } else if (HasIndex) {
855 MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacementIndex;
856 } else if (HasDisplacement) {
857 MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacement;
859 MemOp.Op = M68kMemOp::Kind::RegIndirect;
862 Operands.push_back(M68kOperand::createMemOp(MemOp, Start, End));
863 return ParseStatus::Success;
866 ParseStatus M68kAsmParser::parseRegOrMoveMask(OperandVector &Operands) {
867 SMLoc Start = getLexer().getLoc();
868 M68kMemOp MemOp(M68kMemOp::Kind::RegMask);
872 bool IsFirstRegister =
873 (MemOp.Op == M68kMemOp::Kind::RegMask) && (MemOp.RegMask == 0);
875 MCRegister FirstRegister;
876 ParseStatus Result = parseRegister(FirstRegister);
877 if (IsFirstRegister && Result.isNoMatch())
878 return ParseStatus::NoMatch;
879 if (!Result.isSuccess())
880 return Error(getLexer().getLoc(), "expected start register");
882 MCRegister LastRegister = FirstRegister;
883 if (parseOptionalToken(AsmToken::Minus)) {
884 Result = parseRegister(LastRegister);
885 if (!Result.isSuccess())
886 return Error(getLexer().getLoc(), "expected end register");
889 unsigned FirstRegisterIndex = getRegisterIndex(FirstRegister);
890 unsigned LastRegisterIndex = getRegisterIndex(LastRegister);
892 uint16_t NumNewBits = LastRegisterIndex - FirstRegisterIndex + 1;
893 uint16_t NewMaskBits = ((1 << NumNewBits) - 1) << FirstRegisterIndex;
895 if (IsFirstRegister && (FirstRegister == LastRegister)) {
896 // First register range is a single register, simplify to just Reg
897 // so that it matches more operands.
898 MemOp.Op = M68kMemOp::Kind::Reg;
899 MemOp.OuterReg = FirstRegister;
901 if (MemOp.Op == M68kMemOp::Kind::Reg) {
902 // This is the second register being specified - expand the Reg operand
903 // into a mask first.
904 MemOp.Op = M68kMemOp::Kind::RegMask;
905 MemOp.RegMask = 1 << getRegisterIndex(MemOp.OuterReg);
907 if (MemOp.RegMask == 0)
908 return Error(getLexer().getLoc(),
909 "special registers cannot be used in register masks");
912 if ((FirstRegisterIndex >= 16) || (LastRegisterIndex >= 16))
913 return Error(getLexer().getLoc(),
914 "special registers cannot be used in register masks");
916 if (NewMaskBits & MemOp.RegMask)
917 return Error(getLexer().getLoc(), "conflicting masked registers");
919 MemOp.RegMask |= NewMaskBits;
922 if (!parseOptionalToken(AsmToken::Slash))
927 M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
928 return ParseStatus::Success;
931 void M68kAsmParser::eatComma() {
932 if (Parser.getTok().is(AsmToken::Comma)) {
937 bool M68kAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
938 SMLoc NameLoc, OperandVector &Operands) {
939 SMLoc Start = getLexer().getLoc();
940 Operands.push_back(M68kOperand::createToken(Name, Start, Start));
943 while (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
950 ParseStatus MatchResult = MatchOperandParserImpl(Operands, Name);
951 if (MatchResult.isSuccess())
954 // Add custom operand formats here...
955 SMLoc Loc = getLexer().getLoc();
956 Parser.eatToEndOfStatement();
957 return Error(Loc, "unexpected token parsing operands");
960 // Eat EndOfStatement.
965 bool M68kAsmParser::invalidOperand(SMLoc const &Loc,
966 OperandVector const &Operands,
967 uint64_t const &ErrorInfo) {
968 SMLoc ErrorLoc = Loc;
969 char const *Diag = 0;
971 if (ErrorInfo != ~0U) {
972 if (ErrorInfo >= Operands.size()) {
973 Diag = "too few operands for instruction.";
975 auto const &Op = (M68kOperand const &)*Operands[ErrorInfo];
976 if (Op.getStartLoc() != SMLoc()) {
977 ErrorLoc = Op.getStartLoc();
983 Diag = "invalid operand for instruction";
986 return Error(ErrorLoc, Diag);
989 bool M68kAsmParser::missingFeature(llvm::SMLoc const &Loc,
990 uint64_t const &ErrorInfo) {
991 return Error(Loc, "instruction requires a CPU feature not currently enabled");
994 bool M68kAsmParser::emit(MCInst &Inst, SMLoc const &Loc,
995 MCStreamer &Out) const {
997 Out.emitInstruction(Inst, STI);
1002 bool M68kAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
1003 OperandVector &Operands,
1005 uint64_t &ErrorInfo,
1006 bool MatchingInlineAsm) {
1008 unsigned MatchResult =
1009 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1011 switch (MatchResult) {
1013 return emit(Inst, Loc, Out);
1014 case Match_MissingFeature:
1015 return missingFeature(Loc, ErrorInfo);
1016 case Match_InvalidOperand:
1017 return invalidOperand(Loc, Operands, ErrorInfo);
1018 case Match_MnemonicFail:
1019 return Error(Loc, "invalid instruction");
1025 void M68kOperand::print(raw_ostream &OS) const {
1027 case KindTy::Invalid:
1032 OS << "token '" << Token << "'";
1037 Expr->evaluateAsAbsolute(Value);
1038 OS << "immediate " << Value;